From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lj1-f175.google.com (mail-lj1-f175.google.com [209.85.208.175]) by mx.groups.io with SMTP id smtpd.web08.1629.1628633051394230223 for ; Tue, 10 Aug 2021 15:04:12 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=A4ZX5NZ9; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.208.175, mailfrom: mw@semihalf.com) Received: by mail-lj1-f175.google.com with SMTP id m9so986564ljp.7 for ; Tue, 10 Aug 2021 15:04:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=YEN+x4PnySJlZZckPidzzwH8ppcV8tr3XfXyHstPG2M=; b=A4ZX5NZ9b79P1itGuhftapvHdeGrT8gDSaaOI9OdNkRucCHS2BG+ST0wmGHo9+3vKF HnyV8LRJZitRYoJtCUJ99xa/45ZcB67y62Io4WfCI66zL1ztqNiBHKRfeOpxWid7NcNc pSAjINeZRuiO6kzWF29YijjxTUIuNlpZkecGAaCUKa/Tepn7tOMqOYpVjzOjpfKDTrNC t65e/u26n5cmG0gV5Tqxpv4YbZ4E1tsh/4b7vxPpa2cWmJjj5520Bfn84iibPGZqAXFE /11oLV+pCC3HFs27aGUd2D5gfZTgdTwfwu+sOer9HZIQVsETsqaDAbUU7uI1WAJeY/uY BfVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=YEN+x4PnySJlZZckPidzzwH8ppcV8tr3XfXyHstPG2M=; b=qa8+1virmAyPhauzF/80t2rJMwrHmCyrUw2on4ts1zWF9fDNcpLcFZhXEPHVDcOPCV Cef/rZHULtNDxUzb9BeoyUGLgRo0W1AhKQXsZ9l39p7uIhn7icKd6JQJ8joXdO8qT5sU 9YpdJZZe+79IIhrPCG443+udIVenHw8ZJIkiTEAWnFEUYUY1Orxam0cALMkiHTkibfFo ZzKJ/hASulARwccVwHymtX05YvjZnYY3pCsSI10gex0hyN1RWr1FY5M1otFawcgzzb9M 7/wePfFjPApIjLBp0jdPf2hlJHmTo1Dr2LoXnuDH4kferWrdRUVA9gLfZPIj11VHFlqj 3JCw== X-Gm-Message-State: AOAM531QZYSLruK1IN2u0vZNsofaZGrni+zVc+Bhw7CvyhgjqW4yULfq FPRieOP0RIpXOf1Q0nT1Iu5uQpIMfxW+8dyE X-Google-Smtp-Source: ABdhPJy9ui/UV36lPfZelEUt/SH9tsZbg+dA/6a96qh7eWgLSJPRf8VcSjkEGfmCwCQH/SEvCbdbhg== X-Received: by 2002:a2e:bc1a:: with SMTP id b26mr20936649ljf.132.1628633049445; Tue, 10 Aug 2021 15:04:09 -0700 (PDT) Return-Path: Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id y3sm1984374ljj.121.2021.08.10.15.04.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Aug 2021 15:04:08 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, Samer.El-Haj-Mahmoud@arm.com, sunny.Wang@arm.com, gjb@semihalf.com, upstream@semihalf.com, Marcin Wojtas Subject: [edk2-platforms PATCH v2] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables Date: Wed, 11 Aug 2021 00:04:03 +0200 Message-Id: <20210810220403.3504123-1-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable BBR 1.0 spec says that _STA is required for each device in DSDT or SSDT. Fix that for all platforms with the Marvell SoC's. Signed-off-by: Marcin Wojtas --- Changelog: v1->v2: * Rebase on top of tree Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 56 ++++++= +++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 76 ++++++= ++++++++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 76 ++++++= ++++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 12 ++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 60 ++++++= ++++++++++ 5 files changed, 280 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl b/= Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl index 345c1e4dd6..88e38efeeb 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA7K", 3) {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x000) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU1)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x001) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU2)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x100) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU3)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x101) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D =0D Device (AHC0)=0D @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A7K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CLS, Package (0x03) // _CLS: Class Code=0D {=0D 0x01,=0D @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A7K", 3) Name (_HID, "MRVL0002") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -96,6 +120,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA7K", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -123,6 +151,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -142,6 +174,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -160,6 +196,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) {=0D Name (_HID, "MRVL0001") // _HID: H= ardware ID=0D Name (_CID, "HISI0031") // _CID: C= ompatible ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress=0D Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings=0D {=0D @@ -186,6 +226,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) {=0D Name (_HID, "MRVL0100") // _HID: H= ardware ID=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite,=0D @@ -208,6 +252,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D Name (_CCA, 0x01) // Cache-c= oherent controller=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)=0D @@ -286,6 +334,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) {=0D Name (_HID, "PRP0001") // _HID= : Hardware ID=0D Name (_UID, 0x00) // _UID= : Unique ID=0D + Method (_STA) // _STA= : Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)=0D @@ -312,6 +364,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_SEG, 0x00) // _SEG: PCI Segment=0D Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_PRT, Package () // _PRT: PCI Routing Table=0D {=0D Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/= Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl index 91401c74c8..77d3aebaf1 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x000) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU1)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x001) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU2)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x100) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU3)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x101) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D =0D Device (AHC0)=0D @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A8K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CLS, Package (0x03) // _CLS: Class Code=0D {=0D 0x01,=0D @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A8K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CLS, Package (0x03) // _CLS: Class Code=0D {=0D 0x01,=0D @@ -92,6 +116,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) Name (_HID, "MRVL0002") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -122,6 +150,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -151,6 +183,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -170,6 +206,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x02) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -207,6 +251,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "MRVL0001") // _HID: H= ardware ID=0D Name (_CID, "HISI0031") // _CID: C= ompatible ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress=0D Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings=0D {=0D @@ -233,6 +281,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "MRVL0100") // _HID: H= ardware ID=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite,=0D @@ -251,6 +303,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D Name (_CCA, 0x01) // Cache-c= oherent controller=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)=0D @@ -309,6 +365,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "MRVL0100") // _HID: H= ardware ID=0D Name (_UID, 0x01) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite,=0D @@ -327,6 +387,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D Name (_CCA, 0x01) // Cache-c= oherent controller=0D Name (_UID, 0x01) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)=0D @@ -385,6 +449,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "PRP0001") // _HID= : Hardware ID=0D Name (_UID, 0x00) // _UID= : Unique ID=0D + Method (_STA) // _STA= : Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)=0D @@ -405,6 +473,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "PRP0001") // _HID= : Hardware ID=0D Name (_UID, 0x01) // _UID= : Unique ID=0D + Method (_STA) // _STA= : Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xF4760000, 0x7D)=0D @@ -431,6 +503,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_SEG, 0x00) // _SEG: PCI Segment=0D Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_PRT, Package () // _PRT: PCI Routing Table=0D {=0D Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl= b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl index 7931dc3ef8..a7d1c76e07 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x000) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU1)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x001) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU2)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x100) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU3)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x101) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D =0D Device (AHC0)=0D @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A8K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CLS, Package (0x03) // _CLS: Class Code=0D {=0D 0x01,=0D @@ -92,6 +112,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) Name (_HID, "MRVL0002") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -123,6 +147,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -151,6 +179,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -170,6 +202,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -189,6 +225,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x02) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -208,6 +248,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0001") // _HID: H= ardware ID=0D Name (_CID, "HISI0031") // _CID: C= ompatible ID=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress=0D Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings=0D {=0D @@ -235,6 +279,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0001") // _HID: H= ardware ID=0D Name (_CID, "HISI0031") // _CID: C= ompatible ID=0D Name (_UID, 0x01) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_ADR, ARMADA80X0_MCBIN_DBG2_UART_REG_BASE) // _ADR: A= ddress=0D Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings=0D {=0D @@ -261,6 +309,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "MRVL0100") // _HID: H= ardware ID=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite,=0D @@ -278,6 +330,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "MRVL0101") // _HID: H= ardware ID=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite,=0D @@ -312,6 +368,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D Name (_CCA, 0x01) // Cache-c= oherent controller=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)=0D @@ -351,6 +411,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D Name (_CCA, 0x01) // Cache-c= oherent controller=0D Name (_UID, 0x01) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)=0D @@ -429,6 +493,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "PRP0001") // _HID= : Hardware ID=0D Name (_UID, 0x00) // _UID= : Unique ID=0D + Method (_STA) // _STA= : Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)=0D @@ -449,6 +517,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "PRP0001") // _HID= : Hardware ID=0D Name (_UID, 0x01) // _UID= : Unique ID=0D + Method (_STA) // _STA= : Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xF4760000, 0x7D)=0D @@ -475,6 +547,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_SEG, 0x00) // _SEG: PCI Segment=0D Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_PRT, Package () // _PRT: PCI Routing Table=0D {=0D Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl index 8377b13763..d6619e367b 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl @@ -20,6 +20,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU = ", "CN9131", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CLS, Package (0x03) // _CLS: Class Code=0D {=0D 0x01,=0D @@ -45,6 +49,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU = ", "CN9131", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x02) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -63,6 +71,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU = ", "CN9131", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D Name (_CCA, 0x01) // Cache-c= oherent controller=0D Name (_UID, 0x01) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl index 8c098cd14c..7335e443c6 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl @@ -21,21 +21,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN91= 30", 3) {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x000) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU1)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x001) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU2)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x100) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU3)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x101) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D =0D Device (AHC0)=0D @@ -43,6 +59,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN913= 0", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CLS, Package (0x03) // _CLS: Class Code=0D {=0D 0x01,=0D @@ -68,6 +88,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN913= 0", 3) Name (_HID, "MRVL0003") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -99,6 +123,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN91= 30", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -127,6 +155,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -146,6 +178,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -165,6 +201,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "MRVL0001") // _HID: H= ardware ID=0D Name (_CID, "HISI0031") // _CID: C= ompatible ID=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress=0D Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings=0D {=0D @@ -192,6 +232,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "MRVL0001") // _HID: H= ardware ID=0D Name (_CID, "HISI0031") // _CID: C= ompatible ID=0D Name (_UID, 0x01) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_ADR, CN913X_DBG2_UART_REG_BASE) // _ADR: A= ddress=0D Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings=0D {=0D @@ -218,6 +262,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) {=0D Name (_HID, "MRVL0100") // _HID: H= ardware ID=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite,=0D @@ -240,6 +288,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D Name (_CCA, 0x01) // Cache-c= oherent controller=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)=0D @@ -318,6 +370,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) {=0D Name (_HID, "PRP0001") // _HID= : Hardware ID=0D Name (_UID, 0x00) // _UID= : Unique ID=0D + Method (_STA) // _STA= : Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)=0D @@ -344,6 +400,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_SEG, 0x00) // _SEG: PCI Segment=0D Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_PRT, Package () // _PRT: PCI Routing Table=0D {=0D Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D --=20 2.29.0