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([2607:f2c0:e98c:24:2974:7c11:a389:1a47]) by smtp.gmail.com with ESMTPSA id 19sm1494161qty.97.2021.08.13.17.24.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Aug 2021 17:24:59 -0700 (PDT) From: "Benjamin Doron" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Michael Kubacki Subject: [edk2-platforms][PATCH v2 2/5] KabylakeOpenBoardPkg/AspireVn7Dash572G: Duplicate KabylakeRvp3 directory Date: Fri, 13 Aug 2021 20:24:42 -0400 Message-Id: <20210814002445.10084-3-benjamin.doron00@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210814002445.10084-1-benjamin.doron00@gmail.com> References: <20210804203630.7080-1-benjamin.doron00@gmail.com> <20210814002445.10084-1-benjamin.doron00@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable This makes diffing the follow-up board changes easier. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Michael Kubacki Signed-off-by: Benjamin Doron --- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c | 115 ++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 87 +++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c | 186 +++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c | 153 +++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h | 27 + Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c | 248 +++++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c | 84 +++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h | 30 + Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c | 79 +++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 150 ++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/EcCommands.h= | 46 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/FlashMap= Include.fdf | 48 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatform= HookLib/BasePlatformHookLib.c | 662 ++++++++= ++++++++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePlatform= HookLib/BasePlatformHookLib.inf | 51 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /DxeBoardAcpiTableLib.c | 36 + Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /DxeBoardAcpiTableLib.inf | 48 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /DxeKabylakeRvp3AcpiTableLib.c | 76 +++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /DxeMultiBoardAcpiSupportLib.c | 43 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /DxeMultiBoardAcpiSupportLib.inf | 49 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /SmmBoardAcpiEnableLib.c | 62 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /SmmBoardAcpiEnableLib.inf | 47 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /SmmKabylakeRvp3AcpiEnableLib.c | 39 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /SmmMultiBoardAcpiSupportLib.c | 81 +++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /SmmMultiBoardAcpiSupportLib.inf | 48 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib= /SmmSiliconAcpiEnableLib.c | 168 +++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /KabylakeRvp3GpioTable.c | 381 ++++++++= +++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /KabylakeRvp3HdaVerbTables.c | 232 +++++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /KabylakeRvp3HsioPtssTables.c | 105 +++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /KabylakeRvp3SpdTable.c | 541 ++++++++= +++++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiBoardInitPostMemLib.c | 39 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiBoardInitPostMemLib.inf | 54 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiBoardInitPreMemLib.c | 108 +++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiBoardInitPreMemLib.inf | 135 ++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiKabylakeRvp3Detect.c | 124 ++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiKabylakeRvp3InitLib.h | 44 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiKabylakeRvp3InitPostMemLib.c | 208 ++++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiKabylakeRvp3InitPreMemLib.c | 339 ++++++++= ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiMultiBoardInitPostMemLib.c | 40 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiMultiBoardInitPostMemLib.inf | 56 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiMultiBoardInitPreMemLib.c | 82 +++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiMultiBoardInitPreMemLib.inf | 137 ++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc = | 521 ++++++++= ++++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.fdf = | 715 ++++++++= ++++++++++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgBuildOpt= ion.dsc | 151 +++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc = | 464 ++++++++= +++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSi= liconPolicyUpdateLib/DxeGopPolicyInit.c | 175 +++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSi= liconPolicyUpdateLib/DxeGopPolicyInit.h | 39 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSi= liconPolicyUpdateLib/DxeSaPolicyInit.h | 64 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSi= liconPolicyUpdateLib/DxeSaPolicyUpdate.c | 66 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSi= liconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c | 53 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSi= liconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf | 51 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c | 601 ++++++++= ++++++++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf | 92 +++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_board.py = | 68 ++ Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.cfg = | 36 + 55 files changed, 8384 insertions(+) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c b/Platform/Intel/= KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyU= pdateLibFsp/PcieDeviceTable.c new file mode 100644 index 000000000000..155dfdaf623f --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c @@ -0,0 +1,115 @@ +/** @file=0D + This file is SampleCode of the library for Intel PCH PEI Policy initiali= zation.=0D +=0D +Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "PeiPchPolicyUpdate.h"=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#define PCI_CLASS_NETWORK 0x02=0D +#define PCI_CLASS_NETWORK_ETHERNET 0x00=0D +#define PCI_CLASS_NETWORK_OTHER 0x80=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = =3D {=0D + //=0D + // Intel PRO/Wireless=0D + //=0D + { 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 },=0D + { 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 },=0D + { 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 },=0D + { 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 },=0D + //=0D + // Intel WiMAX/WiFi Link=0D + //=0D + { 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 },=0D + { 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 },=0D + { 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 },=0D + { 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 },=0D + { 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 },=0D + { 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 },=0D + { 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 },=0D + { 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 },=0D + { 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 },=0D + { 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 },=0D + //=0D + // Intel Crane Peak WLAN NIC=0D + //=0D + { 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },=0D + { 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },=0D + //=0D + // Intel Crane Peak w/BT WLAN NIC=0D + //=0D + { 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },=0D + { 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },=0D + //=0D + // Intel Kelsey Peak WiFi, WiMax=0D + //=0D + { 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },=0D + { 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },=0D + //=0D + // Intel Centrino Wireless-N 105=0D + //=0D + { 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },=0D + { 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },=0D + //=0D + // Intel Centrino Wireless-N 135=0D + //=0D + { 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },=0D + { 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },=0D + //=0D + // Intel Centrino Wireless-N 2200=0D + //=0D + { 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },=0D + { 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },=0D + //=0D + // Intel Centrino Wireless-N 2230=0D + //=0D + { 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },=0D + { 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },=0D + //=0D + // Intel Centrino Wireless-N 6235=0D + //=0D + { 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },=0D + { 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },=0D + //=0D + // Intel CampPeak 2 Wifi=0D + //=0D + { 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },=0D + { 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },=0D + //=0D + // Intel WilkinsPeak 1 Wifi=0D + //=0D + { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, = 0, 0 },=0D + { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, = 0, 0 },=0D + //=0D + // Intel Wilkins Peak 2 Wifi=0D + //=0D + { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, = 0, 0 },=0D + { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, = 0, 0 },=0D + //=0D + // Intel Wilkins Peak PF Wifi=0D + //=0D + { 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 },=0D +=0D + //=0D + // End of Table=0D + //=0D + { 0 }=0D +};=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform= /Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSilicon= PolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c new file mode 100644 index 000000000000..d8aff1960f0b --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c @@ -0,0 +1,87 @@ +/** @file=0D + Implementation of Fsp Misc UPD Initialization.=0D +=0D +Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Performs FSP Misc UPD initialization.=0D +=0D + @param[in][out] FspmUpd Pointer to FSPM_UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspMiscUpdUpdatePreMem (=0D + IN OUT FSPM_UPD *FspmUpd=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINTN VariableSize;=0D + VOID *MemorySavedData;=0D + UINT8 MorControl;=0D + VOID *MorControlPtr;=0D +=0D + //=0D + // Initialize S3 Data variable (S3DataPtr). It may be used for warm and = fast boot paths.=0D + //=0D + VariableSize =3D 0;=0D + MemorySavedData =3D NULL;=0D + Status =3D PeiGetVariable (=0D + L"MemoryConfig",=0D + &gFspNonVolatileStorageHobGuid,=0D + &MemorySavedData,=0D + &VariableSize=0D + );=0D + DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" gFspNonVolatileStorageHobGuid= - %r\n", Status));=0D + DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize));=0D + FspmUpd->FspmArchUpd.NvsBufferPtr =3D MemorySavedData;=0D +=0D + if (FspmUpd->FspmArchUpd.NvsBufferPtr !=3D NULL) {=0D + //=0D + // Set the DISB bit in PCH (DRAM Initialization Scratchpad Bit - GEN_P= MCON_A[23]),=0D + // after memory Data is saved to NVRAM.=0D + //=0D + PciOr32 ((UINTN)PCI_LIB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUN= CTION_NUMBER_PCH_PMC, R_PCH_PMC_GEN_PMCON_A), B_PCH_PMC_GEN_PMCON_A_DISB);= =0D + }=0D +=0D + //=0D + // MOR=0D + //=0D + MorControl =3D 0;=0D + MorControlPtr =3D &MorControl;=0D + VariableSize =3D sizeof (MorControl);=0D + Status =3D PeiGetVariable (=0D + MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME,=0D + &gEfiMemoryOverwriteControlDataGuid,=0D + &MorControlPtr,=0D + &VariableSize=0D + );=0D + DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status));=0D + if (MOR_CLEAR_MEMORY_VALUE (MorControl)) {=0D + FspmUpd->FspmConfig.CleanMemory =3D (BOOLEAN)(MorControl & MOR_CLEAR_M= EMORY_BIT_MASK);=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c b/Platform/= Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiFspPolicyUpdateLib.c new file mode 100644 index 000000000000..55be16265e99 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c @@ -0,0 +1,186 @@ +/** @file=0D + Provide FSP wrapper platform related function.=0D +=0D +Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Performs FSP Misc UPD initialization.=0D +=0D + @param[in][out] FspmUpd Pointer to FSPM_UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspMiscUpdUpdatePreMem (=0D + IN OUT FSPM_UPD *FspmUpd=0D + );=0D +=0D +/**=0D + Performs FSP PCH PEI Policy pre mem initialization.=0D +=0D + @param[in][out] FspmUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspPchPolicyUpdatePreMem (=0D + IN OUT FSPM_UPD *FspmUpd=0D + );=0D +=0D +/**=0D + Performs FSP PCH PEI Policy initialization.=0D +=0D + @param[in][out] FspsUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspPchPolicyUpdate (=0D + IN OUT FSPS_UPD *FspsUpd=0D + );=0D +=0D +/**=0D + Performs FSP SA PEI Policy initialization in pre-memory.=0D +=0D + @param[in][out] FspmUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspSaPolicyUpdatePreMem (=0D + IN OUT FSPM_UPD *FspmUpd=0D + );=0D +=0D +/**=0D + Performs FSP SA PEI Policy initialization.=0D +=0D + @param[in][out] FspsUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspSaPolicyUpdate (=0D + IN OUT FSPS_UPD *FspsUpd=0D + );=0D +=0D +VOID=0D +InternalPrintVariableData (=0D + IN UINT8 *Data8,=0D + IN UINTN DataSize=0D + )=0D +{=0D + UINTN Index;=0D +=0D + for (Index =3D 0; Index < DataSize; Index++) {=0D + if (Index % 0x10 =3D=3D 0) {=0D + DEBUG ((DEBUG_INFO, "\n%08X:", Index));=0D + }=0D + DEBUG ((DEBUG_INFO, " %02X", *Data8++));=0D + }=0D + DEBUG ((DEBUG_INFO, "\n"));=0D +}=0D +=0D +/**=0D + Performs silicon pre-mem policy update.=0D +=0D + The meaning of Policy is defined by silicon code.=0D + It could be the raw data, a handle, a PPI, etc.=0D + =0D + The input Policy must be returned by SiliconPolicyDonePreMem().=0D + =0D + 1) In FSP path, the input Policy should be FspmUpd.=0D + A platform may use this API to update the FSPM UPD policy initialized=0D + by the silicon module or the default UPD data.=0D + The output of FSPM UPD data from this API is the final UPD data.=0D +=0D + 2) In non-FSP path, the board may use additional way to get=0D + the silicon policy data field based upon the input Policy.=0D +=0D + @param[in, out] Policy Pointer to policy.=0D +=0D + @return the updated policy.=0D +**/=0D +VOID *=0D +EFIAPI=0D +SiliconPolicyUpdatePreMem (=0D + IN OUT VOID *FspmUpd=0D + )=0D +{=0D + FSPM_UPD *FspmUpdDataPtr;=0D +=0D + FspmUpdDataPtr =3D FspmUpd;=0D + PeiFspSaPolicyUpdatePreMem (FspmUpdDataPtr);=0D + PeiFspPchPolicyUpdatePreMem (FspmUpdDataPtr);=0D + PeiFspMiscUpdUpdatePreMem (FspmUpdDataPtr);=0D +=0D + InternalPrintVariableData ((VOID *)FspmUpdDataPtr, sizeof(FSPM_UPD));=0D +=0D + return FspmUpd;=0D +}=0D +=0D +/**=0D + Performs silicon post-mem policy update.=0D +=0D + The meaning of Policy is defined by silicon code.=0D + It could be the raw data, a handle, a PPI, etc.=0D + =0D + The input Policy must be returned by SiliconPolicyDonePostMem().=0D + =0D + 1) In FSP path, the input Policy should be FspsUpd.=0D + A platform may use this API to update the FSPS UPD policy initialized=0D + by the silicon module or the default UPD data.=0D + The output of FSPS UPD data from this API is the final UPD data.=0D +=0D + 2) In non-FSP path, the board may use additional way to get=0D + the silicon policy data field based upon the input Policy.=0D +=0D + @param[in, out] Policy Pointer to policy.=0D +=0D + @return the updated policy.=0D +**/=0D +VOID *=0D +EFIAPI=0D +SiliconPolicyUpdatePostMem (=0D + IN OUT VOID *FspsUpd=0D + )=0D +{=0D + FSPS_UPD *FspsUpdDataPtr;=0D +=0D + FspsUpdDataPtr =3D FspsUpd;=0D + PeiFspSaPolicyUpdate (FspsUpdDataPtr);=0D + PeiFspPchPolicyUpdate (FspsUpdDataPtr);=0D + =0D + InternalPrintVariableData ((VOID *)FspsUpdDataPtr, sizeof(FSPS_UPD));=0D +=0D + return FspsUpd;=0D +}=0D +=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c b/Platform/Int= el/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPoli= cyUpdateLibFsp/PeiPchPolicyUpdate.c new file mode 100644 index 000000000000..b469720ac657 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c @@ -0,0 +1,153 @@ +/** @file=0D + This file is SampleCode of the library for Intel PCH PEI Policy initiali= zation.=0D +=0D +Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "PeiPchPolicyUpdate.h"=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +extern PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[];=0D +=0D +/**=0D + Add verb table helper function.=0D + This function calculates verbtable number and shows verb table informati= on.=0D +=0D + @param[in,out] VerbTableEntryNum Input current VerbTable number and= output the number after adding new table=0D + @param[in,out] VerbTableArray Pointer to array of VerbTable=0D + @param[in] VerbTable VerbTable which is going to add in= to array=0D +**/=0D +STATIC=0D +VOID=0D +InternalAddVerbTable (=0D + IN OUT UINT8 *VerbTableEntryNum,=0D + IN OUT UINT32 *VerbTableArray,=0D + IN HDAUDIO_VERB_TABLE *VerbTable=0D + )=0D +{=0D + if (VerbTable =3D=3D NULL) {=0D + DEBUG ((DEBUG_ERROR, "InternalAddVerbTable wrong input: VerbTable =3D= =3D NULL\n"));=0D + return;=0D + }=0D +=0D + VerbTableArray[*VerbTableEntryNum] =3D (UINT32) VerbTable;=0D + *VerbTableEntryNum +=3D 1;=0D +=0D + DEBUG ((DEBUG_INFO,=0D + "Add verb table for vendor =3D 0x%04X devId =3D 0x%04X (size =3D %d DW= ords)\n",=0D + VerbTable->Header.VendorId,=0D + VerbTable->Header.DeviceId,=0D + VerbTable->Header.DataDwords)=0D + );=0D +}=0D +=0D +enum HDAUDIO_CODEC_SELECT {=0D + PchHdaCodecPlatformOnboard =3D 0,=0D + PchHdaCodecExternalKit =3D 1=0D +};=0D +=0D +/**=0D + Add verb table function.=0D + This function update the verb table number and verb table ptr of policy.= =0D +=0D + @param[in] HdAudioConfig HDAudie config block=0D + @param[in] CodecType Platform codec type indicator=0D + @param[in] AudioConnectorType Platform audio connector type=0D +**/=0D +STATIC=0D +VOID=0D +InternalAddPlatformVerbTables (=0D + IN OUT FSPS_UPD *FspsUpd,=0D + IN UINT8 CodecType,=0D + IN UINT8 AudioConnectorType=0D + )=0D +{=0D + UINT8 VerbTableEntryNum;=0D + UINT32 VerbTableArray[32];=0D + UINT32 *VerbTablePtr;=0D +=0D + VerbTableEntryNum =3D 0;=0D +=0D + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UINT= N) PcdGet32 (PcdDisplayAudioHdaVerbTable));=0D +=0D + if (CodecType =3D=3D PchHdaCodecPlatformOnboard) {=0D + DEBUG ((DEBUG_INFO, "HDA Policy: Onboard codec selected\n"));=0D + if ((VOID *) (UINTN) PcdGet32 (PcdExtHdaVerbTable) !=3D NULL) {=0D + if (AudioConnectorType =3D=3D 0) { //Type-C Audio connector selected= in Bios Setup menu=0D + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *)= (UINTN) PcdGet32 (PcdExtHdaVerbTable));=0D + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL);=0D + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL);=0D + DEBUG ((DEBUG_INFO, "HDA: Type-C Audio connector selected!\n"));=0D + } else { //Stacked Jack Audio connector selected in Bios Setup menu= =0D + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *)= (UINTN) PcdGet32 (PcdHdaVerbTable));=0D + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *)= (UINTN) PcdGet32 (PcdHdaVerbTable2));=0D + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL);=0D + DEBUG ((DEBUG_INFO, "HDA: Stacked-Jack Audio connector selected!\n= "));=0D + }=0D + } else {=0D + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (= UINTN) PcdGet32 (PcdHdaVerbTable));=0D + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (= UINTN) PcdGet32 (PcdHdaVerbTable2));=0D + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, NULL);=0D + }=0D + } else {=0D + DEBUG ((DEBUG_INFO, "HDA Policy: External codec kit selected\n"));=0D + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UI= NTN) PcdGet32 (PcdCommonHdaVerbTable1));=0D + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UI= NTN) PcdGet32 (PcdCommonHdaVerbTable2));=0D + InternalAddVerbTable (&VerbTableEntryNum, VerbTableArray, (VOID *) (UI= NTN) PcdGet32 (PcdCommonHdaVerbTable3));=0D + }=0D +=0D + FspsUpd->FspsConfig.PchHdaVerbTableEntryNum =3D VerbTableEntryNum;=0D +=0D + VerbTablePtr =3D (UINT32 *) AllocateZeroPool (sizeof (UINT32) * VerbTabl= eEntryNum);=0D + CopyMem (VerbTablePtr, VerbTableArray, sizeof (UINT32) * VerbTableEntryN= um);=0D + FspsUpd->FspsConfig.PchHdaVerbTablePtr =3D (UINT32) VerbTablePtr;=0D +}=0D +=0D +/**=0D + Performs FSP PCH PEI Policy initialization.=0D +=0D + @param[in][out] FspsUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspPchPolicyUpdate (=0D + IN OUT FSPS_UPD *FspsUpd=0D + )=0D +{=0D +=0D + FspsUpd->FspsConfig.PchSubSystemVendorId =3D V_PCH_INTEL_VENDOR_ID;=0D + FspsUpd->FspsConfig.PchSubSystemId =3D V_PCH_DEFAULT_SID;=0D +=0D + FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr =3D (UINT32) mPcieDevi= ceTable;=0D +=0D + InternalAddPlatformVerbTables (FspsUpd, PchHdaCodecPlatformOnboard, PcdG= et8 (PcdAudioConnector));=0D +=0D +DEBUG_CODE_BEGIN();=0D +if ((PcdGet8 (PcdSerialIoUartDebugEnable) =3D=3D 1) &&=0D + FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 = (PcdSerialIoUartNumber)] =3D=3D PchSerialIoDisabled ) {=0D + FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (P= cdSerialIoUartNumber)] =3D PchSerialIoLegacyUart;=0D + }=0D +DEBUG_CODE_END();=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h b/Platform/Int= el/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPoli= cyUpdateLibFsp/PeiPchPolicyUpdate.h new file mode 100644 index 000000000000..30d2f99e1dde --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h @@ -0,0 +1,27 @@ +/** @file=0D +=0D +Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef _PEI_PCH_POLICY_UPDATE_H_=0D +#define _PEI_PCH_POLICY_UPDATE_H_=0D +=0D +//=0D +// External include files do NOT need to be explicitly specified in real E= DKII=0D +// environment=0D +//=0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +=0D +#endif=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c b/Platfo= rm/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSilic= onPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c new file mode 100644 index 000000000000..f6390ee12c17 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c @@ -0,0 +1,248 @@ +/** @file=0D + This file is SampleCode of the library for Intel PCH PEI Policy initiali= zation.=0D +=0D +Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "PeiPchPolicyUpdate.h"=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +VOID=0D +InstallPlatformHsioPtssTable (=0D + IN OUT FSPM_UPD *FspmUpd=0D + )=0D +{=0D + HSIO_PTSS_TABLES *UnknowPtssTables;=0D + HSIO_PTSS_TABLES *SpecificPtssTables;=0D + HSIO_PTSS_TABLES *PtssTables;=0D + UINT8 PtssTableIndex;=0D + UINT32 UnknowTableSize;=0D + UINT32 SpecificTableSize;=0D + UINT32 TableSize;=0D + UINT32 Entry;=0D + UINT8 LaneNum;=0D + UINT8 Index;=0D + UINT8 MaxSataPorts;=0D + UINT8 MaxPciePorts;=0D + UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS];=0D + UINT8 PciePort;=0D + UINTN RpBase;=0D + UINTN RpDevice;=0D + UINTN RpFunction;=0D + UINT32 StrapFuseCfg;=0D + UINT8 PcieControllerCfg;=0D + EFI_STATUS Status;=0D +=0D + UnknowPtssTables =3D NULL;=0D + UnknowTableSize =3D 0;=0D + SpecificPtssTables =3D NULL;=0D + SpecificTableSize =3D 0;=0D +=0D + if (GetPchGeneration () =3D=3D SklPch) {=0D + switch (PchStepping ()) {=0D + case PchLpB0:=0D + case PchLpB1:=0D + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPts= sTable1);=0D + UnknowTableSize =3D PcdGet16 (PcdUnknowLpHsioPtssTable1Size);=0D + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsi= oPtssTable1);=0D + SpecificTableSize =3D PcdGet16 (PcdSpecificLpHsioPtssTable1Size);= =0D + break;=0D + case PchLpC0:=0D + case PchLpC1:=0D + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPts= sTable2);=0D + UnknowTableSize =3D PcdGet16 (PcdUnknowLpHsioPtssTable2Size);=0D + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsi= oPtssTable2);=0D + SpecificTableSize =3D PcdGet16 (PcdSpecificLpHsioPtssTable2Size);= =0D + break;=0D + case PchHB0:=0D + case PchHC0:=0D + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtss= Table1);=0D + UnknowTableSize =3D PcdGet16 (PcdUnknowHHsioPtssTable1Size);=0D + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsio= PtssTable1);=0D + SpecificTableSize =3D PcdGet16 (PcdSpecificHHsioPtssTable1Size);=0D + break;=0D + case PchHD0:=0D + case PchHD1:=0D + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtss= Table2);=0D + UnknowTableSize =3D PcdGet16 (PcdUnknowHHsioPtssTable2Size);=0D + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsio= PtssTable2);=0D + SpecificTableSize =3D PcdGet16 (PcdSpecificHHsioPtssTable2Size);=0D + break;=0D + default:=0D + UnknowPtssTables =3D NULL;=0D + UnknowTableSize =3D 0;=0D + SpecificPtssTables =3D NULL;=0D + SpecificTableSize =3D 0;=0D + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));=0D + }=0D + } else {=0D + switch (PchStepping ()) {=0D + case KblPchHA0:=0D + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtss= Table2);=0D + UnknowTableSize =3D PcdGet16 (PcdUnknowHHsioPtssTable2Size);=0D + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsio= PtssTable2);=0D + SpecificTableSize =3D PcdGet16 (PcdSpecificHHsioPtssTable2Size);=0D + break;=0D + default:=0D + UnknowPtssTables =3D NULL;=0D + UnknowTableSize =3D 0;=0D + SpecificPtssTables =3D NULL;=0D + SpecificTableSize =3D 0;=0D + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));=0D + }=0D + }=0D +=0D + PtssTableIndex =3D 0;=0D + MaxSataPorts =3D GetPchMaxSataPortNum ();=0D + MaxPciePorts =3D GetPchMaxPciePortNum ();=0D + ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal));=0D +=0D + //Populate PCIe topology based on lane configuration=0D + for (PciePort =3D 0; PciePort < MaxPciePorts; PciePort +=3D 4) {=0D + Status =3D GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + RpBase =3D MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (= UINT32) RpFunction);=0D + StrapFuseCfg =3D MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG);=0D + PcieControllerCfg =3D (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_= RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC);=0D + DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value =3D %d\n", PciePo= rt, PcieControllerCfg));=0D + }=0D + for (Index =3D 0; Index < MaxPciePorts; Index++) {=0D + DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology =3D %d\n", Inde= x, PcieTopologyReal[Index]));=0D + }=0D +=0D + //Case 1: BoardId is known, Topology is known/unknown=0D + //Case 1a: SATA=0D + PtssTables =3D SpecificPtssTables;=0D + TableSize =3D SpecificTableSize;=0D + for (Index =3D 0; Index < MaxSataPorts; Index++) {=0D + if (PchGetSataLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) {=0D + for (Entry =3D 0; Entry < TableSize; Entry++) {=0D + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) &&=0D + (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LANE= _OWN_SATA)=0D + )=0D + {=0D + PtssTableIndex++;=0D + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_PCH_HS= IO_RX_DWORD20) &&=0D + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_R= X_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) =3D=3D (UINT32) B_PCH_HSIO_RX_DWORD= 20_ICFGCTLEDATATAP_FULLRATE_5_0)) {=0D + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] = =3D TRUE;=0D + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] =3D (Pt= ssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.Bit= Mask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;=0D + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R= _PCH_HSIO_TX_DWORD8)) {=0D + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) = B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) =3D=3D (UINT32) B_PCH_HSIO_TX_DWORD= 8_ORATE00MARGIN_5_0) {=0D + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Inde= x] =3D TRUE;=0D + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] =3D= (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8= _ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0);=0D + }=0D + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) = B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) =3D=3D (UINT32) B_PCH_HSIO_TX_DWORD= 8_ORATE01MARGIN_5_0) {=0D + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Inde= x] =3D TRUE;=0D + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] =3D= (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWORD8= _ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0);=0D + }=0D + } else {=0D + ASSERT (FALSE);=0D + }=0D + }=0D + }=0D + }=0D + }=0D + //Case 1b: PCIe=0D + for (Index =3D 0; Index < MaxPciePorts; Index++) {=0D + if (PchGetPcieLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) {=0D + for (Entry =3D 0; Entry < TableSize; Entry++) {=0D + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) &&=0D + (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LANE= _OWN_PCIEDMI) &&=0D + (PcieTopologyReal[Index] =3D=3D PtssTables[Entry].Topology)) {= =0D + PtssTableIndex++;=0D + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_PCH_HS= IO_RX_DWORD25) &&=0D + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_R= X_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) =3D=3D (UINT32) B_PCH_HSIO_RX_DWORD25_= CTLE_ADAPT_OFFSET_CFG_4_0)) {=0D + FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] =3D TRUE= ;=0D + FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] =3D (UINT8)((P= tssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.Bi= tMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0);=0D + } else {=0D + ASSERT (FALSE);=0D + }=0D + }=0D + }=0D + }=0D + }=0D + //Case 2: BoardId is unknown, Topology is known/unknown=0D + if (PtssTableIndex =3D=3D 0) {=0D + DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be applied\n= "));=0D +=0D + PtssTables =3D UnknowPtssTables;=0D + TableSize =3D UnknowTableSize;=0D +=0D + for (Index =3D 0; Index < MaxSataPorts; Index++) {=0D + if (PchGetSataLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) {=0D + for (Entry =3D 0; Entry < TableSize; Entry++) {=0D + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) &&=0D + (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LA= NE_OWN_SATA)=0D + )=0D + {=0D + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_PCH_= HSIO_RX_DWORD20) &&=0D + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO= _RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) =3D=3D (UINT32) B_PCH_HSIO_RX_DWO= RD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {=0D + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index]= =3D TRUE;=0D + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] =3D (= PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.B= itMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;=0D + } else if (PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) = R_PCH_HSIO_TX_DWORD8) {=0D + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32= ) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) =3D=3D (UINT32) B_PCH_HSIO_TX_DWO= RD8_ORATE00MARGIN_5_0) {=0D + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[In= dex] =3D TRUE;=0D + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] = =3D (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWO= RD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0);=0D + }=0D + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32= ) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) =3D=3D (UINT32) B_PCH_HSIO_TX_DWO= RD8_ORATE01MARGIN_5_0) {=0D + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[In= dex] =3D TRUE;=0D + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] = =3D (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSIO_TX_DWO= RD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0);=0D + }=0D + } else {=0D + ASSERT (FALSE);=0D + }=0D + }=0D + }=0D + }=0D + }=0D + for (Index =3D 0; Index < MaxPciePorts; Index++) {=0D + if (PchGetPcieLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) {=0D + for (Entry =3D 0; Entry < TableSize; Entry++) {=0D + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) &&=0D + (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LA= NE_OWN_PCIEDMI) &&=0D + (PcieTopologyReal[Index] =3D=3D PtssTables[Entry].Topology))= {=0D + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_PCH_= HSIO_RX_DWORD25) &&=0D + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO= _RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) =3D=3D (UINT32) B_PCH_HSIO_RX_DWORD2= 5_CTLE_ADAPT_OFFSET_CFG_4_0)) {=0D + FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] =3D TR= UE;=0D + FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] =3D (UINT8)(= (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry].PtssTable.= BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0);=0D + } else {=0D + ASSERT (FALSE);=0D + }=0D + }=0D + }=0D + }=0D + }=0D + }=0D +}=0D +=0D +/**=0D + Performs FSP PCH PEI Policy pre mem initialization.=0D +=0D + @param[in][out] FspmUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspPchPolicyUpdatePreMem (=0D + IN OUT FSPM_UPD *FspmUpd=0D + )=0D +{=0D + InstallPlatformHsioPtssTable (FspmUpd);=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Inte= l/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolic= yUpdateLibFsp/PeiSaPolicyUpdate.c new file mode 100644 index 000000000000..d6ec3e38dd7e --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c @@ -0,0 +1,84 @@ +/** @file=0D +Do Platform Stage System Agent initialization.=0D +=0D +Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "PeiSaPolicyUpdate.h"=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Performs FSP SA PEI Policy initialization.=0D +=0D + @param[in][out] FspsUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspSaPolicyUpdate (=0D + IN OUT FSPS_UPD *FspsUpd=0D + )=0D +{=0D + VOID *Buffer;=0D + VOID *MemBuffer;=0D + UINT32 Size;=0D +=0D + DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n"));=0D +=0D + FspsUpd->FspsConfig.PeiGraphicsPeimInit =3D 1;=0D +=0D + Size =3D 0;=0D + Buffer =3D NULL;=0D + PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size);=0D + if (Buffer =3D=3D NULL) {=0D + DEBUG((DEBUG_WARN, "Could not locate VBT\n"));=0D + } else {=0D + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= );=0D + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) {=0D + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);=0D + FspsUpd->FspsConfig.GraphicsConfigPtr =3D (UINT32)(UINTN)MemBuffer= ;=0D + } else {=0D + DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n"));=0D + FspsUpd->FspsConfig.GraphicsConfigPtr =3D 0;=0D + }=0D + }=0D + DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", F= spsUpd->FspsConfig.GraphicsConfigPtr));=0D + DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size= ));=0D +=0D + Size =3D 0;=0D + Buffer =3D NULL;=0D + PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, = &Size);=0D + if (Buffer =3D=3D NULL) {=0D + DEBUG((DEBUG_WARN, "Could not locate Logo\n"));=0D + } else {=0D + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= );=0D + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) {=0D + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);=0D + FspsUpd->FspsConfig.LogoPtr =3D (UINT32)(UINTN)MemBuffer;=0D + FspsUpd->FspsConfig.LogoSize =3D Size;=0D + } else {=0D + DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n"));=0D + FspsUpd->FspsConfig.LogoPtr =3D 0;=0D + FspsUpd->FspsConfig.LogoSize =3D 0;=0D + }=0D + }=0D + DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", FspsU= pd->FspsConfig.LogoPtr));=0D + DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", Fsps= Upd->FspsConfig.LogoSize));=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h b/Platform/Inte= l/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolic= yUpdateLibFsp/PeiSaPolicyUpdate.h new file mode 100644 index 000000000000..3abf3fc8fd2f --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h @@ -0,0 +1,30 @@ +/** @file=0D +=0D +Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef _PEI_SA_POLICY_UPDATE_H_=0D +#define _PEI_SA_POLICY_UPDATE_H_=0D +=0D +//=0D +// External include files do NOT need to be explicitly specified in real E= DKII=0D +// environment=0D +//=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include "PeiPchPolicyUpdate.h"=0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +=0D +extern EFI_GUID gTianoLogoGuid;=0D +=0D +#endif=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c b/Platfor= m/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSilico= nPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c new file mode 100644 index 000000000000..f95f82a25ca5 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c @@ -0,0 +1,79 @@ +/** @file=0D +Do Platform Stage System Agent initialization.=0D +=0D +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "PeiSaPolicyUpdate.h"=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +=0D +/**=0D + Performs FSP SA PEI Policy initialization in pre-memory.=0D +=0D + @param[in][out] FspmUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspSaPolicyUpdatePreMem (=0D + IN OUT FSPM_UPD *FspmUpd=0D + )=0D +{=0D + VOID *Buffer;=0D +=0D + //=0D + // If SpdAddressTable are not all 0, it means DIMM slots implemented and= =0D + // MemorySpdPtr* already updated by reading SPD from DIMM in SiliconPoli= cyInitPreMem.=0D + //=0D + // If SpdAddressTable all 0, this is memory down design and hardcoded Sp= dData=0D + // should be applied to MemorySpdPtr*.=0D + //=0D + if ((PcdGet8 (PcdMrcSpdAddressTable0) =3D=3D 0) && (PcdGet8 (PcdMrcSpdAd= dressTable1) =3D=3D 0)=0D + && (PcdGet8 (PcdMrcSpdAddressTable2) =3D=3D 0) && (PcdGet8 (PcdMrcSp= dAddressTable3) =3D=3D 0)) {=0D + DEBUG((DEBUG_INFO, "Override MemorySpdPtr...\n"));=0D + CopyMem((VOID *)(UINTN)FspmUpd->FspmConfig.MemorySpdPtr00, (VOID *)(UI= NTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize));=0D + CopyMem((VOID *)(UINTN)FspmUpd->FspmConfig.MemorySpdPtr10, (VOID *)(UI= NTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize));=0D + }=0D +=0D + DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings= ...\n"));=0D + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap);=0D + if (Buffer) {=0D + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12);=0D + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) Buffer + 1= 2, 12);=0D + }=0D + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram);=0D + if (Buffer) {=0D + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, 8);=0D + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, (UINT8*) Buffe= r + 8, 8);=0D + }=0D +=0D + DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp = Target Settings...\n"));=0D + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor);=0D + if (Buffer) {=0D + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6);=0D + }=0D + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget);=0D + if (Buffer) {=0D + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10);=0D + }=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/= Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/Pe= iSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf new file mode 100644 index 000000000000..f8bec0c852d6 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf @@ -0,0 +1,150 @@ +## @file=0D +# Provide FSP wrapper platform related function.=0D +#=0D +# Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +##########################################################################= ######=0D +#=0D +# Defines Section - statements that will be processed to create a Makefile= .=0D +#=0D +##########################################################################= ######=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D SiliconPolicyUpdateLibFsp=0D + FILE_GUID =3D 4E83003B-49A9-459E-AAA6-1CA3C6D04FB2= =0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D SiliconPolicyUpdateLib=0D +=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64=0D +#=0D +=0D +##########################################################################= ######=0D +#=0D +# Sources Section - list of files that are required for the build to succe= ed.=0D +#=0D +##########################################################################= ######=0D +=0D +[Sources]=0D + PeiFspPolicyUpdateLib.c=0D + PeiPchPolicyUpdatePreMem.c=0D + PeiPchPolicyUpdate.c=0D + PeiSaPolicyUpdatePreMem.c=0D + PeiSaPolicyUpdate.c=0D + PeiFspMiscUpdUpdateLib.c=0D + PcieDeviceTable.c=0D +=0D +##########################################################################= ######=0D +#=0D +# Package Dependency Section - list of Package files that are required for= =0D +# this module.=0D +#=0D +##########################################################################= ######=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + IntelFsp2Pkg/IntelFsp2Pkg.dec=0D + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec=0D + IntelSiliconPkg/IntelSiliconPkg.dec=0D + KabylakeSiliconPkg/SiPkg.dec=0D + KabylakeFspBinPkg/KabylakeFspBinPkg.dec=0D + KabylakeOpenBoardPkg/OpenBoardPkg.dec=0D + MinPlatformPkg/MinPlatformPkg.dec=0D +=0D +[LibraryClasses.IA32]=0D + FspWrapperApiLib=0D + OcWdtLib=0D + PchResetLib=0D + FspWrapperPlatformLib=0D + BaseMemoryLib=0D + CpuPlatformLib=0D + DebugLib=0D + HobLib=0D + IoLib=0D + PcdLib=0D + PostCodeLib=0D + SmbusLib=0D + MmPciLib=0D + ConfigBlockLib=0D + PeiSaPolicyLib=0D + PchGbeLib=0D + PchInfoLib=0D + PchHsioLib=0D + PchPcieRpLib=0D + MemoryAllocationLib=0D + CpuMailboxLib=0D + DebugPrintErrorLevelLib=0D + SiPolicyLib=0D + PchGbeLib=0D + TimerLib=0D + GpioLib=0D + PeiLib=0D +=0D +[Pcd]=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONSUME= S=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONSUME= S=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## CONSUME= S=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUME= S=0D +=0D + # SPD Address Table=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 ## CONSUME= S=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 ## CONSUME= S=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 ## CONSUME= S=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 ## CONSUME= S=0D +=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize=0D +=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES=0D + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES=0D + gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES=0D + gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi ## CONSUMES=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES=0D +=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size=0D +=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size=0D +=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable2=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdExtHdaVerbTable=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable2=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable3=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDisplayAudioHdaVerbTable=0D +=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAudioConnector=0D +=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid=0D +=0D +[Guids]=0D + gFspNonVolatileStorageHobGuid ## CONSUMES=0D + gTianoLogoGuid ## CONSUMES=0D + gEfiMemoryOverwriteControlDataGuid=0D +=0D +[Depex]=0D + gEdkiiVTdInfoPpiGuid=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/= EcCommands.h b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Includ= e/EcCommands.h new file mode 100644 index 000000000000..a4ab192d8ce1 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/EcComma= nds.h @@ -0,0 +1,46 @@ +/** @file=0D + Definition for supported EC commands.=0D +=0D +Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef EC_COMMANDS_H_=0D +#define EC_COMMANDS_H_=0D +=0D +//=0D +// Timeout if EC command/data fails=0D +//=0D +#define EC_TIME_OUT 0x20000=0D +=0D +//=0D +// The EC implements an embedded controller interface at ports 0x60/0x64 a= nd a ACPI compliant=0D +// system management controller at ports 0x62/0x66. Port 0x66 is the comma= nd and status port,=0D +// port 0x62 is the data port.=0D +//=0D +#define EC_D_PORT 0x62=0D +#define EC_C_PORT 0x66=0D +=0D +//=0D +// Status Port 0x62=0D +//=0D +#define EC_S_OVR_TMP 0x80 // Current CPU temperature exceeds the th= reshold=0D +#define EC_S_SMI_EVT 0x40 // SMI event is pending=0D +#define EC_S_SCI_EVT 0x20 // SCI event is pending=0D +#define EC_S_BURST 0x10 // EC is in burst mode or normal mode=0D +#define EC_S_CMD 0x08 // Byte in data register is command/data= =0D +#define EC_S_IGN 0x04 // Ignored=0D +#define EC_S_IBF 0x02 // Input buffer is full/empty=0D +#define EC_S_OBF 0x01 // Output buffer is full/empty=0D +=0D +//=0D +// EC commands that are issued to the EC through the command port (0x66).= =0D +// New commands and command parameters should only be written by the host = when IBF=3D0.=0D +// Data read from the EC data port is valid only when OBF=3D1.=0D +//=0D +#define EC_C_FAB_ID 0x0D // Get the board fab ID in = the lower 3 bits=0D +#define EC_C_ACPI_READ 0x80 // Read a byte of EC RAM=0D +#define EC_C_ACPI_WRITE 0x81 // Write a byte of EC RAM=0D +=0D +#endif // EC_COMMANDS_H_=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/= Fdf/FlashMapInclude.fdf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash= 572G/Include/Fdf/FlashMapInclude.fdf new file mode 100644 index 000000000000..b5e3f66ceafc --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/Fla= shMapInclude.fdf @@ -0,0 +1,48 @@ +## @file=0D +# FDF file for the KabylakeRvp3 board.=0D +#=0D +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D#=0D +# 8 M BIOS - for FSP wrapper=0D +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D#=0D +DEFINE FLASH_BASE =3D 0x= FF800000 #=0D +DEFINE FLASH_SIZE =3D 0x= 00800000 #=0D +DEFINE FLASH_BLOCK_SIZE =3D 0x= 00010000 #=0D +DEFINE FLASH_NUM_BLOCKS =3D 0x= 00000080 #=0D +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D#=0D +=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset =3D 0x= 00000000 # Flash addr (0xFF800000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize =3D 0x= 00040000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset =3D 0x= 00000000 # Flash addr (0xFF800000)=0D +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =3D 0x= 0001E000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset =3D 0x= 0001E000 # Flash addr (0xFF81E000)=0D +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =3D 0x= 00002000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset =3D 0x= 00020000 # Flash addr (0xFF820000)=0D +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D 0x= 00020000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =3D 0x= 00040000 # Flash addr (0xFF840000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize =3D 0x= 00050000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =3D 0x= 00090000 # Flash addr (0xFF890000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =3D 0x= 00070000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset =3D 0x= 00100000 # Flash addr (0xFF900000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize =3D 0x= 00090000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =3D 0x= 00190000 # Flash addr (0xFF990000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D 0x= 001E0000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D 0x= 00370000 # Flash addr (0xFFB70000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D 0x= 00180000 #=0D +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D 0x= 004F0000 # Flash addr (0xFFCF0000)=0D +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D 0x= 000A0000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D 0x= 00590000 # Flash addr (0xFFD90000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D 0x= 00060000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D 0x= 005F0000 # Flash addr (0xFFDF0000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =3D 0x= 000BC000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D 0x= 006AC000 # Flash addr (0xFFEAC000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D 0x= 00014000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset =3D 0x= 006C0000 # Flash addr (0xFFEC0000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize =3D 0x= 00010000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D 0x= 006D0000 # Flash addr (0xFFED0000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D 0x= 00130000 #=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/KabylakeOpenBoar= dPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.c new file mode 100644 index 000000000000..c7fc6986f547 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePla= tformHookLib/BasePlatformHookLib.c @@ -0,0 +1,662 @@ +/** @file=0D + Platform Hook Library instances=0D +=0D +Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#define COM1_BASE 0x3f8=0D +#define COM2_BASE 0x2f8=0D +=0D +#define SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS 0x0690=0D +=0D +#define LPC_SIO_INDEX_DEFAULT_PORT_2 0x2E=0D +#define LPC_SIO_DATA_DEFAULT_PORT_2 0x2F=0D +#define LPC_SIO_GPIO_REGISTER_ADDRESS_2 0x0A20=0D +=0D +#define LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT 0x2E=0D +#define LEGACY_DAUGHTER_CARD_SIO_DATA_PORT 0x2F=0D +#define LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT 0x4E=0D +#define LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT 0x4F=0D +=0D +typedef struct {=0D + UINT8 Register;=0D + UINT8 Value;=0D +} EFI_SIO_TABLE;=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTable[] =3D {=0D + {0x002, 0x88}, // Power On UARTs=0D + {0x024, COM1_BASE >> 2},=0D + {0x025, COM2_BASE >> 2},=0D + {0x028, 0x043}, // IRQ of UARTs, UART2 IRQ=3D3,UART1 IRQ=3D4,=0D + {0x029, 0x080}, // SIRQ_CLKRUN_EN=0D + {0x02A, 0x000},=0D + {0x02B, 0x0DE},=0D + {0x00A, 0x040},=0D + {0x00C, 0x00E},=0D + {0x02c, 0x002},=0D + {0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4},=0D + {0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8},=0D + {0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff},=0D + {0x03a, 0x00A}, // LPC Docking Enabling=0D + {0x031, 0x01f},=0D + {0x032, 0x000},=0D + {0x033, 0x004},=0D + {0x038, 0x0FB},=0D + {0x035, 0x0FE},=0D + {0x036, 0x000},=0D + {0x037, 0x0FF},=0D + {0x039, 0x000},=0D + {0x034, 0x001},=0D + {0x012, FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & 0xFF}, //= Relocate configuration ports base address=0D + {0x013, (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) >> 8) & 0xFF} //= to ensure SIO config address can be accessed in OS=0D +};=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableSmsc1000[] =3D {=0D + {0x002, 0x88}, // Power On UARTs=0D + {0x007, 0x00},=0D + {0x024, COM1_BASE >> 2},=0D + {0x025, COM2_BASE >> 2},=0D + {0x028, 0x043}, // IRQ of UARTs, UART2 IRQ=3D3,UART1 IRQ=3D4,=0D + {0x029, 0x080}, // SIRQ_CLKRUN_EN=0D + {0x02A, 0x000},=0D + {0x02B, 0x0DE},=0D + {0x00A, 0x040},=0D + {0x00C, 0x00E},=0D + {0x030, FixedPcdGet16 (PcdSioBaseAddress) >> 4},=0D + {0x03b, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS >> 8},=0D + {0x03c, SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS & 0xff},=0D + {0x03a, 0x00A}, // LPC Docking Enabling=0D + {0x031, 0x01f},=0D + {0x032, 0x000},=0D + {0x033, 0x004},=0D + {0x038, 0x0FB},=0D + {0x035, 0x0FE},=0D + {0x036, 0x000},=0D + {0x037, 0x0FE},=0D + {0x039, 0x000},=0D + {0x034, 0x001}=0D +};=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWpcn381u[] =3D {=0D + {0x29, 0x0A0}, // Enable super I/O clock and set to 48M= Hz=0D + {0x22, 0x003}, //=0D + {0x07, 0x003}, // Select UART0 device=0D + {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB=0D + {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB=0D + {0x70, 0x004}, // Set to IRQ4=0D + {0x30, 0x001}, // Enable it with Activation bit=0D + {0x07, 0x002}, // Select UART1 device=0D + {0x60, (COM2_BASE >> 8)}, // Set Base Address MSB=0D + {0x61, (COM2_BASE & 0x00FF)}, // Set Base Address LSB=0D + {0x70, 0x003}, // Set to IRQ3=0D + {0x30, 0x001}, // Enable it with Activation bit=0D + {0x07, 0x007}, // Select GPIO device=0D + {0x60, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 >> 8)}, // Set Base Address= MSB=0D + {0x61, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 & 0x00FF)}, // Set Base Address= LSB=0D + {0x30, 0x001}, // Enable it with Activation bit=0D + {0x21, 0x001}, // Global Device Enable=0D + {0x26, 0x000} // Fast Enable UART 0 & 1 as their enabl= e & activation bit=0D +};=0D +=0D +//=0D +// National PC8374L=0D +//=0D +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mDesktopSioTable[] =3D {=0D + {0x007, 0x03}, // Select Com1=0D + {0x061, 0xF8}, // 0x3F8=0D + {0x060, 0x03}, // 0x3F8=0D + {0x070, 0x04}, // IRQ4=0D + {0x030, 0x01} // Active=0D +};=0D +=0D +//=0D +// IT8628=0D +//=0D +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableSerialPort[] = =3D {=0D + {0x023, 0x09}, // Clock Selection register=0D + {0x007, 0x01}, // Com1 Logical Device Number select=0D + {0x061, 0xF8}, // Serial Port 1 Base Address MSB Register=0D + {0x060, 0x03}, // Serial Port 1 Base Address LSB Register=0D + {0x070, 0x04}, // Serial Port 1 Interrupt Level Select=0D + {0x030, 0x01}, // Serial Port 1 Activate=0D + {0x007, 0x02}, // Com1 Logical Device Number select=0D + {0x061, 0xF8}, // Serial Port 2 Base Address MSB Register=0D + {0x060, 0x02}, // Serial Port 2 Base Address MSB Register=0D + {0x070, 0x03}, // Serial Port 2 Interrupt Level Select=0D + {0x030, 0x01} // Serial Port 2 Activate=0D +};=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableParallelPort[] = =3D {=0D + {0x007, 0x03}, // Parallel Port Logical Device Number select=0D + {0x030, 0x00}, // Parallel port Activate=0D + {0x061, 0x78}, // Parallel Port Base Address 1 MSB Register=0D + {0x060, 0x03}, // Parallel Port Base Address 1 LSB Register=0D + {0x063, 0x78}, // Parallel Port Base Address 2 MSB Register=0D + {0x062, 0x07}, // Parallel Port Base Address 1 LSB Register=0D + {0x0F0, 0x03} // Special Configuration register=0D +};=0D +=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWinbondX374[] =3D {=0D + {0x07, 0x03}, // Select UART0 device=0D + {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB=0D + {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB=0D + {0x70, 0x04}, // Set to IRQ4=0D + {0x30, 0x01} // Enable it with Activation bit=0D +};=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTablePilot3[] =3D {=0D + {0x07, 0x02}, // Set logical device SP Serial port Com0=0D + {0x61, 0xF8}, // Write Base Address LSB register 0x3F8=0D + {0x60, 0x03}, // Write Base Address MSB register 0x3F8=0D + {0x70, 0x04}, // Write IRQ1 value (IRQ 1) keyboard=0D + {0x30, 0x01} // Enable serial port with Activation bit=0D +};=0D +=0D +/**=0D + Detect if a National 393 SIO is docked. If yes, enable the docked SIO=0D + and its serial port, and disable the onboard serial port.=0D +=0D + @retval EFI_SUCCESS Operations performed successfully.=0D +**/=0D +STATIC=0D +VOID=0D +CheckNationalSio (=0D + VOID=0D + )=0D +{=0D + UINT8 Data8;=0D +=0D + //=0D + // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f).=0D + // We use (0x2e, 0x2f) which is determined by BADD default strapping=0D + //=0D +=0D + //=0D + // Read the Pc87393 signature=0D + //=0D + IoWrite8 (0x2e, 0x20);=0D + Data8 =3D IoRead8 (0x2f);=0D +=0D + if (Data8 =3D=3D 0xea) {=0D + //=0D + // Signature matches - National PC87393 SIO is docked=0D + //=0D +=0D + //=0D + // Enlarge the LPC decode scope to accommodate the Docking LPC Switch= =0D + // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated at=0D + // SIO_BASE_ADDRESS + 0x10)=0D + //=0D + PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & (UINT16)~0x7= F), 0x20);=0D +=0D + //=0D + // Enable port switch=0D + //=0D + IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06);=0D +=0D + //=0D + // Turn on docking power=0D + //=0D + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c);=0D +=0D + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c);=0D +=0D + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc);=0D +=0D + //=0D + // Enable port switch=0D + //=0D + IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7);=0D +=0D + //=0D + // GPIO setting=0D + //=0D + IoWrite8 (0x2e, 0x24);=0D + IoWrite8 (0x2f, 0x29);=0D +=0D + //=0D + // Enable chip clock=0D + //=0D + IoWrite8 (0x2e, 0x29);=0D + IoWrite8 (0x2f, 0x1e);=0D +=0D +=0D + //=0D + // Enable serial port=0D + //=0D +=0D + //=0D + // Select com1=0D + //=0D + IoWrite8 (0x2e, 0x7);=0D + IoWrite8 (0x2f, 0x3);=0D +=0D + //=0D + // Base address: 0x3f8=0D + //=0D + IoWrite8 (0x2e, 0x60);=0D + IoWrite8 (0x2f, 0x03);=0D + IoWrite8 (0x2e, 0x61);=0D + IoWrite8 (0x2f, 0xf8);=0D +=0D + //=0D + // Interrupt: 4=0D + //=0D + IoWrite8 (0x2e, 0x70);=0D + IoWrite8 (0x2f, 0x04);=0D +=0D + //=0D + // Enable bank selection=0D + //=0D + IoWrite8 (0x2e, 0xf0);=0D + IoWrite8 (0x2f, 0x82);=0D +=0D + //=0D + // Activate=0D + //=0D + IoWrite8 (0x2e, 0x30);=0D + IoWrite8 (0x2f, 0x01);=0D +=0D + //=0D + // Disable onboard serial port=0D + //=0D + IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55);=0D +=0D + //=0D + // Power Down UARTs=0D + //=0D + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2);=0D + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00);=0D +=0D + //=0D + // Dissable COM1 decode=0D + //=0D + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24);=0D + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);=0D +=0D + //=0D + // Disable COM2 decode=0D + //=0D + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25);=0D + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);=0D +=0D + //=0D + // Disable interrupt=0D + //=0D + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28);=0D + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0);=0D +=0D + IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);=0D +=0D + //=0D + // Enable floppy=0D + //=0D +=0D + //=0D + // Select floppy=0D + //=0D + IoWrite8 (0x2e, 0x7);=0D + IoWrite8 (0x2f, 0x0);=0D +=0D + //=0D + // Base address: 0x3f0=0D + //=0D + IoWrite8 (0x2e, 0x60);=0D + IoWrite8 (0x2f, 0x03);=0D + IoWrite8 (0x2e, 0x61);=0D + IoWrite8 (0x2f, 0xf0);=0D +=0D + //=0D + // Interrupt: 6=0D + //=0D + IoWrite8 (0x2e, 0x70);=0D + IoWrite8 (0x2f, 0x06);=0D +=0D + //=0D + // DMA 2=0D + //=0D + IoWrite8 (0x2e, 0x74);=0D + IoWrite8 (0x2f, 0x02);=0D +=0D + //=0D + // Activate=0D + //=0D + IoWrite8 (0x2e, 0x30);=0D + IoWrite8 (0x2f, 0x01);=0D +=0D + } else {=0D +=0D + //=0D + // No National pc87393 SIO is docked, turn off dock power and=0D + // disable port switch=0D + //=0D + // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf);=0D + // IoWrite8 (0x690, 0);=0D +=0D + //=0D + // If no National pc87393, just return=0D + //=0D + return;=0D + }=0D +}=0D +=0D +=0D +/**=0D +Check whether the IT8628 SIO present on LPC. If yes, enable its serial=0D +ports, parallel port, and port 80.=0D +=0D +@retval EFI_SUCCESS Operations performed successfully.=0D +**/=0D +STATIC=0D +VOID=0D +It8628SioSerialPortInit (=0D + VOID=0D + )=0D +{=0D + UINT8 ChipId0 =3D 0;=0D + UINT8 ChipId1 =3D 0;=0D + UINT16 LpcIoDecondeRangeSet =3D 0;=0D + UINT16 LpcIoDecoodeSet =3D 0;=0D + UINT8 Index;=0D + UINTN LpcBaseAddr;=0D +=0D +=0D + //=0D + // Enable I/O decoding for COM1 (3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2= Eh/2Fh.=0D + //=0D + LpcBaseAddr =3D MmPciBase (=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + PCI_DEVICE_NUMBER_PCH_LPC,=0D + PCI_FUNCTION_NUMBER_PCH_LPC=0D + );=0D +=0D + LpcIoDecondeRangeSet =3D (UINT16) MmioRead16 (LpcBaseAddr + R_PCH_LPC_IO= D);=0D + LpcIoDecoodeSet =3D (UINT16) MmioRead16 (LpcBaseAddr + R_PCH_LPC_IOE);=0D + MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOD), (LpcIoDecondeRangeSet | ((V_= PCH_LPC_IOD_COMB_2F8 << 4) | V_PCH_LPC_IOD_COMA_3F8)));=0D + MmioWrite16 ((LpcBaseAddr + R_PCH_LPC_IOE), (LpcIoDecoodeSet | (B_PCH_LP= C_IOE_SE | B_PCH_LPC_IOE_CBE | B_PCH_LPC_IOE_CAE)));=0D +=0D + //=0D + // Enter MB PnP Mode=0D + //=0D + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x87);=0D + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x01);=0D + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55);=0D + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x55);=0D +=0D + //=0D + // Read Chip Id of SIO IT8628 (registers 0x20 and 0x21)=0D + //=0D + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x20);=0D + ChipId0 =3D IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);=0D +=0D + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x21);=0D + ChipId1 =3D IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);=0D +=0D + //=0D + // Enable Serial Port 1, Port 2=0D + //=0D + if ((ChipId0 =3D=3D 0x86) && (ChipId1 =3D=3D 0x28)) {=0D + for (Index =3D 0; Index < sizeof (mSioIt8628TableSerialPort) / sizeof = (EFI_SIO_TABLE); Index++) {=0D + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, mSioIt8628TableSerialPort[In= dex].Register);=0D + IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Ind= ex].Value);=0D + }=0D + }=0D +=0D + //=0D + // Exit MB PnP Mode=0D + //=0D + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x02);=0D + IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, 0x02);=0D +=0D + return;=0D +}=0D +=0D +=0D +/**=0D + Performs platform specific initialization required for the CPU to access= =0D + the hardware associated with a SerialPortLib instance. This function do= es=0D + not initialize the serial port hardware itself. Instead, it initializes= =0D + hardware devices that are required for the CPU to access the serial port= =0D + hardware. This function may be called more than once.=0D +=0D + @retval RETURN_SUCCESS The platform specific initialization succee= ded.=0D + @retval RETURN_DEVICE_ERROR The platform specific initialization could = not be completed.=0D +=0D +**/=0D +RETURN_STATUS=0D +EFIAPI=0D +PlatformHookSerialPortInitialize (=0D + VOID=0D + )=0D +{=0D + UINT16 ConfigPort;=0D + UINT16 IndexPort;=0D + UINT16 DataPort;=0D + UINT16 DeviceId;=0D + UINT8 Index;=0D + UINT16 AcpiBase;=0D +=0D + //=0D + // Set the ICH ACPI Base Address (Reg#40h) and ACPI Enable bit=0D + // in ACPI Controll (Reg#44h bit7) for PrePpiStall function use.=0D + //=0D + IndexPort =3D 0;=0D + DataPort =3D 0;=0D + Index =3D 0;=0D + AcpiBase =3D 0;=0D + PchAcpiBaseGet (&AcpiBase);=0D + if (AcpiBase =3D=3D 0) {=0D + PchAcpiBaseSet (PcdGet16 (PcdAcpiBaseAddress));=0D + }=0D +=0D + //=0D + // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2E= h/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h.=0D + //=0D + PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));=0D + PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));=0D +=0D + // Configure Sio IT8628=0D + It8628SioSerialPortInit ();=0D +=0D + DeviceId =3D MmioRead16 (MmPciBase (SA_MC_BUS, 0, 0) + R_SA_MC_DEVICE_ID= );=0D + if (IS_SA_DEVICE_ID_MOBILE (DeviceId)) {=0D + //=0D + // if no EC, it is SV Bidwell Bar board=0D + //=0D + if ((IoRead8 (0x66) !=3D 0xFF) && (IoRead8 (0x62) !=3D 0xFF)) {=0D + //=0D + // Super I/O initialization for SMSC SI1007=0D + //=0D + ConfigPort =3D FixedPcdGet16 (PcdLpcSioConfigDefaultPort);=0D + DataPort =3D PcdGet16 (PcdLpcSioDataDefaultPort);=0D + IndexPort =3D PcdGet16 (PcdLpcSioIndexDefaultPort);=0D +=0D + //=0D + // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF;=0D + //=0D + PchLpcGenIoRangeSet (FixedPcdGet16 (PcdSioBaseAddress) & (~0x7F), 0x= 10);=0D +=0D + //=0D + // Program and Enable Default Super IO Configuration Port Addresses = and range=0D + //=0D + PchLpcGenIoRangeSet (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & (~= 0xF), 0x10);=0D +=0D + //=0D + // Enter Config Mode=0D + //=0D + IoWrite8 (ConfigPort, 0x55);=0D +=0D + //=0D + // Check for SMSC SIO1007=0D + //=0D + IoWrite8 (IndexPort, 0x0D); // SMSC SIO1007 Device ID register is = 0x0D=0D + if (IoRead8 (DataPort) =3D=3D 0x20) { // SMSC SIO1007 Device ID is= 0x20=0D + //=0D + // Configure SIO=0D + //=0D + for (Index =3D 0; Index < sizeof (mSioTable) / sizeof (EFI_SIO_TAB= LE); Index++) {=0D + IoWrite8 (IndexPort, mSioTable[Index].Register);=0D + IoWrite8 (DataPort, mSioTable[Index].Value);=0D + }=0D +=0D + //=0D + // Exit Config Mode=0D + //=0D + IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);=0D +=0D + //=0D + // GPIO 15-17:IN 10-14:OUT Enable RS232 ref: Page42 of CRB_SCH= =0D + //=0D + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0c, 0x1f);=0D + }=0D +=0D + //=0D + // Check if a National Pc87393 SIO is docked=0D + //=0D + CheckNationalSio ();=0D +=0D + //=0D + // Super I/O initialization for SMSC SIO1000=0D + //=0D + ConfigPort =3D PcdGet16 (PcdLpcSioIndexPort);=0D + IndexPort =3D PcdGet16 (PcdLpcSioIndexPort);=0D + DataPort =3D PcdGet16 (PcdLpcSioDataPort);=0D +=0D + //=0D + // Enter Config Mode=0D + //=0D + IoWrite8 (ConfigPort, 0x55);=0D +=0D + //=0D + // Check for SMSC SIO1000=0D + //=0D + if (IoRead8 (ConfigPort) !=3D 0xFF) {=0D + //=0D + // Configure SIO=0D + //=0D + for (Index =3D 0; Index < sizeof (mSioTableSmsc1000) / sizeof (EFI= _SIO_TABLE); Index++) {=0D + IoWrite8 (IndexPort, mSioTableSmsc1000[Index].Register);=0D + IoWrite8 (DataPort, mSioTableSmsc1000[Index].Value);=0D + }=0D +=0D + //=0D + // Exit Config Mode=0D + //=0D + IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);=0D + }=0D +=0D + //=0D + // Super I/O initialization for Winbond WPCN381U=0D + //=0D + IndexPort =3D LPC_SIO_INDEX_DEFAULT_PORT_2;=0D + DataPort =3D LPC_SIO_DATA_DEFAULT_PORT_2;=0D +=0D + //=0D + // Check for Winbond WPCN381U=0D + //=0D + IoWrite8 (IndexPort, 0x20); // Winbond WPCN381U Device ID re= gister is 0x20=0D + if (IoRead8 (DataPort) =3D=3D 0xF4) { // Winbond WPCN381U Device I= D is 0xF4=0D + //=0D + // Configure SIO=0D + //=0D + for (Index =3D 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI= _SIO_TABLE); Index++) {=0D + IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register);=0D + IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value);=0D + }=0D + }=0D + } //EC is not exist, skip mobile board detection for SV board=0D +=0D + //=0D + //add for SV Bidwell Bar board=0D + //=0D + if (IoRead8 (COM1_BASE) =3D=3D 0xFF) {=0D + //=0D + // Super I/O initialization for Winbond WPCD374 (LDC2) and 8374 (LDC= )=0D + // Looking for LDC2 card first=0D + //=0D + IoWrite8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT, 0x55);=0D + if (IoRead8 (LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT) =3D=3D 0x55) {=0D + IndexPort =3D LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;=0D + DataPort =3D LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT;=0D + } else {=0D + IndexPort =3D LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT;=0D + DataPort =3D LEGACY_DAUGHTER_CARD_SIO_DATA_PORT;=0D + }=0D +=0D + IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID regist= er is 0x20=0D + if (IoRead8 (DataPort) =3D=3D 0xF1) { // Winbond x374 Device ID is= 0xF1=0D + for (Index =3D 0; Index < sizeof (mSioTableWinbondX374) / sizeof (= EFI_SIO_TABLE); Index++) {=0D + IoWrite8 (IndexPort, mSioTableWinbondX374[Index].Register);=0D + IoWrite8 (DataPort, mSioTableWinbondX374[Index].Value);=0D + }=0D + }=0D + }// end of Bidwell Bar SIO initialization=0D + } else if (IS_SA_DEVICE_ID_DESKTOP (DeviceId) || IS_SA_DEVICE_ID_SERVER= (DeviceId)) {=0D + //=0D + // If we are in debug mode, we will allow serial status codes=0D + //=0D +=0D + //=0D + // National PC8374 SIO & Winbond WPCD374 (LDC2)=0D + //=0D + IndexPort =3D LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;=0D +=0D + IoWrite8 (IndexPort, 0x55);=0D + if (IoRead8 (IndexPort) =3D=3D 0x55) {=0D + IndexPort =3D LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;=0D + DataPort =3D LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT;=0D + } else {=0D + IndexPort =3D LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT;=0D + DataPort =3D LEGACY_DAUGHTER_CARD_SIO_DATA_PORT;=0D + }=0D +=0D + //=0D + // Configure SIO=0D + //=0D + IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID register= is 0x20=0D + if (IoRead8 (DataPort) =3D=3D 0xF1) { // Winbond x374 Device ID is 0= xF1=0D + for (Index =3D 0; Index < sizeof (mDesktopSioTable) / sizeof (EFI_SI= O_TABLE); Index++) {=0D + IoWrite8 (IndexPort, mDesktopSioTable[Index].Register);=0D + //PrePpiStall (200);=0D + IoWrite8 (DataPort, mDesktopSioTable[Index].Value);=0D + //PrePpiStall (200);=0D + }=0D + return RETURN_SUCCESS;=0D + }=0D + //=0D + // Configure Pilot3 SIO=0D + //=0D + IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_UNLOCK); //Enter config mo= de.=0D + IoWrite8 (PILOTIII_SIO_INDEX_PORT, PILOTIII_CHIP_ID_REG); // Pilot= 3 SIO Device ID register is 0x20.=0D + if (IoRead8 (PILOTIII_SIO_DATA_PORT) =3D=3D PILOTIII_CHIP_ID) { // = Pilot3 SIO Device ID register is 0x03.=0D + //=0D + // Configure SIO=0D + //=0D + for (Index =3D 0; Index < sizeof (mSioTablePilot3) / sizeof (EFI_SIO= _TABLE); Index++) {=0D + IoWrite8 (PILOTIII_SIO_INDEX_PORT, mSioTablePilot3[Index].Register= );=0D + IoWrite8 (PILOTIII_SIO_DATA_PORT, mSioTablePilot3[Index].Value);=0D + }=0D + }=0D + IoWrite8 (PILOTIII_SIO_INDEX_PORT , PILOTIII_LOCK); //Exit config mode= .=0D + }=0D +=0D +=0D + return RETURN_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/KabylakeOpenBo= ardPkg/AspireVn7Dash572G/Library/BasePlatformHookLib/BasePlatformHookLib.inf new file mode 100644 index 000000000000..7a5e290657f2 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BasePla= tformHookLib/BasePlatformHookLib.inf @@ -0,0 +1,51 @@ +### @file=0D +# Platform Hook Library instance for Kaby Lake RVP3.=0D +#=0D +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +###=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D BasePlatformHookLib=0D + FILE_GUID =3D E22ADCC6-ED90-4A90-9837-C8E7FF9E963D= =0D + VERSION_STRING =3D 1.0=0D + MODULE_TYPE =3D BASE=0D + LIBRARY_CLASS =3D PlatformHookLib=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D +#=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + IoLib=0D + MmPciLib=0D + PciLib=0D + PchCycleDecodingLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + KabylakeOpenBoardPkg/OpenBoardPkg.dec=0D + KabylakeSiliconPkg/SiPkg.dec=0D +=0D +[Pcd]=0D + gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSU= MES=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort ## CONSU= MES=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort ## CONSU= MES=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort ## CONSU= MES=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataDefaultPort ## CONSU= MES=0D +=0D +[FixedPcd]=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSU= MES=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress ## CONSU= MES=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSU= MES=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSU= MES=0D +=0D +[Sources]=0D + BasePlatformHookLib.c=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/DxeBoardAcpiTableLib.c b/Platform/Intel/KabylakeOpenBoardPkg/A= spireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c new file mode 100644 index 000000000000..8699f8d4033f --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/DxeBoardAcpiTableLib.c @@ -0,0 +1,36 @@ +/** @file=0D + Kaby Lake RVP 3 Board ACPI library=0D +=0D +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3BoardUpdateAcpiTable (=0D + IN OUT EFI_ACPI_COMMON_HEADER *Table,=0D + IN OUT EFI_ACPI_TABLE_VERSION *Version=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +BoardUpdateAcpiTable (=0D + IN OUT EFI_ACPI_COMMON_HEADER *Table,=0D + IN OUT EFI_ACPI_TABLE_VERSION *Version=0D + )=0D +{=0D + KabylakeRvp3BoardUpdateAcpiTable (Table, Version);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/DxeBoardAcpiTableLib.inf b/Platform/Intel/KabylakeOpenBoardPkg= /AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf new file mode 100644 index 000000000000..e0bf5823d8c6 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/DxeBoardAcpiTableLib.inf @@ -0,0 +1,48 @@ +### @file=0D +# Kaby Lake RVP 3 Board ACPI library=0D +#=0D +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +###=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D DxeBoardAcpiTableLib=0D + FILE_GUID =3D 6562E0AE-90D8-4D41-8C97-81286B4BE7D2= =0D + VERSION_STRING =3D 1.0=0D + MODULE_TYPE =3D BASE=0D + LIBRARY_CLASS =3D BoardAcpiTableLib=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D +#=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + IoLib=0D + PciLib=0D + AslUpdateLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + KabylakeOpenBoardPkg/OpenBoardPkg.dec=0D + KabylakeSiliconPkg/SiPkg.dec=0D + BoardModulePkg/BoardModulePkg.dec=0D +=0D +[Pcd]=0D + gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdNativeAspmEnable=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress=0D +=0D +[Sources]=0D + DxeKabylakeRvp3AcpiTableLib.c=0D + DxeBoardAcpiTableLib.c=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/DxeKabylakeRvp3AcpiTableLib.c b/Platform/Intel/KabylakeOpenBoa= rdPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeKabylakeRvp3AcpiTableLib.c new file mode 100644 index 000000000000..d66283f7e830 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/DxeKabylakeRvp3AcpiTableLib.c @@ -0,0 +1,76 @@ +/** @file=0D + Kaby Lake RVP 3 Board ACPI Library=0D +=0D +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED EFI_GLOBAL_NVS_AREA_PROTOCOL mG= lobalNvsArea;=0D +=0D +VOID=0D +KabylakeRvp3UpdateGlobalNvs (=0D + VOID=0D + )=0D +{=0D +=0D + //=0D + // Allocate and initialize the NVS area for SMM and ASL communication.=0D + //=0D + mGlobalNvsArea.Area =3D (VOID *)(UINTN)PcdGet64 (PcdAcpiGnvsAddress);=0D +=0D + //=0D + // Update global NVS area for ASL and SMM init code to use=0D + //=0D +=0D + //=0D + // Enable PowerState=0D + //=0D + mGlobalNvsArea.Area->PowerState =3D 1; // AC =3D1; for mobile platform, = will update this value in SmmPlatform.c=0D +=0D + mGlobalNvsArea.Area->NativePCIESupport =3D PcdGet8 (PcdPciExpNati= ve);=0D +=0D + //=0D + // Enable APIC=0D + //=0D + mGlobalNvsArea.Area->ApicEnable =3D GLOBAL_NVS_DEVICE_ENABLE;=0D +=0D + //=0D + // Low Power S0 Idle - Enabled/Disabled=0D + //=0D + mGlobalNvsArea.Area->LowPowerS0Idle =3D PcdGet8 (PcdLowPowerS0Idle);=0D +=0D + mGlobalNvsArea.Area->Ps2MouseEnable =3D FALSE;=0D + mGlobalNvsArea.Area->Ps2KbMsEnable =3D PcdGet8 (PcdPs2KbMsEnable);= =0D +=0D + mGlobalNvsArea.Area->BoardId =3D (UINT8) LibPcdGetSku ();=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3BoardUpdateAcpiTable (=0D + IN OUT EFI_ACPI_COMMON_HEADER *Table,=0D + IN OUT EFI_ACPI_TABLE_VERSION *Version=0D + )=0D +{=0D + if (Table->Signature =3D=3D EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTI= ON_TABLE_SIGNATURE) {=0D + KabylakeRvp3UpdateGlobalNvs ();=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c b/Platform/Intel/KabylakeOpenBoa= rdPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c new file mode 100644 index 000000000000..dfb1b028f18f --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/DxeMultiBoardAcpiSupportLib.c @@ -0,0 +1,43 @@ +/** @file=0D + Kaby Lake RVP 3 Multi-Board ACPI Support library=0D +=0D +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3BoardUpdateAcpiTable (=0D + IN OUT EFI_ACPI_COMMON_HEADER *Table,=0D + IN OUT EFI_ACPI_TABLE_VERSION *Version=0D + );=0D +=0D +BOARD_ACPI_TABLE_FUNC mKabylakeRvp3BoardAcpiTableFunc =3D {=0D + KabylakeRvp3BoardUpdateAcpiTable=0D +};=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +DxeKabylakeRvp3MultiBoardAcpiSupportLibConstructor (=0D + VOID=0D + )=0D +{=0D + if ((LibPcdGetSku () =3D=3D BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetSku= () =3D=3D BoardIdSkylakeRvp3)) {=0D + return RegisterBoardAcpiTableFunc (&mKabylakeRvp3BoardAcpiTableFunc);= =0D + }=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf b/Platform/Intel/KabylakeOpenB= oardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.= inf new file mode 100644 index 000000000000..e5de9268e71e --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/DxeMultiBoardAcpiSupportLib.inf @@ -0,0 +1,49 @@ +### @file=0D +# Kaby Lake RVP 3 Multi-Board ACPI Support library=0D +#=0D +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +###=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D DxeKabylakeRvp3MultiBoardAcpiTableLib= =0D + FILE_GUID =3D 8E6A3B38-53E0-48C0-970F-058F380FCB80= =0D + VERSION_STRING =3D 1.0=0D + MODULE_TYPE =3D BASE=0D + LIBRARY_CLASS =3D NULL=0D + CONSTRUCTOR =3D DxeKabylakeRvp3MultiBoardAcpiSupportL= ibConstructor=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D +#=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + IoLib=0D + PciLib=0D + AslUpdateLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + KabylakeOpenBoardPkg/OpenBoardPkg.dec=0D + KabylakeSiliconPkg/SiPkg.dec=0D + BoardModulePkg/BoardModulePkg.dec=0D +=0D +[Pcd]=0D + gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdNativeAspmEnable=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress=0D +=0D +[Sources]=0D + DxeKabylakeRvp3AcpiTableLib.c=0D + DxeMultiBoardAcpiSupportLib.c=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/SmmBoardAcpiEnableLib.c b/Platform/Intel/KabylakeOpenBoardPkg/= AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c new file mode 100644 index 000000000000..e89624ea0372 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/SmmBoardAcpiEnableLib.c @@ -0,0 +1,62 @@ +/** @file=0D + Kaby Lake RVP 3 SMM Board ACPI Enable library=0D +=0D +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3BoardEnableAcpi (=0D + IN BOOLEAN EnableSci=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3BoardDisableAcpi (=0D + IN BOOLEAN DisableSci=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +SiliconEnableAcpi (=0D + IN BOOLEAN EnableSci=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +SiliconDisableAcpi (=0D + IN BOOLEAN DisableSci=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +BoardEnableAcpi (=0D + IN BOOLEAN EnableSci=0D + )=0D +{=0D + SiliconEnableAcpi (EnableSci);=0D + return KabylakeRvp3BoardEnableAcpi (EnableSci);=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +BoardDisableAcpi (=0D + IN BOOLEAN DisableSci=0D + )=0D +{=0D + SiliconDisableAcpi (DisableSci);=0D + return KabylakeRvp3BoardDisableAcpi (DisableSci);=0D +}=0D +=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/SmmBoardAcpiEnableLib.inf b/Platform/Intel/KabylakeOpenBoardPk= g/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf new file mode 100644 index 000000000000..46a714dc1d97 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/SmmBoardAcpiEnableLib.inf @@ -0,0 +1,47 @@ +### @file=0D +# Kaby Lake RVP 3 SMM Board ACPI Enable library=0D +#=0D +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +###=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D SmmBoardAcpiEnableLib=0D + FILE_GUID =3D 549E69AE-D3B3-485B-9C17-AF16E20A58AD= =0D + VERSION_STRING =3D 1.0=0D + MODULE_TYPE =3D BASE=0D + LIBRARY_CLASS =3D BoardAcpiEnableLib=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D +#=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + IoLib=0D + PciLib=0D + MmPciLib=0D + PchCycleDecodingLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + KabylakeOpenBoardPkg/OpenBoardPkg.dec=0D + KabylakeSiliconPkg/SiPkg.dec=0D +=0D +[Pcd]=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUME= S=0D +=0D +[Protocols]=0D +=0D +[Sources]=0D + SmmKabylakeRvp3AcpiEnableLib.c=0D + SmmSiliconAcpiEnableLib.c=0D + SmmBoardAcpiEnableLib.c=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/SmmKabylakeRvp3AcpiEnableLib.c b/Platform/Intel/KabylakeOpenBo= ardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmKabylakeRvp3AcpiEnableLib.c new file mode 100644 index 000000000000..54755dd17695 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/SmmKabylakeRvp3AcpiEnableLib.c @@ -0,0 +1,39 @@ +/** @file=0D + Kaby Lake RVP 3 SMM Board ACPI Enable library=0D +=0D +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3BoardEnableAcpi (=0D + IN BOOLEAN EnableSci=0D + )=0D +{=0D + // enable additional board register=0D + return EFI_SUCCESS;=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3BoardDisableAcpi (=0D + IN BOOLEAN DisableSci=0D + )=0D +{=0D + // enable additional board register=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/KabylakeOpenBoa= rdPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c new file mode 100644 index 000000000000..fb678a19bcf9 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/SmmMultiBoardAcpiSupportLib.c @@ -0,0 +1,81 @@ +/** @file=0D + Kaby Lake RVP 3 SMM Multi-Board ACPI Support library=0D +=0D +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3BoardEnableAcpi (=0D + IN BOOLEAN EnableSci=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3BoardDisableAcpi (=0D + IN BOOLEAN DisableSci=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +SiliconEnableAcpi (=0D + IN BOOLEAN EnableSci=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +SiliconDisableAcpi (=0D + IN BOOLEAN DisableSci=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3MultiBoardEnableAcpi (=0D + IN BOOLEAN EnableSci=0D + )=0D +{=0D + SiliconEnableAcpi (EnableSci);=0D + return KabylakeRvp3BoardEnableAcpi (EnableSci);=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3MultiBoardDisableAcpi (=0D + IN BOOLEAN DisableSci=0D + )=0D +{=0D + SiliconDisableAcpi (DisableSci);=0D + return KabylakeRvp3BoardDisableAcpi (DisableSci);=0D +}=0D +=0D +BOARD_ACPI_ENABLE_FUNC mKabylakeRvp3BoardAcpiEnableFunc =3D {=0D + KabylakeRvp3MultiBoardEnableAcpi,=0D + KabylakeRvp3MultiBoardDisableAcpi,=0D +};=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +SmmKabylakeRvp3MultiBoardAcpiSupportLibConstructor (=0D + VOID=0D + )=0D +{=0D + if ((LibPcdGetSku () =3D=3D BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetSk= u () =3D=3D BoardIdSkylakeRvp3)) {=0D + return RegisterBoardAcpiEnableFunc (&mKabylakeRvp3BoardAcpiEnableFunc= );=0D + }=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/KabylakeOpenB= oardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.= inf new file mode 100644 index 000000000000..fca63c831431 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/SmmMultiBoardAcpiSupportLib.inf @@ -0,0 +1,48 @@ +### @file=0D +# Kaby Lake RVP 3 SMM Multi-Board ACPI Support library=0D +#=0D +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +###=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D SmmKabylakeRvp3MultiBoardAcpiSupportL= ib=0D + FILE_GUID =3D 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5= =0D + VERSION_STRING =3D 1.0=0D + MODULE_TYPE =3D BASE=0D + LIBRARY_CLASS =3D NULL=0D + CONSTRUCTOR =3D SmmKabylakeRvp3MultiBoardAcpiSupportL= ibConstructor=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D +#=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + IoLib=0D + PciLib=0D + MmPciLib=0D + PchCycleDecodingLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + KabylakeOpenBoardPkg/OpenBoardPkg.dec=0D + KabylakeSiliconPkg/SiPkg.dec=0D +=0D +[Pcd]=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUME= S=0D +=0D +[Protocols]=0D +=0D +[Sources]=0D + SmmKabylakeRvp3AcpiEnableLib.c=0D + SmmSiliconAcpiEnableLib.c=0D + SmmMultiBoardAcpiSupportLib.c=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardAcpiLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/KabylakeOpenBoardPk= g/AspireVn7Dash572G/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c new file mode 100644 index 000000000000..7f63a12bf461 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAc= piLib/SmmSiliconAcpiEnableLib.c @@ -0,0 +1,168 @@ +/** @file=0D + Kaby Lake RVP 3 SMM Silicon ACPI Enable library=0D +=0D +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Clear Port 80h=0D +=0D + SMI handler to enable ACPI mode=0D +=0D + Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI=0D +=0D + Disables the SW SMI Timer.=0D + ACPI events are disabled and ACPI event status is cleared.=0D + SCI mode is then enabled.=0D +=0D + Clear SLP SMI status=0D + Enable SLP SMI=0D +=0D + Disable SW SMI Timer=0D +=0D + Clear all ACPI event status and disable all ACPI events=0D +=0D + Disable PM sources except power button=0D + Clear status bits=0D +=0D + Disable GPE0 sources=0D + Clear status bits=0D +=0D + Disable GPE1 sources=0D + Clear status bits=0D +=0D + Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)=0D +=0D + Enable SCI=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SiliconEnableAcpi (=0D + IN BOOLEAN EnableSci=0D + )=0D +{=0D + UINT32 OutputValue;=0D + UINT32 SmiEn;=0D + UINT32 SmiSts;=0D + UINT32 ULKMC;=0D + UINTN LpcBaseAddress;=0D + UINT16 AcpiBaseAddr;=0D + UINT32 Pm1Cnt;=0D +=0D + LpcBaseAddress =3D MmPciBase (=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + PCI_DEVICE_NUMBER_PCH_LPC,=0D + PCI_FUNCTION_NUMBER_PCH_LPC=0D + );=0D +=0D + //=0D + // Get the ACPI Base Address=0D + //=0D + PchAcpiBaseGet (&AcpiBaseAddr);=0D +=0D + //=0D + // BIOS must also ensure that CF9GR is cleared and locked before handing= control to the=0D + // OS in order to prevent the host from issuing global resets and resett= ing ME=0D + //=0D + // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Res= et=0D + // MmioWrite32 (=0D + // PmcBaseAddress + R_PCH_PMC_ETR3),=0D + // PmInit);=0D +=0D + //=0D + // Clear Port 80h=0D + //=0D + IoWrite8 (0x80, 0);=0D +=0D + //=0D + // Disable SW SMI Timer and clean the status=0D + //=0D + SmiEn =3D IoRead32 (AcpiBaseAddr + R_PCH_SMI_EN);=0D + SmiEn &=3D ~(B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_SWSMI_TMR | B_PCH_S= MI_EN_LEGACY_USB);=0D + IoWrite32 (AcpiBaseAddr + R_PCH_SMI_EN, SmiEn);=0D +=0D + SmiSts =3D IoRead32 (AcpiBaseAddr + R_PCH_SMI_STS);=0D + SmiSts |=3D B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SM= I_EN_LEGACY_USB;=0D + IoWrite32 (AcpiBaseAddr + R_PCH_SMI_STS, SmiSts);=0D +=0D + //=0D + // Disable port 60/64 SMI trap if they are enabled=0D + //=0D + ULKMC =3D MmioRead32 (LpcBaseAddress + R_PCH_LPC_ULKMC) & ~(B_PCH_LPC_UL= KMC_60REN | B_PCH_LPC_ULKMC_60WEN | B_PCH_LPC_ULKMC_64REN | B_PCH_LPC_ULKMC= _64WEN | B_PCH_LPC_ULKMC_A20PASSEN);=0D + MmioWrite32 (LpcBaseAddress + R_PCH_LPC_ULKMC, ULKMC);=0D +=0D + //=0D + // Disable PM sources except power button=0D + //=0D + IoWrite16 (AcpiBaseAddr + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN);= =0D +=0D + //=0D + // Clear PM status except Power Button status for RapidStart Resume=0D + //=0D + IoWrite16 (AcpiBaseAddr + R_PCH_ACPI_PM1_STS, 0xFEFF);=0D +=0D + //=0D + // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)=0D + //=0D + IoWrite8 (R_PCH_RTC_INDEX_ALT, R_PCH_RTC_REGD);=0D + IoWrite8 (R_PCH_RTC_TARGET_ALT, 0x0);=0D +=0D + //=0D + // Write ALT_GPI_SMI_EN to disable GPI1 (SMC_EXTSMI#)=0D + //=0D + OutputValue =3D IoRead32 (AcpiBaseAddr + 0x38);=0D + OutputValue =3D OutputValue & ~(1 << (UINTN) PcdGet8 (PcdSmcExtSmiBitPos= ition));=0D + IoWrite32 (AcpiBaseAddr + 0x38, OutputValue);=0D +=0D +=0D + //=0D + // Enable SCI=0D + //=0D + if (EnableSci) {=0D + Pm1Cnt =3D IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT);=0D + Pm1Cnt |=3D B_PCH_ACPI_PM1_CNT_SCI_EN;=0D + IoWrite32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt);=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +SiliconDisableAcpi (=0D + IN BOOLEAN DisableSci=0D + )=0D +{=0D + UINT16 AcpiBaseAddr;=0D + UINT32 Pm1Cnt;=0D +=0D + //=0D + // Get the ACPI Base Address=0D + //=0D + PchAcpiBaseGet (&AcpiBaseAddr);=0D +=0D + //=0D + // Disable SCI=0D + //=0D + if (DisableSci) {=0D + Pm1Cnt =3D IoRead32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT);=0D + Pm1Cnt &=3D ~B_PCH_ACPI_PM1_CNT_SCI_EN;=0D + IoWrite32 (AcpiBaseAddr + R_PCH_ACPI_PM1_CNT, Pm1Cnt);=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/KabylakeRvp3GpioTable.c b/Platform/Intel/KabylakeOpenBoardPkg/= AspireVn7Dash572G/Library/BoardInitLib/KabylakeRvp3GpioTable.c new file mode 100644 index 000000000000..2439c6bc1edc --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/KabylakeRvp3GpioTable.c @@ -0,0 +1,381 @@ +/** @file=0D + GPIO definition table for KabylakeRvp3=0D +=0D +Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef _KABYLAKE_RVP3_GPIO_TABLE_H_=0D +#define _KABYLAKE_RVP3_GPIO_TABLE_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +=0D +#define END_OF_GPIO_TABLE 0xFFFFFFFF=0D +=0D +GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[] =3D=0D +{=0D +//skip for eSPI function {GPIO_SKL_LP_GPP_A0, {GpioPadModeNative1, GpioHo= stOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, Gp= ioTermNone}},//H_RCIN_N=0D +//skip for eSPI function {GPIO_SKL_LP_GPP_A1, {GpioPadModeNative1, GpioHo= stOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, Gp= ioTermWpd20K}},//LPC_AD0_ESPI_IO0=0D +//skip for eSPI function {GPIO_SKL_LP_GPP_A2, {GpioPadModeNative1, GpioHo= stOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, Gp= ioTermWpd20K}},//LPC_AD1_ESPI_IO1=0D +//skip for eSPI function {GPIO_SKL_LP_GPP_A3, {GpioPadModeNative1, GpioHo= stOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, Gp= ioTermWpd20K}},//LPC_AD2_ESPI_IO2=0D +//skip for eSPI function {GPIO_SKL_LP_GPP_A4, {GpioPadModeNative1, GpioHo= stOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, Gp= ioTermWpd20K}},//LPC_AD3_ESPI_IO3=0D +//skip for eSPI function {GPIO_SKL_LP_GPP_A5, {GpioPadModeNative1, GpioH= ostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, G= pioTermNone}},//LPC_FRAME_ESPI_CS_N=0D +//skip for eSPI function {GPIO_SKL_LP_GPP_A6, {GpioPadModeNative1, GpioH= ostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, G= pioTermNone}},//INT_SERIRQ=0D + {GPIO_SKL_LP_GPP_A7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PM_SLP_S= 0ix_R_N=0D +// skip for PM_CLKRUN_N {GPIO_SKL_LP_GPP_A8, {GpioPadModeNative1, GpioHos= tOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, Gpi= oTermNone}},//PM_CLKRUN_N=0D +//skip for eSPI function {GPIO_SKL_LP_GPP_A9, {GpioPadModeNative1, Gpi= oHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, = GpioTermWpd20K}},//LPC_CLK_ESPI_CLK=0D +// skip for PCH_CLK_PCI_TPM {GPIO_SKL_LP_GPP_A10, {GpioPadModeNative1, Gpi= oHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, = GpioTermWpd20K}},//PCH_CLK_PCI_TPM=0D + {GPIO_SKL_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermN= one}},//EC_HID_INTR=0D + {GPIO_SKL_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone}},//M.2_WWAN_GN= SS_UART_RST_N=0D +//skip for SUS_PWR_ACK_R {GPIO_SKL_LP_GPP_A13, {GpioPadModeNative1, GpioH= ostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, G= pioTermNone}},//SUS_PWR_ACK_R=0D +//skip for eSPI function {GPIO_SKL_LP_GPP_A14, {GpioPadModeNative1, Gpi= oHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, = GpioTermNone}},//PM_SUS_STAT_ESPI_RST_N=0D +//skip for SUSACK_R_N {GPIO_SKL_LP_GPP_A15, {GpioPadModeNative1, GpioHost= OwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, Gpio= TermWpd20K}},//SUSACK_R_N=0D + {GPIO_SKL_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_1P8_S= EL=0D + {GPIO_SKL_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_PWR_E= N_N=0D + {GPIO_SKL_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_0= _SENSOR=0D + {GPIO_SKL_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_1= _SENSOR=0D + {GPIO_SKL_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_GP_2= _SENSOR=0D + {GPIO_SKL_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GNSS_CHU= B_IRQ=0D + {GPIO_SKL_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_SLP_= N=0D + {GPIO_SKL_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermN= one}},//FPS_DRDY=0D + {GPIO_SKL_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_V= ID0=0D + {GPIO_SKL_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//V0.85A_V= ID1=0D + {GPIO_SKL_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//GP_VRALE= RTB=0D + {GPIO_SKL_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermN= one}},//TCH_PAD_INTR_R_N=0D + {GPIO_SKL_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//BT_RF_KI= LL_N=0D + {GPIO_SKL_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermN= one}},//M.2_BT_UART_WAKE_N=0D + // {GPIO_SKL_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_R= EQ_SLOT1_N=0D + // {GPIO_SKL_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_R= EQ_SLOT2_LAN_N=0D + // {GPIO_SKL_LP_GPP_B8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_R= EQ_M.2_SSD_SLOT3_N=0D + // {GPIO_SKL_LP_GPP_B9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_R= EQ_M.2_WIGIG_N=0D + // {GPIO_SKL_LP_GPP_B10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNo= ne, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CLK_R= EQ_M.2_WLAN_N=0D + {GPIO_SKL_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//MPHY_EXT= _PWR_GATEB=0D + {GPIO_SKL_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SLP_= S0_N=0D + {GPIO_SKL_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PLT_RST_= N=0D + {GPIO_SKL_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PN= L_PWREN=0D + // {GPIO_SKL_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_N= FC_DFU, NOT OWNED BY BIOS=0D + {GPIO_SKL_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv= , GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNo= ne}},//M.2_WLAN_WIFI_WAKE_N=0D + {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv= , GpioOutDefault, GpioIntEdge | GpioIntSci, GpioPlatformReset, GpioTermWpu= 20K}},//TBT_CIO_PLUG_EVENT_N=0D + {GPIO_SKL_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv= , GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermWp= u20K}},//PCH_SLOT1_WAKE_N=0D + {GPIO_SKL_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//FPS_GSP= I1_CS_R1_N=0D + {GPIO_SKL_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GS= PI1_CLK_R1=0D + {GPIO_SKL_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GS= PI1_MISO_R1=0D + {GPIO_SKL_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//FPS_GS= PI1_MOSI_R1=0D + {GPIO_SKL_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DISCRE= TE_GNSS_RESET_N=0D + {GPIO_SKL_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SMB_CLK= =0D + {GPIO_SKL_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SMB_DA= TA=0D + {GPIO_SKL_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SKIN_T= HRM_SNSR_ALERT_N=0D + {GPIO_SKL_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_CLK= =0D + {GPIO_SKL_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML0_DAT= A=0D + {GPIO_SKL_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv= , GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWp= d20K}},//M.2_WIGIG_WAKE_N=0D + {GPIO_SKL_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SML1_CLK= , OWNED BY ME=0D + {GPIO_SKL_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//SML1_D= ATA, OWNED BY ME=0D + {GPIO_SKL_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART0_RXD=0D + {GPIO_SKL_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART0_TXD=0D + {GPIO_SKL_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART0_RTS_N=0D + {GPIO_SKL_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART0_CTS_N=0D + {GPIO_SKL_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART1_ISH_UART1_RXD=0D + {GPIO_SKL_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART1_ISH_UART1_TXD=0D + {GPIO_SKL_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART1_ISH_UART1_RTS_N=0D + {GPIO_SKL_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART1_ISH_UART1_CTS_N=0D + {GPIO_SKL_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _I2C0_SDA=0D + {GPIO_SKL_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _I2C0_SCL=0D + {GPIO_SKL_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _I2C1_SDA=0D + {GPIO_SKL_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _I2C1_SCL=0D + {GPIO_SKL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART2_RXD=0D + {GPIO_SKL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART2_TXD=0D + {GPIO_SKL_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART2_RTS_N=0D + {GPIO_SKL_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO= _UART2_CTS_N=0D + {GPIO_SKL_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCH= PNL_CS_N=0D + {GPIO_SKL_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCH= PNL_CLK=0D + {GPIO_SKL_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCH= PNL_MISO=0D + {GPIO_SKL_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCH= PNL_MOSI=0D + {GPIO_SKL_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//CSI2_FLA= SH_STROBE=0D + {GPIO_SKL_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0= _SDA=0D + {GPIO_SKL_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C0= _SCL=0D + {GPIO_SKL_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1= _SDA=0D + {GPIO_SKL_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_I2C1= _SCL=0D + {GPIO_SKL_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNo= ne}},//HOME_BTN=0D + {GPIO_SKL_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNo= ne}},//SCREEN_LOCK_PCH=0D + {GPIO_SKL_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNo= ne}},//VOL_UP_PCH=0D + {GPIO_SKL_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTermNo= ne}},//VOL_DOWN_PCH=0D + {GPIO_SKL_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART= 0_RXD_SML0B_DATA=0D + {GPIO_SKL_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART= 0_TXD_SML0B_CLK=0D + {GPIO_SKL_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART= 0_RTS_N=0D + {GPIO_SKL_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//ISH_UART= 0_CTS_SML0B_ALERT_N=0D + {GPIO_SKL_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK= _1=0D + {GPIO_SKL_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DMIC_D= ATA_1=0D + {GPIO_SKL_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DMIC_CLK= _0=0D + {GPIO_SKL_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DMIC_D= ATA_0=0D + {GPIO_SKL_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCH= PNL_IO2=0D + {GPIO_SKL_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SPI1_TCH= PNL_IO3=0D + {GPIO_SKL_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP_MCLK= =0D + {GPIO_SKL_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv= , GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNo= ne}},//SPI_TPM_HDR_IRQ_N=0D + {GPIO_SKL_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA_ODD= _PRSNT_N=0D + {GPIO_SKL_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioHostDeepReset, GpioT= ermNone}},//M.2_SSD_SATA2_PCIE3_DET_N=0D + {GPIO_SKL_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//EINK_SSR_D= FU_N=0D + {GPIO_SKL_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_NFC_= RESET=0D + {GPIO_SKL_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA1_PH= YSLP1_DIRECT_R=0D + // {GPIO_SKL_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutLow, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SATA2= _PHYSLP2_M.2SSD_R, NOT OWNED BY BIOS=0D + {GPIO_SKL_LP_GPP_E8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//PCH_SATA= _LED_N=0D + {GPIO_SKL_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_0= _WP1_OTG_N=0D + {GPIO_SKL_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_1= _WP4_N=0D + {GPIO_SKL_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//USB_OC_2= _WP2_WP3_WP5_R_N=0D + // {GPIO_SKL_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn= , GpioOutDefault, GpioIntLevel | GpioIntDis, GpioHostDeepReset, GpioTer= mNone}},//PCH_NFC_IRQ, NOT OWNED BY BIOS=0D + {GPIO_SKL_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_HPD= _Q=0D + {GPIO_SKL_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_HPD= _Q=0D + {GPIO_SKL_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv= , GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioHostDeepReset, GpioTermNon= e}},//SMC_EXTSMI_R_N=0D + {GPIO_SKL_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv= , GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTermNo= ne}},//SMC_RUNTIME_SCI_R_N=0D + {GPIO_SKL_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EDP_HPD= =0D + {GPIO_SKL_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI1_CTR= L_CLK=0D + {GPIO_SKL_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI1_C= TRL_DATA=0D + {GPIO_SKL_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//DDI2_CTR= L_CLK=0D + {GPIO_SKL_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//DDI2_C= TRL_DATA=0D + {GPIO_SKL_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv= , GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermN= one}},//PCH_CODEC_IRQ=0D + {GPIO_SKL_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermWpd20K}},//TCH_PN= L_RST_N=0D + {GPIO_SKL_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SCL= K=0D + {GPIO_SKL_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_SFR= M=0D + {GPIO_SKL_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_TXD= =0D + {GPIO_SKL_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SSP2_RXD= =0D + {GPIO_SKL_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTer= mNone}},//SERIALIO_I2C2_SDA=0D + {GPIO_SKL_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTer= mNone}},//SERIALIO_I2C2_SCL=0D + {GPIO_SKL_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTer= mNone}},//SERIALIO_I2C3_SDA=0D + {GPIO_SKL_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTer= mNone}},//SERIALIO_I2C3_SCL=0D + {GPIO_SKL_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTer= mNone}},//SERIALIO_I2C4_SDA=0D + {GPIO_SKL_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTer= mNone}},//SERIALIO_I2C4_SCL=0D + {GPIO_SKL_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTer= mNone}},//SERIALIO_I2C5_ISH_12C2_SDA=0D + {GPIO_SKL_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTolerance1v8 | GpioTer= mNone}},//SERIALIO_I2C5_ISH_12C2_SCL=0D + {GPIO_SKL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD= =0D + {GPIO_SKL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DAT= A0=0D + {GPIO_SKL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DAT= A1=0D + {GPIO_SKL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DAT= A2=0D + {GPIO_SKL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DAT= A3=0D + {GPIO_SKL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DAT= A4=0D + {GPIO_SKL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DAT= A5=0D + {GPIO_SKL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DAT= A6=0D + {GPIO_SKL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DAT= A7=0D + {GPIO_SKL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCL= K=0D + {GPIO_SKL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK= =0D + {GPIO_SKL_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermN= one}},//PCH_M.2_WWAN_UIM_SIM_DET=0D + {GPIO_SKL_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CMD=0D + {GPIO_SKL_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA0= =0D + {GPIO_SKL_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA1= =0D + {GPIO_SKL_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA2= =0D + {GPIO_SKL_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_DATA3= =0D + {GPIO_SKL_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CDB=0D + {GPIO_SKL_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_CLK=0D + {GPIO_SKL_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,= GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SD_WP=0D + {GPIO_SKL_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_BATLOW_R_N= =0D + {GPIO_SKL_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//AC_PRESENT_R=0D + {GPIO_SKL_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntSci, GpioDswReset, GpioTermNone}},/= /LANWAKE_SMC_WAKE_SCI_N=0D + {GPIO_SKL_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermWpu20K}},//PM_PWRBTN_R_= N=0D + {GPIO_SKL_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S3_R_N=0D + {GPIO_SKL_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S4_R_N=0D + {GPIO_SKL_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_M_R_N=0D + {GPIO_SKL_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//USB_WAKEOUT_IN= TRUDET_N=0D + {GPIO_SKL_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SUS_CLK=0D + {GPIO_SKL_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PCH_SLP_WLAN_N= =0D + {GPIO_SKL_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//SLP_S5_R_N=0D + {GPIO_SKL_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//PM_LANPHY_ENAB= LE=0D + {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of= Table=0D +};=0D +=0D +UINT16 mGpioTableLpDdr3Rvp3Size =3D sizeof (mGpioTableLpDdr3Rvp3) / sizeof= (GPIO_INIT_CONFIG) - 1;=0D +=0D +GPIO_INIT_CONFIG mGpioTableKabyLakeYLpddr3Rvp3[] =3D=0D +{=0D + { GPIO_SKL_LP_GPP_A12, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirNon= e, GpioOutDefault, GpioIntDis, GpioResumeReset, GpioTermNone } },//REALSENS= E_ISH_WAKE=0D + { GPIO_SKL_LP_GPP_A20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirNon= e, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone } },//IRIS_P= ROXI_INTR=0D + { GPIO_SKL_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut= , GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone}},//M.2_WWAN_G= NSS_UART_RST_N=0D + { GPIO_SKL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,= GpioOutDefault, GpioIntEdge | GpioIntApic, GpioHostDeepReset, GpioTermNo= ne } },//SD_CARD_WAKE=0D + { GPIO_SKL_LP_GPP_D11, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirNon= e, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone } },//TYPEC_= P1_DCI_CLK=0D + { GPIO_SKL_LP_GPP_D12, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirNon= e, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone } },//TYPEC_= P1_DCI_DATA=0D +};=0D +=0D +UINT16 mGpioTableKabyLakeYLpddr3Rvp3Size =3D sizeof (mGpioTableKabyLakeYLp= ddr3Rvp3) / sizeof (GPIO_INIT_CONFIG);=0D +=0D +GPIO_INIT_CONFIG mGpioTableLpddr3Rvp3UcmcDevice[] =3D=0D +{=0D + { GPIO_SKL_LP_GPP_B0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone = } }, //GPP_B0=0D + { GPIO_SKL_LP_GPP_B1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, G= pioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone = } }, //GPP_B1=0D +};=0D +=0D +UINT16 mGpioTableLpddr3Rvp3UcmcDeviceSize =3D sizeof (mGpioTableLpddr3Rvp3= UcmcDevice) / sizeof (GPIO_INIT_CONFIG);=0D +=0D +GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3Touchpanel =3D=0D + {GPIO_SKL_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNo= ne}};=0D +=0D +GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3SdhcSidebandCardDetect =3D=0D + {GPIO_SKL_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntBothEdge, GpioHostDeepReset, GpioTermNone}}; //SD_C= DB D3=0D +=0D +//IO Expander Table for SKL RVP7, RVP13 and RVP15=0D +IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[] =3D=0D +{=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_3.3_PWREN_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SNSR_HUB_DFU_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SATA_PWR_EN_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_RST_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WLAN_WAKE_CTRL_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //GFX_CRB_DET_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //MFG_MODE_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //FLIP_TO_TABLET_MODE_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_SLOT1_RST_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB3_CAM_PWREN_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD_TESTMODE_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //BIOS_REC_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //EINK_PWREN_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TBT_FORCE_PWR_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIFI_RST_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //DGPU_PRSNT_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB2_CAM_PWREN_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //IMAGING_DFU_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SW_GFX_PWERGD_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_WAKE_CTRL_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_RST_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TP_IOEXP1_P26=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TP_IOEXP1_P27=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_PWREN_IOEXP=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_DISABLE_IOEXP_N=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_WP4_PWREN_IOEXP=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_OTG_WP1_PWREN_IOEXP=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_WP2_WP3_WP5_PWREN_R_IOEXP=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_AUDIO_PWREN_IOEXP=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_GNSS_DISABLE_IOEXP_N=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED}/= /M.2_WIGIG_PWREN_IOEXP=0D +};=0D +=0D +UINT16 mGpioTableIoExpanderSize =3D sizeof (mGpioTableIoExpander) / sizeof= (IO_EXPANDER_GPIO_CONFIG);=0D +=0D +//IO Expander Table for KBL -Refresh=0D +IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeRDdr4[] =3D=0D +{=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_3.3_PWREN_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SNSR_HUB_DFU_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SATA_PWR_EN_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_RST_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WLAN_WAKE_CTRL_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //GFX_CRB_DET_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //MFG_MODE_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //FLIP_TO_TABLET_MODE_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_SLOT1_RST_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB3_CAM_PWREN_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD_TESTMODE_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //BIOS_REC_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //Unused pin=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TBT_FORCE_PWR_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIFI_RST_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RTD3_USB_PD1_PWR_EN=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB2_CAM_PWREN_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //IMAGING_DFU_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //HRESET_PD1_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_WAKE_CTRL_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_RST_IOEXP_N=0D + //{IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPAN= DER_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED= },//M.2_WWAN_RST_CNTRL_R=0D + // We want the initial state to be high.=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_RST_CNTRL_R=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_WAKE_CTRL_R_N=0D + // Turn off WWAN power and will turn it on later.=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_PWREN_IOEXP=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_DISABLE_IOEXP_N=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_WP2_WP3_WP5_PWREN_R_IOEXP=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_AUDIO_PWREN_IOEXP=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_GNSS_DISABLE_IOEXP_N=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_PWREN_IOEXP=0D +};=0D +UINT16 mGpioTableIoExpanderSizeKabylakeRDdr4 =3D sizeof (mGpioTableIoExpan= derKabylakeRDdr4) / sizeof (IO_EXPANDER_GPIO_CONFIG);=0D +=0D +//IO Expander Table for KBL -kc=0D +IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeKcDdr3[] =3D=0D +{=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_3.3_PWREN_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SNSR_HUB_DFU_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SATA_PWR_EN_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_RST_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WLAN_WAKE_CTRL_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //GFX_CRB_DET_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //MFG_MODE_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //FLIP_TO_TABLET_MODE_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_SLOT1_RST_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB3_CAM_PWREN_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD_TESTMODE_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //BIOS_REC_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //EINK_PWREN_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TBT_FORCE_PWR_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIFI_RST_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB2_CAM_PWREN_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //IMAGING_DFU_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_WAKE_CTRL_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_RST_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TP_IOEXP1_P26=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TP_IOEXP1_P27=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_PWREN_IOEXP=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_DISABLE_IOEXP_N=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_WP4_PWREN_IOEXP=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_OTG_WP1_PWREN_IOEXP=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_WP2_WP3_WP5_PWREN_R_IOEXP=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_AUDIO_PWREN_IOEXP=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_GNSS_DISABLE_IOEXP_N=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_PWREN_IOEXP=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //FPS_LOCK_N=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_FLEX_PWREN=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB_UART_SEL=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_DOCK_PWREN_IOEXP_R=0D +};=0D +UINT16 mGpioTableIoExpanderSizeKabylakeKcDdr3 =3D sizeof (mGpioTableIoExpa= nderKabylakeKcDdr3) / sizeof (IO_EXPANDER_GPIO_CONFIG);=0D +//IO Expander Table Full table for KBL RVP3=0D +IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpanderKabylakeRvp3[] =3D=0D +{=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_3.3_PWREN_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SNSR_HUB_DFU_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SATA_PWR_EN_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_RST_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WLAN_WAKE_CTRL_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //GFX_CRB_DET_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //MFG_MODE_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //FLIP_TO_TABLET_MODE_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_8, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_SLOT1_RST_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_9, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB3_CAM_PWREN_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_10, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //RSVD_TESTMODE_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_11, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //BIOS_REC_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_12, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //EINK_PWREN_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_13, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TBT_FORCE_PWR_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_14, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIFI_RST_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_15, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //DGPU_PRSNT_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_16, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCIE_SLOT1_PWREN_WKCTRL_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED }= ,//SW_GFX_DGPU_SEL (KBL_RVP3_BOARD)=0D +//{IO_EXPANDER_0, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB2_CAM_PWREN_IOEXP (SKL_RVP3_BOARD)=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_18, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //IMAGING_DFU_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_19, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //SW_GFX_PWERGD_IOEXP=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_20, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_WAKE_CTRL_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_21, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_SSD_RST_IOEXP_N=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TP_IOEXP1_P26=0D + {IO_EXPANDER_0, IO_EXPANDER_GPIO_23, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //TP_IOEXP1_P27=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_0, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_PWREN_IOEXP=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_1, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WWAN_DISABLE_IOEXP_N=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_2, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_WP4_PWREN_IOEXP=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_INPUT, IO_EXPANDE= R_GPO_LEVEL_LOW, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED }= ,//Not Connected (KBK_RVP3_BOARD)=0D +//{IO_EXPANDER_1, IO_EXPANDER_GPIO_3, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_OTG_WP1_PWREN_IOEXP (SKL_RVP3_BOARD)=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_4, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB32_WP2_WP3_WP5_PWREN_R_IOEXP=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_5, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //PCH_AUDIO_PWREN_IOEXP=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_6, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_GNSS_DISABLE_IOEXP_N=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_7, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //M.2_WIGIG_PWREN_IOEXP=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_17, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //USB2_CAM_PWREN (KBL_RVP3_BOARD)=0D + {IO_EXPANDER_1, IO_EXPANDER_GPIO_22, IO_EXPANDER_GPIO_OUTPUT, IO_EXPANDE= R_GPO_LEVEL_HIGH, IO_EXPANDER_GPI_INV_DISABLED, IO_EXPANDER_GPIO_RESERVED},= //FPS_LOCK_N (KBL_RVP3_BOARD)=0D +};=0D +=0D +UINT16 mGpioTableIoExpanderKabylakeRvp3Size =3D sizeof (mGpioTableIoExpand= erKabylakeRvp3) / sizeof (IO_EXPANDER_GPIO_CONFIG);=0D +=0D +#endif // _KABYLAKE_RVP3_GPIO_TABLE_H_=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/KabylakeRvp3HdaVerbTables.c b/Platform/Intel/KabylakeOpenBoard= Pkg/AspireVn7Dash572G/Library/BoardInitLib/KabylakeRvp3HdaVerbTables.c new file mode 100644 index 000000000000..92afcbab0653 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/KabylakeRvp3HdaVerbTables.c @@ -0,0 +1,232 @@ +/** @file=0D + HDA Verb table for KabylakeRvp3=0D +=0D +Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef _KABYLAKE_RVP3_HDA_VERB_TABLES_H_=0D +#define _KABYLAKE_RVP3_HDA_VERB_TABLES_H_=0D +=0D +#include =0D +=0D +HDAUDIO_VERB_TABLE HdaVerbTableAlc286Rvp3 =3D HDAUDIO_VERB_TABLE_INIT (=0D + //=0D + // VerbTable: (Realtek ALC286) for RVP3=0D + // Revision ID =3D 0xff=0D + // Codec Verb Table for SKL PCH boards=0D + // Codec Address: CAd value (0/1/2)=0D + // Codec Vendor: 0x10EC0286=0D + //=0D + 0x10EC, 0x0286,=0D + 0xFF, 0xFF,=0D + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=0D + //=0D + // Realtek Semiconductor Corp.=0D + //=0D + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=0D +=0D + //Realtek High Definition Audio Configuration - Version : 5.0.2.9=0D + //Realtek HD Audio Codec : ALC286=0D + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086=0D + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0286&SUBSYS_10EC108E=0D + //The number of verb command block : 16=0D +=0D + // NID 0x12 : 0x411111F0=0D + // NID 0x13 : 0x40000000=0D + // NID 0x14 : 0x9017011F=0D + // NID 0x17 : 0x90170110=0D + // NID 0x18 : 0x03A11040=0D + // NID 0x19 : 0x411111F0=0D + // NID 0x1A : 0x411111F0=0D + // NID 0x1D : 0x4066A22D=0D + // NID 0x1E : 0x411111F0=0D + // NID 0x21 : 0x03211020=0D +=0D +=0D + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D=0D + //HDA Codec Subsystem ID : 0x10EC108E=0D + 0x0017208E,=0D + 0x00172110,=0D + 0x001722EC,=0D + 0x00172310,=0D +=0D + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D=0D + //Widget node 0x01 :=0D + 0x0017FF00,=0D + 0x0017FF00,=0D + 0x0017FF00,=0D + 0x0017FF00,=0D + //Pin widget 0x12 - DMIC=0D + 0x01271CF0,=0D + 0x01271D11,=0D + 0x01271E11,=0D + 0x01271F41,=0D + //Pin widget 0x13 - DMIC=0D + 0x01371C00,=0D + 0x01371D00,=0D + 0x01371E00,=0D + 0x01371F40,=0D + //Pin widget 0x14 - SPEAKER-OUT (Port-D)=0D + 0x01771C1F,=0D + 0x01771D01,=0D + 0x01771E17,=0D + 0x01771F90,=0D + //Pin widget 0x17 - I2S-OUT=0D + 0x01771C10,=0D + 0x01771D01,=0D + 0x01771E17,=0D + 0x01771F90,=0D + //Pin widget 0x18 - MIC1 (Port-B)=0D + 0x01871C40,=0D + 0x01871D10,=0D + 0x01871EA1,=0D + 0x01871F03,=0D + //Pin widget 0x19 - I2S-IN=0D + 0x01971CF0,=0D + 0x01971D11,=0D + 0x01971E11,=0D + 0x01971F41,=0D + //Pin widget 0x1A - LINE1 (Port-C)=0D + 0x01A71CF0,=0D + 0x01A71D11,=0D + 0x01A71E11,=0D + 0x01A71F41,=0D + //Pin widget 0x1D - PC-BEEP=0D + 0x01D71C2D,=0D + 0x01D71DA2,=0D + 0x01D71E66,=0D + 0x01D71F40,=0D + //Pin widget 0x1E - S/PDIF-OUT=0D + 0x01E71CF0,=0D + 0x01E71D11,=0D + 0x01E71E11,=0D + 0x01E71F41,=0D + //Pin widget 0x21 - HP-OUT (Port-A)=0D + 0x02171C20,=0D + 0x02171D10,=0D + 0x02171E21,=0D + 0x02171F03,=0D + //Widget node 0x20 :=0D + 0x02050071,=0D + 0x02040014,=0D + 0x02050010,=0D + 0x02040C22,=0D + //Widget node 0x20 - 1 :=0D + 0x0205004F,=0D + 0x02045029,=0D + 0x0205004F,=0D + 0x02045029,=0D + //Widget node 0x20 - 2 :=0D + 0x0205002B,=0D + 0x02040DD0,=0D + 0x0205002D,=0D + 0x02047020,=0D + //Widget node 0x20 - 3 :=0D + 0x0205000E,=0D + 0x02046C80,=0D + 0x01771F90,=0D + 0x01771F90,=0D + //TI AMP settings :=0D + 0x02050022,=0D + 0x0204004C,=0D + 0x02050023,=0D + 0x02040000,=0D + 0x02050025,=0D + 0x02040000,=0D + 0x02050026,=0D + 0x0204B010,=0D +=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D +=0D + 0x02050022,=0D + 0x0204004C,=0D + 0x02050023,=0D + 0x02040002,=0D + 0x02050025,=0D + 0x02040011,=0D + 0x02050026,=0D + 0x0204B010,=0D +=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D +=0D + 0x02050022,=0D + 0x0204004C,=0D + 0x02050023,=0D + 0x0204000D,=0D + 0x02050025,=0D + 0x02040010,=0D + 0x02050026,=0D + 0x0204B010,=0D +=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D +=0D + 0x02050022,=0D + 0x0204004C,=0D + 0x02050023,=0D + 0x02040025,=0D + 0x02050025,=0D + 0x02040008,=0D + 0x02050026,=0D + 0x0204B010,=0D +=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D +=0D + 0x02050022,=0D + 0x0204004C,=0D + 0x02050023,=0D + 0x02040002,=0D + 0x02050025,=0D + 0x02040000,=0D + 0x02050026,=0D + 0x0204B010,=0D +=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D + 0x000F0000,=0D +=0D + 0x02050022,=0D + 0x0204004C,=0D + 0x02050023,=0D + 0x02040003,=0D + 0x02050025,=0D + 0x02040000,=0D + 0x02050026,=0D + 0x0204B010=0D +);=0D +=0D +#endif // _KABYLAKE_RVP3_HDA_VERB_TABLES_H_=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/KabylakeRvp3HsioPtssTables.c b/Platform/Intel/KabylakeOpenBoar= dPkg/AspireVn7Dash572G/Library/BoardInitLib/KabylakeRvp3HsioPtssTables.c new file mode 100644 index 000000000000..8a9048fa4c88 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/KabylakeRvp3HsioPtssTables.c @@ -0,0 +1,105 @@ +/** @file=0D + KabylakeRvp3 HSIO PTSS H File=0D +=0D +Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef KABYLAKE_RVP3_HSIO_PTSS_H_=0D +#define KABYLAKE_RVP3_HSIO_PTSS_H_=0D +=0D +#include =0D +=0D +#ifndef HSIO_PTSS_TABLE_SIZE=0D +#define HSIO_PTSS_TABLE_SIZE(A) A##_Size =3D sizeof (A) / sizeof (HSIO_PTS= S_TABLES)=0D +#endif=0D +=0D +//BoardId KabylakeRvp3=0D +HSIO_PTSS_TABLES PchLpHsioPtss_Cx_KabylakeRvp3[] =3D {=0D + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoM2},=0D + {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0= 000}, PchPcieTopoM2},=0D + {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D + {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4},=0D + {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32) ~0x3F0000= 00}, PchSataTopoDirectConnect},=0D + {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0= 000}, PchPcieTopoM2},=0D + {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D + {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4},=0D + {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D + {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4},=0D + {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D + {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D + {{12, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D + {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D + {{13, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D + {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D + {{14, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D + {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D + {{15, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D + {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4},=0D + {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopoM2},=0D + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopox1},=0D + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00322900, (UINT32) ~0x3F3F00}= , PchSataTopoM2},=0D + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00382C00, (UINT32) ~0x3F3F00}= , PchSataTopoDirectConnect},=0D + {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopoM2},=0D + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopox1},=0D + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D + {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D + {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D + {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown}=0D +};=0D +=0D +UINT16 PchLpHsioPtss_Cx_KabylakeRvp3_Size =3D sizeof(PchLpHsioPtss_Cx_Kaby= lakeRvp3) / sizeof(HSIO_PTSS_TABLES);=0D +=0D +HSIO_PTSS_TABLES PchLpHsioPtss_Bx_KabylakeRvp3[] =3D {=0D + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchPcieTopoUnknown},=0D + {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D + {{11, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D + {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4},=0D + {{4, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x04000000, (UINT32) ~0x3F0000= 00}, PchSataTopoDirectConnect},=0D + {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D + {{10, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D + {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4},=0D + {{5, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D + {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4},=0D + {{6, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D + {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D + {{12, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D + {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D + {{13, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D + {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D + {{14, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D + {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0x150, 0x03000000, (UINT32) ~0x3F0000= 00}, PchSataTopoUnknown},=0D + {{15, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F0= 000}, PchPcieTopoUnknown},=0D + {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopox4},=0D + {{7, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopox1},=0D + {{8, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D + {{11, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00322900, (UINT32) ~0x3F3F00}= , PchPcieTopoUnknown},=0D + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D + {{10, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00382C00, (UINT32) ~0x3F3F00}= , PchSataTopoDirectConnect},=0D + {{15, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00060000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopox1},=0D + {{9, V_PCH_PCR_FIA_LANE_OWN_PCIEDMI, 0x164, 0x00080000, (UINT32) ~0x1F00= 00}, PchPcieTopoUnknown},=0D + {{12, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D + {{13, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D + {{14, V_PCH_PCR_FIA_LANE_OWN_SATA, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}= , PchSataTopoUnknown},=0D +};=0D +=0D +UINT16 PchLpHsioPtss_Bx_KabylakeRvp3_Size =3D sizeof(PchLpHsioPtss_Bx_Kaby= lakeRvp3) / sizeof(HSIO_PTSS_TABLES);=0D +=0D +#endif // KABYLAKE_RVP3_HSIO_PTSS_H_=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/KabylakeRvp3SpdTable.c b/Platform/Intel/KabylakeOpenBoardPkg/A= spireVn7Dash572G/Library/BoardInitLib/KabylakeRvp3SpdTable.c new file mode 100644 index 000000000000..e4ad785bda20 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/KabylakeRvp3SpdTable.c @@ -0,0 +1,541 @@ +/** @file=0D + GPIO definition table for KabylakeRvp3=0D +=0D +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef _KABYLAKE_RVP3_SPD_TABLE_H_=0D +#define _KABYLAKE_RVP3_SPD_TABLE_H_=0D +=0D +//=0D +// DQByteMap[0] - ClkDQByteMap:=0D +// If clock is per rank, program to [0xFF, 0xFF]=0D +// If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]=0D +// If clock is shared by 2 ranks but does not go to all bytes,=0D +// Entry[i] defines which DQ bytes Group i services=0D +// DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is CmdN= /CAB=0D +// DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is CmdS= /CAB=0D +// DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is CKE = /CAB=0D +// For DDR, DQByteMap[3:1] =3D [0xFF, 0]=0D +// DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we have= 1 CTL / rank=0D +// Variable only exists to make the code eas= ier to use=0D +// DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we have= 1 CA Vref=0D +// Variable only exists to make the code eas= ier to use=0D +//=0D +//=0D +// DQ byte mapping to CMD/CTL/CLK, from the CPU side - for SKL RVP3, SKL S= DS - used by SKL/KBL MRC=0D +//=0D +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqByteMapSklRvp3[2][6][2] =3D {= =0D + // Channel 0:=0D + {=0D + { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to p= ackage 1 - Bytes[7:4]=0D + { 0x00, 0xF0 }, // CmdN does not have CAA, CAB goes to Bytes[7:4]=0D + { 0x0F, 0xF0 }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[= 7:4]=0D + { 0x0F, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB=0D + { 0xFF, 0x00 }, // CTL (CS) goes to all bytes=0D + { 0xFF, 0x00 } // CA Vref is one for all bytes=0D + },=0D + // Channel 1:=0D + {=0D + { 0x33, 0xCC }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to p= ackage 1 - Bytes[7:4]=0D + { 0x00, 0xCC }, // CmdN does not have CAA, CAB goes to Bytes[7:4]=0D + { 0x33, 0xCC }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[= 7:4]=0D + { 0x33, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB=0D + { 0xFF, 0x00 }, // CTL (CS) goes to all bytes=0D + { 0xFF, 0x00 } // CA Vref is one for all bytes=0D + }=0D +};=0D +=0D +//=0D +// DQS byte swizzling between CPU and DRAM - for SKL DOE RVP=0D +//=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqsMapCpu2DramSklRvp3[2][8] =3D= {=0D + { 0, 1, 3, 2, 4, 5, 6, 7 }, // Channel 0=0D + { 1, 0, 4, 5, 2, 3, 6, 7 } // Channel 1=0D +};=0D +=0D +// Samsung K4E6E304ED-EGCF 178b QDP LPDDR3, 4Gb die (256Mx16), x16=0D +// or Hynix H9CCNNNBLTALAR-NUD=0D +// or similar=0D +// 1867, 14-17-17-40=0D +// 2 ranks per channel, 2 SDRAMs per rank, 8x4Gb =3D 4GB total per channel= =0D +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp16Spd[] =3D {=0D + 0x24, ///< 0 Number of Serial PD Bytes= Written / SPD Device Size=0D + 0x20, ///< 1 SPD Revision=0D + 0x0F, ///< 2 DRAM Device Type=0D + 0x0E, ///< 3 Module Type=0D + 0x14, ///< 4 SDRAM Density and Banks: = 8 Banks, 4 Gb SDRAM density=0D + 0x12, ///< 5 SDRAM Addressing: 14 Rows= , 11 Columns=0D + 0xB5, ///< 6 SDRAM Package Type: QDP, = 1 Channel per die, Signal Loading Matrix 1=0D + 0x00, ///< 7 SDRAM Optional Features=0D + 0x00, ///< 8 SDRAM Thermal and Refresh= Options=0D + 0x00, ///< 9 Other SDRAM Optional Feat= ures=0D + 0x00, ///< 10 Reserved - must be coded = as 0x00=0D + 0x03, ///< 11 Module Nominal Voltage, V= DD=0D + 0x0A, ///< 12 Module Organization, SDRA= M width: 16 bits, 2 Ranks=0D + 0x23, ///< 13 Module Memory Bus Width: = 2 channels, 64 bit channel bus width=0D + 0x00, ///< 14 Module Thermal Sensor=0D + 0x00, ///< 15 Extended Module Type=0D + 0x00, ///< 16 Reserved - must be coded = as 0x00=0D + 0x00, ///< 17 Timebases=0D + 0x09, ///< 18 SDRAM Minimum Cycle Time = (tCKmin): tCKmin =3D 1.071ns (LPDDR3-1867)=0D + 0xFF, ///< 19 SDRAM Minimum Cycle Time = (tCKmax)=0D + 0xD4, ///< 20 CAS Latencies Supported, = First Byte (tCK): 14, 12, 10, 8=0D + 0x00, ///< 21 CAS Latencies Supported, = Second Byte=0D + 0x00, ///< 22 CAS Latencies Supported, = Third Byte=0D + 0x00, ///< 23 CAS Latencies Supported, = Fourth Byte=0D + 0x78, ///< 24 Minimum CAS Latency Time = (tAAmin) =3D 14.994 ns=0D + 0x00, ///< 25 Read and Write Latency Se= t Options=0D + 0x90, ///< 26 Minimum RAS# to CAS# Dela= y Time (tRCDmin)=0D + 0xA8, ///< 27 Minimum Row Precharge Del= ay Time for all banks (tRPab)=0D + 0x90, ///< 28 Minimum Row Precharge Del= ay Time per bank (tRPpb)=0D + 0x10, ///< 29 Minimum Refresh Recovery = Delay Time for all banks (tRFCab), Least Significant Byte=0D + 0x04, ///< 30 Minimum Refresh Recovery = Delay Time for all banks (tRFCab), Most Significant Byte=0D + 0xE0, ///< 31 Minimum Refresh Recovery = Delay Time for per bank (tRFCpb), Least Significant Byte=0D + 0x01, ///< 32 Minimum Refresh Recovery = Delay Time for per bank (tRFCpb), Most Significant Byte=0D + 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bi= t Mapping=0D + 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bi= t Mapping=0D + 0, 0, ///< 78 - 79=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119=0D + 0x00, ///< 120 Fine Offset for Minimum R= ow Precharge Delay Time per bank (tRPpb)=0D + 0x00, ///< 121 Fine Offset for Minimum R= ow Precharge Delay Time for all banks (tRPab)=0D + 0x00, ///< 122 Fine Offset for Minimum R= AS# to CAS# Delay Time (tRCDmin)=0D + 0xFA, ///< 123 Fine Offset for Minimum C= AS Latency Time (tAAmin): 14.994 ns (LPDDR3-1867)=0D + 0x7F, ///< 124 Fine Offset for SDRAM Min= imum Cycle Time (tCKmax): 32.002 ns=0D + 0xCA, ///< 125 Fine Offset for SDRAM Min= imum Cycle Time (tCKmin): 1.071 ns (LPDDR-1867)=0D + 0x00, ///< 126 CRC A=0D + 0x00, ///< 127 CRC B=0D + 0, 0, ///< 128 - 129=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319=0D + 0x00, ///< 320 Module Manufacturer ID Co= de, Least Significant Byte=0D + 0x00, ///< 321 Module Manufacturer ID Co= de, Most Significant Byte=0D + 0x00, ///< 322 Module Manufacturing Loca= tion=0D + 0x00, ///< 323 Module Manufacturing Date= Year=0D + 0x00, ///< 324 Module Manufacturing Date= Week=0D + 0x55, ///< 325 Module Serial Number A=0D + 0x00, ///< 326 Module Serial Number B=0D + 0x00, ///< 327 Module Serial Number C=0D + 0x00, ///< 328 Module Serial Number D=0D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number:= Unused bytes coded as ASCII Blanks (0x20)=0D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number= =0D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number= =0D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number= =0D + 0x00, ///< 349 Module Revision Code=0D + 0x00, ///< 350 DRAM Manufacturer ID Code= , Least Significant Byte=0D + 0x00, ///< 351 DRAM Manufacturer ID Code= , Most Significant Byte=0D + 0x00, ///< 352 DRAM Stepping=0D + 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509=0D + 0, 0 ///< 510 - 511=0D +};=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp16SpdSize =3D sizeof= (mSkylakeRvp16Spd);=0D +=0D +//Hynix H9CCNNNBJTMLAR-NUD, DDP, LPDDR3, 8Gb die=0D +//1867=0D +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp3Spd110[] =3D {=0D + 0x91, ///< 0 Number of Serial PD Byt= es Written / SPD Device Size / CRC Coverage 1, 2=0D + 0x20, ///< 1 SPD Revision=0D + 0xF1, ///< 2 DRAM Device Type=0D + 0x03, ///< 3 Module Type=0D + 0x05, ///< 4 SDRAM Density and Banks= , 8Gb=0D + 0x19, ///< 5 SDRAM Addressing: 15 Ro= ws, 10 Columns=0D + 0x05, ///< 6 Module Nominal Voltage= =0D + 0x0B, ///< 7 Module Organization: 32= bits, 2 Ranks=0D + 0x03, ///< 8 Module Memory Bus Width= =0D + 0x11, ///< 9 Fine Timebase (FTB) Div= idend / Divisor=0D + 0x01, ///< 10 Medium Timebase (MTB) D= ividend=0D + 0x08, ///< 11 Medium Timebase (MTB) D= ivisor=0D + 0x09, ///< 12 SDRAM Minimum Cycle Tim= e (tCKmin): tCKmin =3D 1.071 ns (LPDDR3-1867)=0D + 0x00, ///< 13 Reserved0=0D + 0x50, ///< 14 CAS Latencies supported= (tCK): 14, 12, 10, 8 (LSB)=0D + 0x05, ///< 15 CAS Latencies supported= (tCK): 14, 12, 10, 8 (LSB)=0D + 0x78, ///< 16 Minimum CAS Latency (tA= Amin) =3D 14.994 ns=0D + 0x78, ///< 17 Minimum Write Recovery = Time (tWRmin)=0D + 0x90, ///< 18 Minimum RAS# to CAS# De= lay Time (tRCDmin)=0D + 0x50, ///< 19 Minimum Row Active to R= ow Active Delay Time (tRRDmin)=0D + 0x90, ///< 20 Minimum Row Precharge D= elay Time (tRPmin)=0D + 0x11, ///< 21 Upper Nibbles for tRAS = and tRC=0D + 0x50, ///< 22 Minimum Active to Prech= arge Delay Time (tRASmin), Least Significant Byte=0D + 0xE0, ///< 23 Minimum Active to Activ= e/Refresh Delay Time (tRCmin), Least Significant Byte=0D + 0x90, ///< 24 Minimum Refresh Recover= y Delay Time (tRFCmin), Least Significant Byte=0D + 0x06, ///< 25 Minimum Refresh Recover= y Delay Time (tRFCmin), Most Significant Byte=0D + 0x3C, ///< 26 Minimum Internal Write = to Read Command Delay Time (tWTRmin)=0D + 0x3C, ///< 27 Minimum Internal Read t= o Precharge Command Delay Time (tRTPmin)=0D + 0x01, ///< 28 Upper Nibble for tFAW=0D + 0x90, ///< 29 Minimum Four Activate W= indow Delay Time (tFAWmin)=0D + 0x00, ///< 30 SDRAM Optional Features= =0D + 0x00, ///< 31 SDRAMThermalAndRefreshO= ptions=0D + 0x00, ///< 32 ModuleThermalSensor=0D + 0x00, ///< 33 SDRAM Device Type=0D + 0xCA, ///< 34 Fine Offset for SDRAM M= inimum Cycle Time (tCKmin): 1.071 ns (LPDDR3-1867)=0D + 0xFA, ///< 35 Fine Offset for Minimum= CAS Latency Time (tAAmin): 14.994 ns (LPDDR3-1867)=0D + 0x00, ///< 36 Fine Offset for Minimum= RAS# to CAS# Delay Time (tRCDmin)=0D + 0x00, ///< 37 Fine Offset for Minimum= Row Precharge Delay Time (tRPmin)=0D + 0x00, ///< 38 Fine Offset for Minimum= Active to Active/Refresh Delay Time (tRCmin)=0D + 0xA8, ///< 39 Row precharge time for = all banks (tRPab)=0D + 0x00, ///< 40 FTB for Row precharge t= ime for all banks (tRPab)=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 41 - 49=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59=0D + 0, 0, ///< 60 - 61=0D + 0x00, ///< 62 Reference Raw Card Used= =0D + 0x00, ///< 63 Address Mapping from Ed= ge Connector to DRAM=0D + 0x00, ///< 64 ThermalHeatSpreaderSolu= tion=0D + 0, 0, 0, 0, 0, ///< 65 - 69=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109=0D + 0, 0, 0, 0, 0, 0, 0, ///< 110 - 116=0D + 0x00, ///< 117 Module Manufacturer ID = Code, Least Significant Byte=0D + 0x00, ///< 118 Module Manufacturer ID = Code, Most Significant Byte=0D + 0x00, ///< 119 Module Manufacturing Lo= cation=0D + 0x00, ///< 120 Module Manufacturing Da= te Year=0D + 0x00, ///< 121 Module Manufacturing Da= te creation work week=0D + 0x55, ///< 122 Module Serial Number A= =0D + 0x00, ///< 123 Module Serial Number B= =0D + 0x00, ///< 124 Module Serial Number C= =0D + 0x00, ///< 125 Module Serial Number D= =0D + 0x00, ///< 126 CRC A=0D + 0x00 ///< 127 CRC B=0D +};=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp3Spd110Size =3D size= of (mSkylakeRvp3Spd110);=0D +=0D +//=0D +// Micron MT52L512M32D2PF 78b DDP LPDDR3, 8Gb die (256Mx32), x32=0D +//=0D +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mKblRSpdLpddr32133[] =3D {=0D + 0x91, ///< 0 128 SPD bytes used, 256= total, CRC covers 0..116=0D + 0x20, ///< 1 SPD Revision 2.0=0D + 0xF1, ///< 2 DRAM Type: LPDDR3 SDRAM= =0D + 0x03, ///< 3 Module Type: SO-DIMM=0D + 0x05, ///< 4 8 Banks, 8 Gb SDRAM den= sity=0D + 0x19, ///< 5 SDRAM Addressing: 15 Ro= ws, 10 Columns=0D + 0x05, ///< 6 Module Nominal Voltage = VDD: 1.2v=0D + 0x0B, ///< 7 SDRAM width: 32 bits, 2= Ranks=0D + 0x03, ///< 8 SDRAM bus width: 64 bit= s, no ECC=0D + 0x11, ///< 9 Fine Timebase (FTB) gra= nularity: 1 ps=0D + 0x01, ///< 10 Medium Timebase (MTB) := 0.125 ns=0D + 0x08, ///< 11 Medium Timebase Divisor= =0D + 0x08, ///< 12 tCKmin =3D 0.938 ns (LP= DDR3-2133)=0D + 0x00, ///< 13 Reserved=0D + 0x50, ///< 14 CAS Latencies supported= (tCK): 16, 14, 12, 10, 8 (LSB)=0D + 0x15, ///< 15 CAS Latencies supported= (tCK): 16, 14, 12, 10, 8 (MSB)=0D + 0x78, ///< 16 Minimum CAS Latency (tA= Amin) =3D 15.008 ns=0D + 0x78, ///< 17 tWR =3D 15 ns=0D + 0x90, ///< 18 Minimum RAS-to-CAS dela= y (tRCDmin) =3D 18 ns=0D + 0x50, ///< 19 tRRD =3D 10 ns=0D + 0x90, ///< 20 Minimum row precharge t= ime (tRPmin) =3D 18 ns=0D + 0x11, ///< 21 Upper nibbles for tRAS = and tRC=0D + 0x50, ///< 22 tRASmin =3D 42 ns=0D + 0xE0, ///< 23 tRCmin =3D (tRASmin + = tRPmin) =3D 60 ns=0D + 0x90, ///< 24 tRFCmin =3D (tRFCab) = =3D 210 ns (8Gb)=0D + 0x06, ///< 25 tRFCmin MSB=0D + 0x3C, ///< 26 tWTRmin =3D 7.5 ns=0D + 0x3C, ///< 27 tRTPmin =3D 7.5 ns=0D + 0x01, ///< 28 tFAWmin upper nibble=0D + 0x90, ///< 29 tFAWmin =3D 50 ns=0D + 0x00, ///< 30 SDRAM Optional Features= - none=0D + 0x00, ///< 31 SDRAM Thermal / Refresh= options - none=0D + 0x00, ///< 32 ModuleThermalSensor=0D + 0x00, ///< 33 SDRAM Device Type=0D + 0xC2, ///< 34 FTB for tCKmin =3D 0.93= 8 ns (LPDDR3-2133)=0D + 0x08, ///< 35 FTB for tAAmin =3D 15.0= 08 ns (LPDDR3-2133)=0D + 0x00, ///< 36 Fine Offset for Minimum= RAS# to CAS# Delay Time (tRCDmin)=0D + 0x00, ///< 37 Fine Offset for Minimum= Row Precharge Delay Time (tRPmin)=0D + 0x00, ///< 38 Fine Offset for Minimum= Active to Active/Refresh Delay Time (tRCmin)=0D + 0xA8, ///< 39 Row precharge time for = all banks (tRPab)=3D 21 ns=0D + 0x00, ///< 40 FTB for Row precharge t= ime for all banks (tRPab) =3D 0=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 41 - 49=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59=0D + 0, 0, ///< 60 - 61=0D + 0x00, ///< 62 Reference Raw Card Used= =0D + 0x00, ///< 63 Rank1 Mapping: Standard= =0D + 0x00, ///< 64 ThermalHeatSpreaderSolu= tion=0D + 0, 0, 0, 0, 0, ///< 65 - 69=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109=0D + 0, 0, 0, 0, 0, 0, 0, ///< 110 - 116=0D + 0x00, ///< 117 Module Manufacturer ID = Code, Least Significant Byte=0D + 0x00, ///< 118 Module Manufacturer ID = Code, Most Significant Byte=0D + 0x00, ///< 119 Module Manufacturing Lo= cation=0D + 0x00, ///< 120 Module Manufacturing Da= te Year=0D + 0x00, ///< 121 Module Manufacturing Da= te creation work week=0D + 0x55, ///< 122 Module ID: Module Seria= l Number=0D + 0x00, ///< 123 Module Serial Number B= =0D + 0x00, ///< 124 Module Serial Number C= =0D + 0x00, ///< 125 Module Serial Number D= =0D + 0x00, ///< 126 CRC A=0D + 0x00 ///< 127 CRC B=0D +};=0D +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mKblRSpdLpddr32133Size =3D size= of (mKblRSpdLpddr32133);=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSpdLpddr32133[] =3D {=0D + 0x24, ///< 0 Number of Serial PD Bytes= Written / SPD Device Size=0D + 0x01, ///< 1 SPD Revision=0D + 0x0F, ///< 2 DRAM Device Type=0D + 0x0E, ///< 3 Module Type=0D + 0x15, ///< 4 SDRAM Density and Banks: = 8 Banks, 8 Gb SDRAM density=0D + 0x19, ///< 5 SDRAM Addressing: 15 Rows= , 10 Columns=0D + 0x90, ///< 6 SDRAM Package Type: QDP, = 1 Channel per die, Signal Loading Matrix 1=0D + 0x00, ///< 7 SDRAM Optional Features=0D + 0x00, ///< 8 SDRAM Thermal and Refresh= Options=0D + 0x00, ///< 9 Other SDRAM Optional Feat= ures=0D + 0x00, ///< 10 Reserved - must be coded = as 0x00=0D + 0x0B, ///< 11 Module Nominal Voltage, V= DD=0D + 0x0B, ///< 12 Module Organization, SDRA= M width: 32 bits, 2 Ranks=0D + 0x03, ///< 13 Module Memory Bus Width: = 2 channels, 64 bit channel bus width=0D + 0x00, ///< 14 Module Thermal Sensor=0D + 0x00, ///< 15 Extended Module Type=0D + 0x00, ///< 16 Reserved - must be coded = as 0x00=0D + 0x00, ///< 17 Timebases=0D + 0x08, ///< 18 SDRAM Minimum Cycle Time = (tCKmin)=0D + 0xFF, ///< 19 SDRAM Minimum Cycle Time = (tCKmax)=0D + 0xD4, ///< 20 CAS Latencies Supported, = First Byte=0D + 0x01, ///< 21 CAS Latencies Supported, = Second Byte=0D + 0x00, ///< 22 CAS Latencies Supported, = Third Byte=0D + 0x00, ///< 23 CAS Latencies Supported, = Fourth Byte=0D + 0x78, ///< 24 Minimum CAS Latency Time = (tAAmin)=0D + 0x00, ///< 25 Read and Write Latency Se= t Options=0D + 0x90, ///< 26 Minimum RAS# to CAS# Dela= y Time (tRCDmin)=0D + 0xA8, ///< 27 Minimum Row Precharge Del= ay Time for all banks (tRPab)=0D + 0x90, ///< 28 Minimum Row Precharge Del= ay Time per bank (tRPpb)=0D + 0x90, ///< 29 Minimum Refresh Recovery = Delay Time for all banks (tRFCab), Least Significant Byte=0D + 0x06, ///< 30 Minimum Refresh Recovery = Delay Time for all banks (tRFCab), Most Significant Byte=0D + 0xD0, ///< 31 Minimum Refresh Recovery = Delay Time for per bank (tRFCpb), Least Significant Byte=0D + 0x02, ///< 32 Minimum Refresh Recovery = Delay Time for per bank (tRFCpb), Most Significant Byte=0D + 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bi= t Mapping=0D + 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bi= t Mapping=0D + 0, 0, ///< 78 - 79=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119=0D + 0x00, ///< 120 Fine Offset for Minimum R= ow Precharge Delay Time per bank (tRPpb)=0D + 0x00, ///< 121 Fine Offset for Minimum R= ow Precharge Delay Time for all banks (tRPab)=0D + 0x00, ///< 122 Fine Offset for Minimum R= AS# to CAS# Delay Time (tRCDmin)=0D + 0x08, ///< 123 Fine Offset for Minimum C= AS Latency Time (tAAmin)=0D + 0x7F, ///< 124 Fine Offset for SDRAM Min= imum Cycle Time (tCKmax)=0D + 0xC2, ///< 125 Fine Offset for SDRAM Min= imum Cycle Time (tCKmin)=0D + 0x00, ///< 126 CRC A=0D + 0x00, ///< 127 CRC B=0D + 0, 0, ///< 128 - 129=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319=0D + 0x00, ///< 320 Module Manufacturer ID Co= de, Least Significant Byte=0D + 0x00, ///< 321 Module Manufacturer ID Co= de, Most Significant Byte=0D + 0x00, ///< 322 Module Manufacturing Loca= tion=0D + 0x00, ///< 323 Module Manufacturing Date= Year=0D + 0x00, ///< 324 Module Manufacturing Date= Week=0D + 0x55, ///< 325 Module Serial Number A=0D + 0x00, ///< 326 Module Serial Number B=0D + 0x00, ///< 327 Module Serial Number C=0D + 0x00, ///< 328 Module Serial Number D=0D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number:= Unused bytes coded as ASCII Blanks (0x20)=0D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number= =0D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number= =0D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number= =0D + 0x00, ///< 349 Module Revision Code=0D + 0x00, ///< 350 DRAM Manufacturer ID Code= , Least Significant Byte=0D + 0x00, ///< 351 DRAM Manufacturer ID Code= , Most Significant Byte=0D + 0x00, ///< 352 DRAM Stepping=0D + 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509=0D + 0, 0 ///< 510 - 511=0D +};=0D +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSpdLpddr32133Size =3D sizeof (= mSpdLpddr32133);=0D +=0D +/**=0D + Hynix H9CCNNN8JTMLAR-NTM_178b_DDP LPDDR3, 4Gb die (128Mx32), x32=0D + or Elpida EDF8132A1MC-GD-F=0D + or Samsung K4E8E304EB-EGCE=0D + 1600, 12-15-15-34=0D + 2 rank per channel, 2 SDRAMs per rank, 4x4Gb =3D 2GB total per channel=0D +**/=0D +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp3Spd[] =3D {=0D + 0x24, ///< 0 Number of Serial PD Bytes= Written / SPD Device Size=0D + 0x20, ///< 1 SPD Revision=0D + 0x0F, ///< 2 DRAM Device Type=0D + 0x0E, ///< 3 Module Type=0D + 0x14, ///< 4 SDRAM Density and Banks: = 8 Banks, 4 Gb SDRAM density=0D + 0x11, ///< 5 SDRAM Addressing: 14 Rows= , 10 Columns=0D + 0x95, ///< 6 SDRAM Package Type: DDP, = 1 Channel per die, Signal Loading Matrix 1=0D + 0x00, ///< 7 SDRAM Optional Features=0D + 0x00, ///< 8 SDRAM Thermal and Refresh= Options=0D + 0x00, ///< 9 Other SDRAM Optional Feat= ures=0D + 0x00, ///< 10 Reserved - must be coded = as 0x00=0D + 0x03, ///< 11 Module Nominal Voltage, V= DD=0D + 0x0B, ///< 12 Module Organization, SDRA= M width: 32 bits, 2 Ranks=0D + 0x23, ///< 13 Module Memory Bus Width: = 2 channels, 64 bit channel bus width=0D + 0x00, ///< 14 Module Thermal Sensor=0D + 0x00, ///< 15 Extended Module Type=0D + 0x00, ///< 16 Reserved - must be coded = as 0x00=0D + 0x00, ///< 17 Timebases=0D + 0x0A, ///< 18 SDRAM Minimum Cycle Time = (tCKmin)=0D + 0xFF, ///< 19 SDRAM Minimum Cycle Time = (tCKmax)=0D + 0x54, ///< 20 CAS Latencies Supported, = First Byte (tCk): 12 10 8=0D + 0x00, ///< 21 CAS Latencies Supported, = Second Byte=0D + 0x00, ///< 22 CAS Latencies Supported, = Third Byte=0D + 0x00, ///< 23 CAS Latencies Supported, = Fourth Byte=0D + 0x78, ///< 24 Minimum CAS Latency Time = (tAAmin)=0D + 0x00, ///< 25 Read and Write Latency Se= t Options=0D + 0x90, ///< 26 Minimum RAS# to CAS# Dela= y Time (tRCDmin)=0D + 0xA8, ///< 27 Minimum Row Precharge Del= ay Time for all banks (tRPab)=0D + 0x90, ///< 28 Minimum Row Precharge Del= ay Time per bank (tRPpb)=0D + 0x10, ///< 29 Minimum Refresh Recovery = Delay Time for all banks (tRFCab), Least Significant Byte=0D + 0x04, ///< 30 Minimum Refresh Recovery = Delay Time for all banks (tRFCab), Most Significant Byte=0D + 0xE0, ///< 31 Minimum Refresh Recovery = Delay Time for per bank (tRFCpb), Least Significant Byte=0D + 0x01, ///< 32 Minimum Refresh Recovery = Delay Time for per bank (tRFCpb), Most Significant Byte=0D + 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bi= t Mapping=0D + 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bi= t Mapping=0D + 0, 0, ///< 78 - 79=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119=0D + 0x00, ///< 120 Fine Offset for Minimum R= ow Precharge Delay Time per bank (tRPpb)=0D + 0x00, ///< 121 Fine Offset for Minimum R= ow Precharge Delay Time for all banks (tRPab)=0D + 0x00, ///< 122 Fine Offset for Minimum R= AS# to CAS# Delay Time (tRCDmin)=0D + 0x00, ///< 123 Fine Offset for Minimum C= AS Latency Time (tAAmin)=0D + 0x7F, ///< 124 Fine Offset for SDRAM Min= imum Cycle Time (tCKmax)=0D + 0x00, ///< 125 Fine Offset for SDRAM Min= imum Cycle Time (tCKmin)=0D + 0x00, ///< 126 CRC A=0D + 0x00, ///< 127 CRC B=0D + 0, 0, ///< 128 - 129=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319=0D + 0x00, ///< 320 Module Manufacturer ID Co= de, Least Significant Byte=0D + 0x00, ///< 321 Module Manufacturer ID Co= de, Most Significant Byte=0D + 0x00, ///< 322 Module Manufacturing Loca= tion=0D + 0x00, ///< 323 Module Manufacturing Date= Year=0D + 0x00, ///< 324 Module Manufacturing Date= Week=0D + 0x55, ///< 325 Module Serial Number A=0D + 0x00, ///< 326 Module Serial Number B=0D + 0x00, ///< 327 Module Serial Number C=0D + 0x00, ///< 328 Module Serial Number D=0D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number:= Unused bytes coded as ASCII Blanks (0x20)=0D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number= =0D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number= =0D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number= =0D + 0x00, ///< 349 Module Revision Code=0D + 0x00, ///< 350 DRAM Manufacturer ID Code= , Least Significant Byte=0D + 0x00, ///< 351 DRAM Manufacturer ID Code= , Most Significant Byte=0D + 0x00, ///< 352 DRAM Stepping=0D + 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499=0D + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509=0D + 0, 0 ///< 510 - 511=0D +};=0D +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mSkylakeRvp3SpdSize =3D sizeof = (mSkylakeRvp3Spd);=0D +#endif // _KABYLAKE_RVP3_SPD_TABLE_H_=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiBoardInitPostMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg= /AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.c new file mode 100644 index 000000000000..2e079a0387a5 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiBoardInitPostMemLib.c @@ -0,0 +1,39 @@ +/** @file=0D + Kaby Lake RVP 3 Board Initialization Post-Memory library=0D +=0D +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3BoardInitBeforeSiliconInit (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +BoardInitBeforeSiliconInit (=0D + VOID=0D + )=0D +{=0D + KabylakeRvp3BoardInitBeforeSiliconInit ();=0D + return EFI_SUCCESS;=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +BoardInitAfterSiliconInit (=0D + VOID=0D + )=0D +{=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/KabylakeOpenBoardP= kg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.inf new file mode 100644 index 000000000000..bdf481b9805c --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiBoardInitPostMemLib.inf @@ -0,0 +1,54 @@ +## @file=0D +# Component information file for KabylakeRvp3InitLib in PEI post memory ph= ase.=0D +#=0D +# Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D PeiBoardPostMemInitLib=0D + FILE_GUID =3D 7fcc3900-d38d-419f-826b-72481e8b5509= =0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D BoardInitLib=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + DebugLib=0D + BaseMemoryLib=0D + MemoryAllocationLib=0D + GpioExpanderLib=0D + PcdLib=0D + SiliconInitLib=0D +=0D +[Packages]=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + KabylakeOpenBoardPkg/OpenBoardPkg.dec=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + KabylakeSiliconPkg/SiPkg.dec=0D + IntelSiliconPkg/IntelSiliconPkg.dec=0D +=0D +[Sources]=0D + PeiKabylakeRvp3InitPostMemLib.c=0D + KabylakeRvp3GpioTable.c=0D + KabylakeRvp3HdaVerbTables.c=0D + PeiBoardInitPostMemLib.c=0D +=0D +[FixedPcd]=0D +=0D +[Pcd]=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel=0D +=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize=0D +=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable=0D +=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiBoardInitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/= AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.c new file mode 100644 index 000000000000..f5c695ecff86 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiBoardInitPreMemLib.c @@ -0,0 +1,108 @@ +/** @file=0D + Kaby Lake RVP 3 Board Initialization Pre-Memory library=0D +=0D +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3BoardDetect (=0D + VOID=0D + );=0D +=0D +EFI_BOOT_MODE=0D +EFIAPI=0D +KabylakeRvp3BoardBootModeDetect (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3BoardDebugInit (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3BoardInitBeforeMemoryInit (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +BoardDetect (=0D + VOID=0D + )=0D +{=0D + KabylakeRvp3BoardDetect ();=0D + return EFI_SUCCESS;=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +BoardDebugInit (=0D + VOID=0D + )=0D +{=0D + KabylakeRvp3BoardDebugInit ();=0D + return EFI_SUCCESS;=0D +}=0D +=0D +EFI_BOOT_MODE=0D +EFIAPI=0D +BoardBootModeDetect (=0D + VOID=0D + )=0D +{=0D + return KabylakeRvp3BoardBootModeDetect ();=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +BoardInitBeforeMemoryInit (=0D + VOID=0D + )=0D +{=0D + if ((LibPcdGetSku () =3D=3D BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetSku= () =3D=3D BoardIdSkylakeRvp3)) {=0D + KabylakeRvp3BoardInitBeforeMemoryInit ();=0D + }=0D + return EFI_SUCCESS;=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +BoardInitAfterMemoryInit (=0D + VOID=0D + )=0D +{=0D + return EFI_SUCCESS;=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +BoardInitBeforeTempRamExit (=0D + VOID=0D + )=0D +{=0D + return EFI_SUCCESS;=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +BoardInitAfterTempRamExit (=0D + VOID=0D + )=0D +{=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPk= g/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf new file mode 100644 index 000000000000..850fc514188b --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiBoardInitPreMemLib.inf @@ -0,0 +1,135 @@ +## @file=0D +# Component information file for PEI KabylakeRvp3 Board Init Pre-Mem Libra= ry=0D +#=0D +# Copyright (c) 2017 - 2021 Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D PeiBoardInitPreMemLib=0D + FILE_GUID =3D ec3675bc-1470-417d-826e-37378140213d= =0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D BoardInitLib=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + DebugLib=0D + BaseMemoryLib=0D + MemoryAllocationLib=0D + PcdLib=0D + SiliconInitLib=0D + EcLib=0D + PchResetLib=0D +=0D +[Packages]=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + KabylakeOpenBoardPkg/OpenBoardPkg.dec=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + KabylakeSiliconPkg/SiPkg.dec=0D + IntelSiliconPkg/IntelSiliconPkg.dec=0D +=0D +[Sources]=0D + PeiKabylakeRvp3Detect.c=0D + PeiKabylakeRvp3InitPreMemLib.c=0D + KabylakeRvp3HsioPtssTables.c=0D + KabylakeRvp3SpdTable.c=0D + PeiBoardInitPreMemLib.c=0D +=0D +[Pcd]=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort=0D +=0D + # PCH-LP HSIO PTSS Table=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size=0D +=0D + # PCH-H HSIO PTSS Table=0D + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1=0D + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2=0D + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size=0D + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size=0D +=0D + # SA Misc Config=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize=0D +=0D + # PEG Reset By GPIO=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive=0D +=0D +=0D + # SPD Address Table=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3=0D +=0D + # CA Vref Configuration=0D +=0D + # Root Port Clock Info=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort0ClkInfo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort4ClkInfo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort5ClkInfo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort7ClkInfo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort8ClkInfo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort9ClkInfo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortLanClkInfo=0D +=0D + # USB 2.0 Port AFE=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe=0D +=0D + # USB 2.0 Port Over Current Pin=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13=0D +=0D + # USB 3.0 Port Over Current Pin=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5=0D +=0D + # Misc=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent=0D +=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiKabylakeRvp3Detect.c b/Platform/Intel/KabylakeOpenBoardPkg/= AspireVn7Dash572G/Library/BoardInitLib/PeiKabylakeRvp3Detect.c new file mode 100644 index 000000000000..429f4316dd64 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiKabylakeRvp3Detect.c @@ -0,0 +1,124 @@ +/** @file=0D +=0D +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include "PeiKabylakeRvp3InitLib.h"=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#define BOARD_ID_MASK_8BIT 0xff=0D +=0D +/**=0D + Get board fab ID.=0D +=0D + @param[out] DataBuffer=0D +=0D + @retval EFI_SUCCESS Command success=0D + @retval EFI_DEVICE_ERROR Command error=0D +**/=0D +EFI_STATUS=0D +GetBoardFabId (=0D + OUT UINT8 *DataBuffer=0D + )=0D +{=0D + UINT8 DataSize;=0D +=0D + //=0D + // For 'EC_C_FAB_ID' command NumberOfSendData =3D 0, NumberOfReceiveData= =3D2.=0D + //=0D + DataSize =3D 2;=0D + return (LpcEcInterface (EC_C_FAB_ID, &DataSize, DataBuffer));=0D +}=0D +=0D +/**=0D + Get RVP3 board ID.=0D + There are 2 different RVP3 boards having different ID.=0D + This function will return board ID to caller.=0D +=0D + @param[out] DataBuffer=0D +=0D + @retval EFI_SUCCESS Command success=0D + @retval EFI_DEVICE_ERROR Command error=0D +**/=0D +EFI_STATUS=0D +GetRvp3BoardId (=0D + UINT8 *BoardId=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINT16 EcBoardInfo;=0D + UINT8 DataBuffer[2];=0D +=0D + Status =3D GetBoardFabId (DataBuffer);=0D + if (Status =3D=3D EFI_SUCCESS) {=0D + EcBoardInfo =3D DataBuffer[0];=0D + EcBoardInfo =3D (EcBoardInfo << 8) | DataBuffer[1];=0D + //=0D + // Get the following data:=0D + // [7:0] - BOARD_IDx=0D + // [8] - GEN_ID=0D + // [11:9] - REV_FAB_IDx=0D + // [12] - TP_SPD_PRSNT=0D + // [15:13] - BOM_IDx=0D + //=0D + *BoardId =3D (UINT8) (EcBoardInfo & BOARD_ID_MASK_8BIT);=0D + DEBUG ((DEBUG_INFO, "BoardId =3D %X\n", *BoardId));=0D + }=0D + return Status;=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3BoardDetect (=0D + VOID=0D + )=0D +{=0D + UINT8 BoardId;=0D +=0D + if (LibPcdGetSku () !=3D 0) {=0D + return EFI_SUCCESS;=0D + }=0D +=0D + DEBUG ((DEBUG_INFO, "KabylakeRvp3DetectionCallback\n"));=0D + if (GetRvp3BoardId (&BoardId) =3D=3D EFI_SUCCESS) {=0D + if (BoardId =3D=3D BoardIdKabyLakeYLpddr3Rvp3) {=0D + LibPcdSetSku (BoardIdKabyLakeYLpddr3Rvp3);=0D + ASSERT (LibPcdGetSku() =3D=3D BoardIdKabyLakeYLpddr3Rvp3);=0D + } else if (BoardId =3D=3D BoardIdSkylakeRvp3) {=0D + LibPcdSetSku (BoardIdSkylakeRvp3);=0D + ASSERT (LibPcdGetSku() =3D=3D BoardIdSkylakeRvp3);=0D + }=0D + DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));=0D + }=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiKabylakeRvp3InitLib.h b/Platform/Intel/KabylakeOpenBoardPkg= /AspireVn7Dash572G/Library/BoardInitLib/PeiKabylakeRvp3InitLib.h new file mode 100644 index 000000000000..5b2ccf6b0dea --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiKabylakeRvp3InitLib.h @@ -0,0 +1,44 @@ +/** @file=0D +=0D +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef _PEI_KABYLAKE_RVP3_BOARD_INIT_LIB_H_=0D +#define _PEI_KABYLAKE_RVP3_BOARD_INIT_LIB_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +=0D +extern const UINT8 mDqByteMapSklRvp3[2][6][2];=0D +extern const UINT8 mDqsMapCpu2DramSklRvp3[2][8];=0D +extern const UINT8 mSkylakeRvp3Spd110[];=0D +extern const UINT16 mSkylakeRvp3Spd110Size;=0D +extern const UINT8 mSkylakeRvp3Spd[];=0D +extern const UINT16 mSkylakeRvp3SpdSize;=0D +extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_KabylakeRvp3[];=0D +extern UINT16 PchLpHsioPtss_Bx_KabylakeRvp3_Size;=0D +extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_KabylakeRvp3[];=0D +extern UINT16 PchLpHsioPtss_Cx_KabylakeRvp3_Size;=0D +=0D +extern HDAUDIO_VERB_TABLE HdaVerbTableAlc286Rvp3;=0D +extern GPIO_INIT_CONFIG mGpioTableLpddr3Rvp3UcmcDevice[];=0D +extern UINT16 mGpioTableLpddr3Rvp3UcmcDeviceSize;=0D +=0D +extern IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[];=0D +extern UINT16 mGpioTableIoExpanderSize;=0D +extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3Touchpanel;=0D +extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[];=0D +extern UINT16 mGpioTableLpDdr3Rvp3Size;=0D +=0D +#endif // _PEI_KABYLAKE_RVP3_BOARD_INIT_LIB_H_=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiKabylakeRvp3InitPostMemLib.c b/Platform/Intel/KabylakeOpenB= oardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiKabylakeRvp3InitPostMemLi= b.c new file mode 100644 index 000000000000..5d398ab6654e --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiKabylakeRvp3InitPostMemLib.c @@ -0,0 +1,208 @@ +/** @file=0D +=0D +Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include "PeiKabylakeRvp3InitLib.h"=0D +=0D +/**=0D + SkylaeA0Rvp3 board configuration init function for PEI post memory phase= .=0D +=0D + PEI_BOARD_CONFIG_PCD_INIT=0D +=0D + @param Content pointer to the buffer contain init information for boar= d init.=0D +=0D + @retval EFI_SUCCESS The function completed successfully.=0D + @retval EFI_INVALID_PARAMETER The parameter is NULL.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3Init (=0D + VOID=0D + )=0D +{=0D + PcdSet32S (PcdHdaVerbTable, (UINTN) &HdaVerbTableAlc286Rvp3);=0D +=0D + //=0D + // Assign the GPIO table with pin configs to be used for UCMC=0D + //=0D + PcdSet32S (PcdBoardUcmcGpioTable, (UINTN)mGpioTableLpddr3Rvp3UcmcDevice)= ;=0D + PcdSet16S (PcdBoardUcmcGpioTableSize, mGpioTableLpddr3Rvp3UcmcDeviceSize= );=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +#define EXPANDERS 2 // = defines expander's quantity=0D +=0D +/**=0D + Configures GPIO=0D +=0D + @param[in] GpioTable Point to Platform Gpio table=0D + @param[in] GpioTableCount Number of Gpio table entries=0D +=0D +**/=0D +VOID=0D +ConfigureGpio (=0D + IN GPIO_INIT_CONFIG *GpioDefinition,=0D + IN UINT16 GpioTableCount=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));=0D +=0D + Status =3D GpioConfigurePads (GpioTableCount, GpioDefinition);=0D +=0D + DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));=0D +}=0D +=0D +VOID=0D +SetBit (=0D + IN OUT UINT32 *Value,=0D + IN UINT32 BitNumber,=0D + IN BOOLEAN NewBitValue=0D + )=0D +{=0D + if (NewBitValue) {=0D + *Value |=3D 1 << BitNumber;=0D + } else {=0D + *Value &=3D ~(1 << BitNumber);=0D + }=0D +}=0D +=0D +/**=0D + Configures IO Expander GPIO device=0D +=0D + @param[in] IOExpGpioDefinition Point to IO Expander Gpio table=0D + @param[in] IOExpGpioTableCount Number of Gpio table entries=0D +=0D +**/=0D +void=0D +ConfigureIoExpanderGpio (=0D + IN IO_EXPANDER_GPIO_CONFIG *IoExpGpioDefinition,=0D + IN UINT16 IoExpGpioTableCount=0D + )=0D +{=0D + UINT8 Index;=0D + UINT32 Direction[EXPANDERS] =3D {0x00FFFFFF, 0x00FFFFFF};=0D + UINT32 Level[EXPANDERS] =3D {0};=0D + UINT32 Polarity[EXPANDERS] =3D {0};=0D +=0D + // IoExpander {TCA6424A}=0D + DEBUG ((DEBUG_INFO, "IO Expander Configuration Start\n"));=0D + for (Index =3D 0; Index < IoExpGpioTableCount; Index++) { //Program IO= Expander as per the table defined in PeiPlatformHooklib.c=0D + SetBit(&Direction[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpG= pioDefinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].Gpi= oDirection);=0D + SetBit(&Level[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpGpioD= efinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].GpioLev= el);=0D + SetBit(&Polarity[IoExpGpioDefinition[Index].IoExpanderNumber], IoExpGp= ioDefinition[Index].GpioPinNumber, (BOOLEAN)IoExpGpioDefinition[Index].Gpio= Inversion);=0D + }=0D + for (Index =3D 0; Index < EXPANDERS; Index++) {=0D + GpioExpBulkConfig(Index, Direction[Index], Polarity[Index], Level[Inde= x]);=0D + }=0D + DEBUG ((DEBUG_INFO, "IO Expander Configuration End\n"));=0D + return;=0D +}=0D +=0D +/**=0D + Configure GPIO behind IoExpander.=0D +=0D + @param[in] PeiServices General purpose services available to ever= y PEIM.=0D + @param[in] NotifyDescriptor=0D + @param[in] Interface=0D +=0D + @retval EFI_SUCCESS Operation success.=0D +**/=0D +VOID=0D +ExpanderGpioInit (=0D + VOID=0D + )=0D +{=0D + ConfigureIoExpanderGpio(mGpioTableIoExpander, mGpioTableIoExpanderSize);= =0D +}=0D +=0D +/**=0D + Configure single GPIO pad for touchpanel interrupt=0D +=0D +**/=0D +VOID=0D +TouchpanelGpioInit (=0D + VOID=0D + )=0D +{=0D + GPIO_INIT_CONFIG* TouchpanelPad;=0D + GPIO_PAD_OWN PadOwnVal;=0D +=0D + PadOwnVal =3D 0;=0D + TouchpanelPad =3D &mGpioTableLpDdr3Rvp3Touchpanel;=0D +=0D + GpioGetPadOwnership (TouchpanelPad->GpioPad, &PadOwnVal);=0D + if (PadOwnVal =3D=3D GpioPadOwnHost) {=0D + GpioConfigurePads (1, TouchpanelPad);=0D + }=0D +}=0D +=0D +=0D +/**=0D + Configure GPIO=0D +=0D +**/=0D +VOID=0D +GpioInit (=0D + VOID=0D + )=0D +{=0D + ConfigureGpio (mGpioTableLpDdr3Rvp3, mGpioTableLpDdr3Rvp3Size);=0D +=0D + TouchpanelGpioInit();=0D +=0D + return;=0D +}=0D +=0D +=0D +/**=0D + Configure GPIO and SIO=0D +=0D + @retval EFI_SUCCESS Operation success.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3BoardInitBeforeSiliconInit (=0D + VOID=0D + )=0D +{=0D + KabylakeRvp3Init ();=0D +=0D + GpioInit ();=0D + ExpanderGpioInit ();=0D + =0D + ///=0D + /// Do Late PCH init=0D + ///=0D + LateSiliconInit ();=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c b/Platform/Intel/KabylakeOpenBo= ardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c new file mode 100644 index 000000000000..d34b0be3c7f6 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiKabylakeRvp3InitPreMemLib.c @@ -0,0 +1,339 @@ +/** @file=0D +=0D +Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include "PeiKabylakeRvp3InitLib.h"=0D +=0D +#include =0D +#include =0D +=0D +//=0D +// Reference RCOMP resistors on motherboard - for SKL RVP1=0D +//=0D +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp1[SA_MRC_MAX= _RCOMP] =3D { 200, 81, 162 };=0D +//=0D +// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for SK= L RVP1=0D +//=0D +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp1[SA_MRC_MAX_R= COMP_TARGETS] =3D { 100, 40, 40, 23, 40 };=0D +=0D +/**=0D + SkylaeA0Rvp3 board configuration init function for PEI pre-memory phase.= =0D +=0D + PEI_BOARD_CONFIG_PCD_INIT=0D +=0D + @param Content pointer to the buffer contain init information for boar= d init.=0D +=0D + @retval EFI_SUCCESS The function completed successfully.=0D + @retval EFI_INVALID_PARAMETER The parameter is NULL.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3InitPreMem (=0D + VOID=0D + )=0D +{=0D + PcdSet32S (PcdPcie0WakeGpioNo, 0);=0D + PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);=0D + PcdSet32S (PcdPcie0HoldRstGpioNo, 8);=0D + PcdSetBoolS (PcdPcie0HoldRstActive, TRUE);=0D + PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);=0D + PcdSet32S (PcdPcie0PwrEnableGpioNo, 16);=0D + PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);=0D +=0D + //=0D + // HSIO PTSS Table=0D + //=0D + PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_Bx_Kab= ylakeRvp3);=0D + PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_Bx_Kab= ylakeRvp3_Size);=0D + PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_Cx_Kab= ylakeRvp3);=0D + PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_Cx_Kab= ylakeRvp3_Size);=0D +=0D + //=0D + // DRAM related definition=0D + //=0D + PcdSet8S (PcdSaMiscUserBd, 5);=0D +=0D + PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapSklRvp3);=0D + PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapSklRvp3));=0D + PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramSklRvp3);=0D + PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramSklRvp3));=0D + PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorSklRvp1);=0D + PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetSklRvp1);=0D + //=0D + // Example policy for DIMM slots implementation boards:=0D + // 1. Assign Smbus address of DIMMs and SpdData will be updated later=0D + // by reading from DIMM SPD.=0D + // 2. No need to apply hardcoded SpdData buffers here for such board.=0D + // Example:=0D + // PcdMrcSpdAddressTable0 =3D 0xA0=0D + // PcdMrcSpdAddressTable1 =3D 0xA2=0D + // PcdMrcSpdAddressTable2 =3D 0xA4=0D + // PcdMrcSpdAddressTable3 =3D 0xA6=0D + // PcdMrcSpdData =3D 0=0D + // PcdMrcSpdDataSize =3D 0=0D + //=0D + // Kabylake RVP3 has 8GB Memory down implementation withouit SPD,=0D + // So assign all SpdAddress to 0 and apply static SpdData buffers:=0D + // PcdMrcSpdAddressTable0 =3D 0=0D + // PcdMrcSpdAddressTable1 =3D 0=0D + // PcdMrcSpdAddressTable2 =3D 0=0D + // PcdMrcSpdAddressTable3 =3D 0=0D + // PcdMrcSpdData =3D static data buffer=0D + // PcdMrcSpdDataSize =3D sizeof (static data buffer)=0D + //=0D + PcdSet8S (PcdMrcSpdAddressTable0, 0);=0D + PcdSet8S (PcdMrcSpdAddressTable1, 0);=0D + PcdSet8S (PcdMrcSpdAddressTable2, 0);=0D + PcdSet8S (PcdMrcSpdAddressTable3, 0);=0D + PcdSet32S (PcdMrcSpdData, (UINTN) mSkylakeRvp3Spd110);=0D + PcdSet16S (PcdMrcSpdDataSize, mSkylakeRvp3Spd110Size);=0D +=0D + PcdSetBoolS (PcdIoExpanderPresent, TRUE);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + SkylaeA0Rvp3 board configuration init function for PEI pre-memory phase.= =0D +=0D + PEI_BOARD_CONFIG_PCD_INIT=0D +=0D + @param Content pointer to the buffer contain init information for boar= d init.=0D +=0D + @retval EFI_SUCCESS The function completed successfully.=0D + @retval EFI_INVALID_PARAMETER The parameter is NULL.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SkylakeRvp3InitPreMem (=0D + VOID=0D + )=0D +{=0D + PcdSet32S (PcdPcie0WakeGpioNo, 0);=0D + PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);=0D + PcdSet32S (PcdPcie0HoldRstGpioNo, 8);=0D + PcdSetBoolS (PcdPcie0HoldRstActive, TRUE);=0D + PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);=0D + PcdSet32S (PcdPcie0PwrEnableGpioNo, 16);=0D + PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);=0D +=0D + //=0D + // HSIO PTSS Table=0D + //=0D + PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_Bx_Kab= ylakeRvp3);=0D + PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_Bx_Kab= ylakeRvp3_Size);=0D + PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_Cx_Kab= ylakeRvp3);=0D + PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_Cx_Kab= ylakeRvp3_Size);=0D +=0D + //=0D + // DRAM related definition=0D + //=0D + PcdSet8S (PcdSaMiscUserBd, 5);=0D +=0D + PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapSklRvp3);=0D + PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapSklRvp3));=0D + PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramSklRvp3);=0D + PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramSklRvp3));=0D + PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorSklRvp1);=0D + PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetSklRvp1);=0D + //=0D + // Example policy for DIMM slots implementation boards:=0D + // 1. Assign Smbus address of DIMMs and SpdData will be updated later=0D + // by reading from DIMM SPD.=0D + // 2. No need to apply hardcoded SpdData buffers here for such board.=0D + // Example:=0D + // PcdMrcSpdAddressTable0 =3D 0xA0=0D + // PcdMrcSpdAddressTable1 =3D 0xA2=0D + // PcdMrcSpdAddressTable2 =3D 0xA4=0D + // PcdMrcSpdAddressTable3 =3D 0xA6=0D + // PcdMrcSpdData =3D 0=0D + // PcdMrcSpdDataSize =3D 0=0D + //=0D + // Skylake RVP3 has 4GB Memory down implementation withouit SPD,=0D + // So assign all SpdAddress to 0 and apply static SpdData buffers:=0D + // PcdMrcSpdAddressTable0 =3D 0=0D + // PcdMrcSpdAddressTable1 =3D 0=0D + // PcdMrcSpdAddressTable2 =3D 0=0D + // PcdMrcSpdAddressTable3 =3D 0=0D + // PcdMrcSpdData =3D static data buffer=0D + // PcdMrcSpdDataSize =3D sizeof (static data buffer)=0D + //=0D + PcdSet8S (PcdMrcSpdAddressTable0, 0);=0D + PcdSet8S (PcdMrcSpdAddressTable1, 0);=0D + PcdSet8S (PcdMrcSpdAddressTable2, 0);=0D + PcdSet8S (PcdMrcSpdAddressTable3, 0);=0D + PcdSet32S (PcdMrcSpdData, (UINTN) mSkylakeRvp3Spd);=0D + PcdSet16S (PcdMrcSpdDataSize, mSkylakeRvp3SpdSize);=0D +=0D + PcdSetBoolS (PcdIoExpanderPresent, TRUE);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +#define SIO_RUNTIME_REG_BASE_ADDRESS 0x0680=0D +=0D +/**=0D + Configures GPIO.=0D +=0D + @param[in] GpioTable Point to Platform Gpio table=0D + @param[in] GpioTableCount Number of Gpio table entries=0D +=0D +**/=0D +VOID=0D +ConfigureGpio (=0D + IN GPIO_INIT_CONFIG *GpioDefinition,=0D + IN UINT16 GpioTableCount=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));=0D +=0D + Status =3D GpioConfigurePads (GpioTableCount, GpioDefinition);=0D +=0D + DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));=0D +}=0D +=0D +/**=0D + Configure GPIO Before Memory is not ready.=0D +=0D +**/=0D +VOID=0D +GpioInitPreMem (=0D + VOID=0D + )=0D +{=0D + // ConfigureGpio ();=0D +}=0D +=0D +/**=0D + Configure Super IO.=0D +=0D +**/=0D +VOID=0D +SioInit (=0D + VOID=0D + )=0D +{=0D + //=0D + // Program and Enable Default Super IO Configuration Port Addresses and = range=0D + //=0D + PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x1= 0);=0D +=0D + //=0D + // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF;=0D + //=0D + PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F), 0x10);=0D +=0D + return;=0D +}=0D +=0D +/**=0D + Configues the IC2 Controller on which GPIO Expander Communicates.=0D + This Function is to enable the I2CGPIOExapanderLib to programm the Gpios= =0D + Complete intilization will be done in later Stage=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +I2CGpioExpanderInitPreMem(=0D + VOID=0D + )=0D +{=0D + ConfigureSerialIoController (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden= );=0D + SerialIoI2cGpioInit (PchSerialIoIndexI2C4, PchSerialIoAcpiHidden, PchSer= ialIoIs33V);=0D +}=0D +=0D +/**=0D + Configure GPIO and SIO before memory ready.=0D +=0D + @retval EFI_SUCCESS Operation success.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3BoardInitBeforeMemoryInit (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + if (LibPcdGetSku () =3D=3D BoardIdKabyLakeYLpddr3Rvp3) {=0D + KabylakeRvp3InitPreMem ();=0D + } else if (LibPcdGetSku () =3D=3D BoardIdSkylakeRvp3) {=0D + SkylakeRvp3InitPreMem ();=0D + }=0D +=0D + //=0D + // Configures the I2CGpioExpander=0D + //=0D + if (PcdGetBool (PcdIoExpanderPresent)) {=0D + I2CGpioExpanderInitPreMem();=0D + }=0D +=0D + GpioInitPreMem ();=0D + SioInit ();=0D +=0D + ///=0D + /// Do basic PCH init=0D + ///=0D + SiliconInit ();=0D +=0D + //=0D + // Install PCH RESET PPI and EFI RESET2 PeiService=0D + //=0D + Status =3D PchInitializeReset ();=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3BoardDebugInit (=0D + VOID=0D + )=0D +{=0D + ///=0D + /// Do Early PCH init=0D + ///=0D + EarlySiliconInit ();=0D + return EFI_SUCCESS;=0D +}=0D +=0D +EFI_BOOT_MODE=0D +EFIAPI=0D +KabylakeRvp3BoardBootModeDetect (=0D + VOID=0D + )=0D +{=0D + return BOOT_WITH_FULL_CONFIGURATION;=0D +}=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiMultiBoardInitPostMemLib.c b/Platform/Intel/KabylakeOpenBoa= rdPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c new file mode 100644 index 000000000000..70e93e94da11 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiMultiBoardInitPostMemLib.c @@ -0,0 +1,40 @@ +/** @file=0D + Kaby Lake RVP 3 Multi-Board Initialization Post-Memory library=0D +=0D +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3BoardInitBeforeSiliconInit (=0D + VOID=0D + );=0D +=0D +BOARD_POST_MEM_INIT_FUNC mKabylakeRvp3BoardInitFunc =3D {=0D + KabylakeRvp3BoardInitBeforeSiliconInit,=0D + NULL, // BoardInitAfterSiliconInit=0D +};=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +PeiKabylakeRvp3MultiBoardInitLibConstructor (=0D + VOID=0D + )=0D +{=0D + if ((LibPcdGetSku () =3D=3D BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetSku= () =3D=3D BoardIdSkylakeRvp3)) {=0D + return RegisterBoardPostMemInit (&mKabylakeRvp3BoardInitFunc);=0D + }=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/KabylakeOpenB= oardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.= inf new file mode 100644 index 000000000000..f955dd4ea966 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiMultiBoardInitPostMemLib.inf @@ -0,0 +1,56 @@ +## @file=0D +# Component information file for KabylakeRvp3InitLib in PEI post memory ph= ase.=0D +#=0D +# Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D PeiKabylakeRvp3MultiBoardInitLib=0D + FILE_GUID =3D C7D39F17-E5BA-41D9-8DFE-FF9017499280= =0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D NULL=0D + CONSTRUCTOR =3D PeiKabylakeRvp3MultiBoardInitLibConst= ructor=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + DebugLib=0D + BaseMemoryLib=0D + MemoryAllocationLib=0D + GpioExpanderLib=0D + PcdLib=0D + SiliconInitLib=0D + MultiBoardInitSupportLib=0D +=0D +[Packages]=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + KabylakeOpenBoardPkg/OpenBoardPkg.dec=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + KabylakeSiliconPkg/SiPkg.dec=0D + IntelSiliconPkg/IntelSiliconPkg.dec=0D +=0D +[Sources]=0D + PeiKabylakeRvp3InitPostMemLib.c=0D + KabylakeRvp3GpioTable.c=0D + KabylakeRvp3HdaVerbTables.c=0D + PeiMultiBoardInitPostMemLib.c=0D +=0D +[FixedPcd]=0D +=0D +[Pcd]=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel=0D +=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize=0D +=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable=0D +=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiMultiBoardInitPreMemLib.c b/Platform/Intel/KabylakeOpenBoar= dPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c new file mode 100644 index 000000000000..59b3177201db --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiMultiBoardInitPreMemLib.c @@ -0,0 +1,82 @@ +/** @file=0D + Kaby Lake RVP 3 Multi-Board Initialization Pre-Memory library=0D +=0D +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3BoardDetect (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3MultiBoardDetect (=0D + VOID=0D + );=0D +=0D +EFI_BOOT_MODE=0D +EFIAPI=0D +KabylakeRvp3BoardBootModeDetect (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3BoardDebugInit (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3BoardInitBeforeMemoryInit (=0D + VOID=0D + );=0D +=0D +BOARD_DETECT_FUNC mKabylakeRvp3BoardDetectFunc =3D {=0D + KabylakeRvp3MultiBoardDetect=0D +};=0D +=0D +BOARD_PRE_MEM_INIT_FUNC mKabylakeRvp3BoardPreMemInitFunc =3D {=0D + KabylakeRvp3BoardDebugInit,=0D + KabylakeRvp3BoardBootModeDetect,=0D + KabylakeRvp3BoardInitBeforeMemoryInit,=0D + NULL, // BoardInitAfterMemoryInit=0D + NULL, // BoardInitBeforeTempRamExit=0D + NULL, // BoardInitAfterTempRamExit=0D +};=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +KabylakeRvp3MultiBoardDetect (=0D + VOID=0D + )=0D +{=0D + KabylakeRvp3BoardDetect ();=0D + if ((LibPcdGetSku () =3D=3D BoardIdKabyLakeYLpddr3Rvp3) || (LibPcdGetSku= () =3D=3D BoardIdSkylakeRvp3)) {=0D + RegisterBoardPreMemInit (&mKabylakeRvp3BoardPreMemInitFunc);=0D + }=0D + return EFI_SUCCESS;=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +PeiKabylakeRvp3MultiBoardInitPreMemLibConstructor (=0D + VOID=0D + )=0D +{=0D + return RegisterBoardDetect (&mKabylakeRvp3BoardDetectFunc);=0D +} \ No newline at end of file diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBo= ardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf new file mode 100644 index 000000000000..23fe6b6f03c5 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiMultiBoardInitPreMemLib.inf @@ -0,0 +1,137 @@ +## @file=0D +# Component information file for PEI KabylakeRvp3 Board Init Pre-Mem Libra= ry=0D +#=0D +# Copyright (c) 2017 - 2021 Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D PeiKabylakeRvp3MultiBoardInitPreMemLi= b=0D + FILE_GUID =3D EA05BD43-136F-45EE-BBBA-27D75817574F= =0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D NULL=0D + CONSTRUCTOR =3D PeiKabylakeRvp3MultiBoardInitPreMemLi= bConstructor=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + DebugLib=0D + BaseMemoryLib=0D + MemoryAllocationLib=0D + PcdLib=0D + SiliconInitLib=0D + MultiBoardInitSupportLib=0D + EcLib=0D + PchResetLib=0D +=0D +[Packages]=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + KabylakeOpenBoardPkg/OpenBoardPkg.dec=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + KabylakeSiliconPkg/SiPkg.dec=0D + IntelSiliconPkg/IntelSiliconPkg.dec=0D +=0D +[Sources]=0D + PeiKabylakeRvp3InitPreMemLib.c=0D + KabylakeRvp3HsioPtssTables.c=0D + KabylakeRvp3SpdTable.c=0D + PeiMultiBoardInitPreMemLib.c=0D + PeiKabylakeRvp3Detect.c=0D +=0D +[Pcd]=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort=0D +=0D + # PCH-LP HSIO PTSS Table=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size=0D +=0D + # PCH-H HSIO PTSS Table=0D + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1=0D + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2=0D + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size=0D + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size=0D +=0D + # SA Misc Config=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize=0D +=0D + # PEG Reset By GPIO=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive=0D +=0D +=0D + # SPD Address Table=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3=0D +=0D + # CA Vref Configuration=0D +=0D + # Root Port Clock Info=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort0ClkInfo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort4ClkInfo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort5ClkInfo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort7ClkInfo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort8ClkInfo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort9ClkInfo=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortLanClkInfo=0D +=0D + # USB 2.0 Port AFE=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe=0D +=0D + # USB 2.0 Port Over Current Pin=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13=0D +=0D + # USB 3.0 Port Over Current Pin=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5=0D +=0D + # Misc=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent=0D +=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoar= dPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP= kg.dsc new file mode 100644 index 000000000000..f64555e3910f --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc @@ -0,0 +1,521 @@ +## @file=0D +# The main build description file for the KabylakeRvp3 board.=0D +#=0D +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +[Defines]=0D + DEFINE PLATFORM_PACKAGE =3D MinPlatformPkg=0D + DEFINE PLATFORM_SI_PACKAGE =3D KabylakeSiliconPkg=0D + DEFINE PLATFORM_SI_BIN_PACKAGE =3D KabylakeSiliconBinPkg=0D + DEFINE PLATFORM_BOARD_PACKAGE =3D KabylakeOpenBoardPkg=0D + DEFINE BOARD =3D KabylakeRvp3=0D + DEFINE PROJECT =3D $(PLATFORM_BOARD_PACKAGE= )/$(BOARD)=0D + DEFINE PEI_ARCH =3D IA32=0D + DEFINE DXE_ARCH =3D X64=0D + DEFINE TOP_MEMORY_ADDRESS =3D 0x0=0D +=0D + #=0D + # Default value for OpenBoardPkg.fdf use=0D + #=0D + DEFINE BIOS_SIZE_OPTION =3D SIZE_70=0D +=0D + PLATFORM_NAME =3D $(PLATFORM_PACKAGE)=0D + PLATFORM_GUID =3D 8470676C-18E8-467F-B126-= 28DB1941AA5A=0D + PLATFORM_VERSION =3D 0.1=0D + DSC_SPECIFICATION =3D 0x00010005=0D + OUTPUT_DIRECTORY =3D Build/$(PROJECT)=0D + SUPPORTED_ARCHITECTURES =3D IA32|X64=0D + BUILD_TARGETS =3D DEBUG|RELEASE=0D + SKUID_IDENTIFIER =3D ALL=0D + FLASH_DEFINITION =3D $(PROJECT)/OpenBoardPkg.= fdf=0D +=0D + FIX_LOAD_TOP_MEMORY_ADDRESS =3D 0x0=0D +=0D + #=0D + # Include PCD configuration for this board.=0D + #=0D + !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc=0D +=0D + !include OpenBoardPkgPcd.dsc=0D + !include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc=0D +=0D +[Defines]=0D +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1=0D + #=0D + # For backward compatibility API mode will use KabylakeFspBinPkg.=0D + # KabylakeFspBinPkg only supports API mode.=0D + #=0D + DEFINE PLATFORM_FSP_BIN_PACKAGE =3D KabylakeFspBinPkg=0D +!else=0D + #=0D + # AmberLakeFspBinPkg supports both API and Dispatch modes=0D + #=0D + DEFINE PLATFORM_FSP_BIN_PACKAGE =3D AmberLakeFspBinPkg=0D +!endif=0D +=0D +[PcdsDynamicExDefault.common.DEFAULT]=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode =3D=3D TRUE=0D +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 0=0D + #=0D + # Include FSP DynamicEx PCD settings in Dispatch mode=0D + #=0D + !include $(PLATFORM_FSP_BIN_PACKAGE)/FspPcds.dsc=0D +=0D + #=0D + # Override some FSP consumed PCD default value to match platform require= ment.=0D + #=0D + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress |gEfiMdePkgTokenSpaceGui= d.PcdPciExpressBaseAddress=0D + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpa= ceGuid.PcdPciExpressRegionLength=0D +!endif=0D +!endif=0D +=0D +##########################################################################= ######=0D +#=0D +# SKU Identification section - list of all SKU IDs supported by this board= .=0D +#=0D +##########################################################################= ######=0D +[SkuIds]=0D + 0x00|DEFAULT # 0|DEFAULT is reserved and always required.= =0D + 0x04|KabylakeRvp3=0D + 0x60|KabyLakeYLpddr3Rvp3=0D +=0D +##########################################################################= ######=0D +#=0D +# Includes section - other DSC file contents included for this board build= .=0D +#=0D +##########################################################################= ######=0D +=0D +#######################################=0D +# Library Includes=0D +#######################################=0D +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc=0D +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc=0D +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc=0D +!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc=0D +!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc=0D +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc=0D +=0D +#######################################=0D +# Component Includes=0D +#######################################=0D +=0D +# @todo: Change below line to [Components.$(PEI_ARCH)] after https://bugzi= lla.tianocore.org/show_bug.cgi?id=3D2308=0D +# is completed=0D +[Components.IA32]=0D +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc=0D +!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc=0D +=0D +# @todo: Change below line to [Components.$(DXE_ARCH)] after https://bugzi= lla.tianocore.org/show_bug.cgi?id=3D2308=0D +# is completed=0D +[Components.X64]=0D +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc=0D +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc=0D +=0D +#######################################=0D +# Build Option Includes=0D +#######################################=0D +!include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc=0D +!include OpenBoardPkgBuildOption.dsc=0D +=0D +##########################################################################= ######=0D +#=0D +# Library Class section - list of all Library Classes needed by this board= .=0D +#=0D +##########################################################################= ######=0D +=0D +[LibraryClasses.common]=0D + #######################################=0D + # Edk2 Packages=0D + #######################################=0D + FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFs= pWrapperApiLib.inf=0D + FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib= /PeiFspWrapperApiTestLib.inf=0D +=0D + #######################################=0D + # Silicon Initialization Package=0D + #######################################=0D + ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBloc= kLib.inf=0D + SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSilic= onInitLib.inf=0D +=0D +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1=0D + #=0D + # FSP API mode=0D + #=0D + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInit= LibFsp/PeiSiliconPolicyInitLibFsp.inf=0D +!else=0D + #=0D + # FSP Dispatch mode and non-FSP build (EDK2 build)=0D + #=0D + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInit= LibFsp/PeiSiliconPolicyInitLibFspAml.inf=0D +!endif=0D +=0D + #####################################=0D + # Platform Package=0D + #####################################=0D + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/B= oardInitLibNull.inf=0D + FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWra= pperHobProcessLib/PeiFspWrapperHobProcessLib.inf=0D + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf=0D + PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple/= PciHostBridgeLibSimple.inf=0D + PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimpl= e/PciSegmentInfoLibSimple.inf=0D + PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf=0D + PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootMa= nagerLib/DxePlatformBootManagerLib.inf=0D + ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiR= eportFvLib.inf=0D + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull= /TestPointCheckLibNull.inf=0D +=0D + #######################################=0D + # Board Package=0D + #######################################=0D + EcLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseEcLib/BaseEcLib.inf=0D + GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/Ba= seGpioExpanderLib.inf=0D + I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAcc= essLib.inf=0D + PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatf= ormSecLib/SecFspWrapperPlatformSecLib.inf=0D +=0D + # Thunderbolt=0D +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE=0D + DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTbtPol= icyLib/DxeTbtPolicyLib.inf=0D + TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmTbt= CommonLib/TbtCommonLib.inf=0D +!endif=0D +=0D + #######################################=0D + # Board-specific=0D + #######################################=0D + PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookL= ib.inf=0D +=0D +[LibraryClasses.IA32.SEC]=0D + #######################################=0D + # Platform Package=0D + #######################################=0D + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Sec= TestPointCheckLib.inf=0D + SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLib= Null/SecBoardInitLibNull.inf=0D + SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPolicy= UpdateLibNull/SiliconPolicyUpdateLibNull.inf=0D +=0D +[LibraryClasses.common.PEIM]=0D + #######################################=0D + # Silicon Package=0D + #######################################=0D + ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.= inf=0D +=0D + #######################################=0D + # Platform Package=0D + #######################################=0D + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupp= ortLib/PeiMultiBoardInitSupportLib.inf=0D + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf=0D + MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/PeiMultiBoardInitSupportLib.inf=0D + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointL= ib.inf=0D +!if $(TARGET) =3D=3D DEBUG=0D + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Pei= TestPointCheckLib.inf=0D +!endif=0D + SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrr= LibNull.inf=0D +=0D + #######################################=0D + # Board Package=0D + #######################################=0D +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1=0D + #=0D + # FSP API mode=0D + #=0D + SiliconPolicyUpdateLib|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyUpd= ateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf=0D +!else=0D + #=0D + # FSP Dispatch mode and non-FSP build (EDK2 build)=0D + #=0D + SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/PeiSiliconPolicyUpdateL= ib/PeiSiliconPolicyUpdateLib.inf=0D +!endif=0D +=0D + # Thunderbolt=0D +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE=0D + PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/Pe= iDTbtInitLib/PeiDTbtInitLib.inf=0D + PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtPol= icyLib/PeiTbtPolicyLib.inf=0D +!endif=0D +=0D +[LibraryClasses.common.DXE_DRIVER]=0D + #######################################=0D + # Silicon Initialization Package=0D + #######################################=0D + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/DxeSiliconPolicyInit= Lib/DxeSiliconPolicyInitLib.inf=0D +=0D + #######################################=0D + # Platform Package=0D + #######################################=0D + BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupport= Lib/DxeMultiBoardAcpiSupportLib.inf=0D + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupp= ortLib/DxeMultiBoardInitSupportLib.inf=0D + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWrapp= erPlatformLib/DxeFspWrapperPlatformLib.inf=0D + MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpi= SupportLib/DxeMultiBoardAcpiSupportLib.inf=0D + MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/DxeMultiBoardInitSupportLib.inf=0D + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointL= ib.inf=0D +=0D +!if $(TARGET) =3D=3D DEBUG=0D + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Dxe= TestPointCheckLib.inf=0D +!endif=0D + #######################################=0D + # Board Package=0D + #######################################=0D + BoardBdsHookLib|BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.i= nf=0D + BoardBootManagerLib|BoardModulePkg/Library/BoardBootManagerLib/BoardBoot= ManagerLib.inf=0D +=0D + #######################################=0D + # Board-specific=0D + #######################################=0D + SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/DxeSiliconPolicyUpdateL= ib/DxeSiliconPolicyUpdateLib.inf=0D +=0D +[LibraryClasses.X64.DXE_RUNTIME_DRIVER]=0D + #######################################=0D + # Silicon Initialization Package=0D + #######################################=0D + ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemL= ib/DxeRuntimeResetSystemLib.inf=0D +=0D +[LibraryClasses.X64.DXE_SMM_DRIVER]=0D + #######################################=0D + # Silicon Initialization Package=0D + #######################################=0D + SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCommonLi= b/SmmSpiFlashCommonLib.inf=0D +=0D + #######################################=0D + # Platform Package=0D + #######################################=0D + BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSuppor= tLib/SmmMultiBoardAcpiSupportLib.inf=0D + MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpi= SupportLib/SmmMultiBoardAcpiSupportLib.inf=0D + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointL= ib.inf=0D +!if $(TARGET) =3D=3D DEBUG=0D + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Smm= TestPointCheckLib.inf=0D +!endif=0D +=0D +#######################################=0D +# PEI Components=0D +#######################################=0D +# @todo: Change below line to [Components.$(PEI_ARCH)] after https://bugzi= lla.tianocore.org/show_bug.cgi?id=3D2308=0D +# is completed=0D +[Components.IA32]=0D + #######################################=0D + # Edk2 Packages=0D + #######################################=0D + UefiCpuPkg/SecCore/SecCore.inf {=0D + =0D + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf=0D + }=0D +=0D +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1=0D + #=0D + # In FSP API mode the policy has to be installed before FSP Wrapper upda= ting UPD.=0D + # Add policy as dependency for FSP Wrapper=0D + #=0D + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf {=0D + =0D + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicy= InitLibDependency/PeiPreMemSiliconPolicyInitLibDependency.inf=0D + }=0D + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf {=0D + =0D + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicy= InitLibDependency/PeiPostMemSiliconPolicyInitLibDependency.inf=0D + }=0D +!else=0D + #=0D + # In FSP Dispatch mode the policy will be installed after FSP-M dispatch= ed (only PrePolicy silicon-init executed).=0D + # Do not add policy dependency and let FspmWrapper report FSP-M FV to di= spatcher.=0D + #=0D + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf {=0D + =0D + SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPoli= cyInitLibNull/SiliconPolicyInitLibNull.inf=0D + }=0D + #=0D + # In FSP Dispatch mode the policy will be installed after FSP-S dispatch= ed (only PrePolicy silicon-init executed).=0D + # Do not add policy dependency and let FspsWrapper report FSP-S FV to di= spatcher.=0D + #=0D + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf {=0D + =0D + SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPoli= cyInitLibNull/SiliconPolicyInitLibNull.inf=0D + }=0D +!endif=0D +=0D + #######################################=0D + # Silicon Initialization Package=0D + #######################################=0D + IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf=0D + IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamp= lePei.inf=0D +=0D + #######################################=0D + # Platform Package=0D + #######################################=0D + $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf=0D + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf = {=0D + =0D + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D=3D = FALSE=0D + BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib= .inf=0D + !else=0D + NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.in= f=0D + !endif=0D + }=0D +=0D + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf= {=0D + =0D + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D=3D = FALSE=0D + BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLi= b.inf=0D + !else=0D + NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.i= nf=0D + !endif=0D + }=0D +=0D +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1=0D + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf {=0D + =0D + #=0D + # Hook a library constructor to update some policy fields when policy = is installed.=0D + #=0D + NULL|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiSiliconPolicyNoti= fyLib/PeiPreMemSiliconPolicyNotifyLib.inf=0D + }=0D + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe= m.inf=0D +!else=0D + #=0D + # FSP Dispatch mode will consume DefaultPolicyInit PPI produced by FSP t= o install a default policy PPI.=0D + # Similar as UPD in FSP API mode, DefaultPolicyInit PPI in Dispatch mode= can generate different policy structure=0D + # for different FSP revisions, but they must maintain backward compatibi= lity.=0D + #=0D + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf {=0D + =0D + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicy= InitLib/PeiPreMemSiliconPolicyInitLib.inf=0D + }=0D + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe= m.inf {=0D + =0D + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicy= InitLib/PeiPostMemSiliconPolicyInitLib.inf=0D + }=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE=0D + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf=0D +!endif=0D +=0D + #######################################=0D + # Board Package=0D + #######################################=0D + # Thunderbolt=0D +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE=0D + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf=0D +!endif=0D + $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf=0D +=0D +#######################################=0D +# DXE Components=0D +#######################################=0D +# @todo: Change below line to [Components.$(DXE_ARCH)] after https://bugzi= lla.tianocore.org/show_bug.cgi?id=3D2308=0D +# is completed=0D +[Components.X64]=0D + #######################################=0D + # Edk2 Packages=0D + #######################################=0D + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf=0D + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf=0D + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf=0D + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf=0D + MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf=0D + MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf=0D + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf{=0D + =0D + NULL|BoardModulePkg/Library/BdsPs2KbcLib/BdsPs2KbcLib.inf=0D + }=0D + UefiCpuPkg/CpuDxe/CpuDxe.inf=0D +=0D +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1=0D + #=0D + # FSP API mode=0D + #=0D + IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf=0D +!endif=0D +=0D + ShellPkg/Application/Shell/Shell.inf {=0D + =0D + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE=0D + =0D + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comma= ndsLib.inf=0D + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comma= ndsLib.inf=0D + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comma= ndsLib.inf=0D + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Com= mandsLib.inf=0D + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1C= ommandsLib.inf=0D + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comma= ndsLib.inf=0D + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1C= ommandsLib.inf=0D + NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2C= ommandsLib.inf=0D + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommand= Lib.inf=0D + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePars= ingLib.inf=0D + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfg= CommandLib.inf=0D + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib= .inf=0D + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf=0D + }=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE=0D + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf {=0D + =0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046=0D + =0D + !if $(TARGET) =3D=3D DEBUG=0D + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialP= ort.inf=0D + !endif=0D + }=0D +!endif=0D +=0D + #######################################=0D + # Silicon Initialization Package=0D + #######################################=0D + IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf=0D + $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf=0D +=0D + #######################################=0D + # Platform Package=0D + #######################################=0D + $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf=0D + $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf=0D + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf=0D + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf=0D + $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf=0D + $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE=0D + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE=0D +=0D + $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf=0D + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf=0D +=0D + $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf {=0D + =0D + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D=3D = FALSE=0D + BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEna= bleLib.inf=0D + !else=0D + NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.i= nf=0D + !endif=0D + }=0D +=0D + $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf {=0D + =0D + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D=3D = FALSE=0D + BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTabl= eLib.inf=0D + !else=0D + NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.i= nf=0D + !endif=0D + }=0D +=0D +!endif=0D +=0D + #######################################=0D + # Board Package=0D + #######################################=0D + # Thunderbolt=0D +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE=0D + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf=0D + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf=0D + $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE=0D + $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf {=0D + =0D + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D=3D = FALSE=0D + BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTabl= eLib.inf=0D + !else=0D + NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.i= nf=0D + !endif=0D + }=0D +!endif=0D + BoardModulePkg/LegacySioDxe/LegacySioDxe.inf=0D + BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoar= dPkg.fdf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP= kg.fdf new file mode 100644 index 000000000000..6cdf4e2f9f1f --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.fdf @@ -0,0 +1,715 @@ +## @file=0D +# FDF file of Platform.=0D +#=0D +# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf=0D +=0D +##########################################################################= ######=0D +#=0D +# FD Section=0D +# The [FD] Section is made up of the definition statements and a=0D +# description of what goes into the Flash Device Image. Each FD section= =0D +# defines one flash "device" image. A flash device image may be one of=0D +# the following: Removable media bootable image (like a boot floppy=0D +# image,) an Option ROM image (that would be "flashed" into an add-in=0D +# card,) a System "Flash" image (that would be burned into a system's=0D +# flash) or an Update ("Capsule") image that will be used to update and=0D +# existing system flash.=0D +#=0D +##########################################################################= ######=0D +[FD.KabylakeRvp3]=0D +#=0D +# FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks, c= annot be=0D +# assigned with PCD values. Instead, it uses the definitions for its varie= ty, which=0D +# are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS.=0D +#=0D +BaseAddress =3D $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdFlashAreaBaseAdd= ress #The base address of the FLASH Device.=0D +Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdFlashAreaSize = #The size in bytes of the FLASH Device=0D +ErasePolarity =3D 1=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +NumBlocks =3D $(FLASH_NUM_BLOCKS)=0D +=0D +DEFINE SIPKG_DXE_SMM_BIN =3D INF=0D +DEFINE SIPKG_PEI_BIN =3D INF=0D +=0D +# Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macr= o expression is not supported.=0D +# So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase to= get the real CodeCache base address.=0D +SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D $(gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvPreMemoryOffset)=0D +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gSiPkgTokenSpaceGui= d.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffs= et)=0D +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceGui= d.PcdFlashMicrocodeFvSize)=0D +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgToke= nSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60=0D +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvBase=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvSize=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvOffset=0D +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gSiPkgTok= enSpaceGuid.PcdFlashAreaBaseAddress=0D +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gSiPkgTok= enSpaceGuid.PcdFlashAreaSize=0D +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gSiPkgT= okenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.Pc= dFlashFvFspTOffset)=0D +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gSiPkgT= okenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.Pc= dFlashFvFspMOffset)=0D +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gSiPkgT= okenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.Pc= dFlashFvFspSOffset)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gSiPkgTok= enSpaceGuid.PcdFlashAreaBaseAddress=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gSiPkgTok= enSpaceGuid.PcdFlashAreaSize=0D +##########################################################################= ######=0D +#=0D +# Following are lists of FD Region layout which correspond to the location= s of different=0D +# images within the flash device.=0D +#=0D +# Regions must be defined in ascending order and may not overlap.=0D +#=0D +# A Layout Region start with a eight digit hex offset (leading "0x" requir= ed) followed by=0D +# the pipe "|" character, followed by the size of the region, also in hex = with the leading=0D +# "0x" characters. Like:=0D +# Offset|Size=0D +# PcdOffsetCName|PcdSizeCName=0D +# RegionType =0D +# Fv Size can be adjusted=0D +#=0D +##########################################################################= ######=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModul= ePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize=0D +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageVariableSize=0D +#NV_VARIABLE_STORE=0D +DATA =3D {=0D + ## This is the EFI_FIRMWARE_VOLUME_HEADER=0D + # ZeroVector []=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + # FileSystemGuid=0D + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,=0D + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,=0D + # FvLength: 0x40000=0D + 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + #Signature "_FVH" #Attributes=0D + 0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00,=0D + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision=0D + #=0D + # Be careful on CheckSum field.=0D + #=0D + 0x48, 0x00, 0x32, 0x09, 0x00, 0x00, 0x00, 0x02,=0D + #Blockmap[0]: 4 Blocks 0x10000 Bytes / Block=0D + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,=0D + #Blockmap[1]: End=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + ## This is the VARIABLE_STORE_HEADER=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable =3D=3D TRUE=0D + # Signature: gEfiAuthenticatedVariableGuid =3D { 0xaaf32c78, 0x947b, 0x= 439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}=0D + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,=0D + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,=0D +!else=0D + # Signature: gEfiVariableGuid =3D { 0xddcf3616, 0x3275, 0x4164, { 0x98,= 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}=0D + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,=0D + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,=0D +!endif=0D + #Size: 0x1E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariable= Size) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x1DFB8=0D + # This can speed up the Variable Dispatch a bit.=0D + 0xB8, 0xDF, 0x01, 0x00,=0D + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32=0D + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D +}=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeMod= ulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize=0D +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize=0D +#NV_FTW_WORKING=0D +DATA =3D {=0D + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D=0D + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }}=0D + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,=0D + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,=0D + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved=0D + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,=0D + # WriteQueueSize: UINT64=0D + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D +}=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModul= ePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize=0D +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize=0D +#NV_FTW_SPARE=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvAdvancedSize=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvAdvancedSize=0D +FV =3D FvAdvanced=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvSecuritySize=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvSecuritySize=0D +FV =3D FvSecurity=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvOsBootSize=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvOsBootSize=0D +FV =3D FvOsBoot=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvUefiBootSize=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvUefiBootSize=0D +FV =3D FvUefiBoot=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvPostMemorySize=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvPostMemorySize=0D +FV =3D FvPostMemory=0D +=0D +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFla= shMicrocodeFvSize=0D +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlash= MicrocodeFvSize=0D +#Microcode=0D +FV =3D FvMicrocode=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspSSize=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpace= Guid.PcdFlashFvFspSSize=0D +# FSP_S Section=0D +FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspMSize=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpace= Guid.PcdFlashFvFspMSize=0D +# FSP_M Section=0D +FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspTSize=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpace= Guid.PcdFlashFvFspTSize=0D +# FSP_T Section=0D +FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset|gMinPlatfo= rmPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryBase|gMinPlatform= PkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize=0D +FV =3D FvAdvancedPreMemory=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTok= enSpaceGuid.PcdFlashFvPreMemorySize=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgToken= SpaceGuid.PcdFlashFvPreMemorySize=0D +FV =3D FvPreMemory=0D +=0D +##########################################################################= ######=0D +#=0D +# FV Section=0D +#=0D +# [FV] section is used to define what components or modules are placed wit= hin a flash=0D +# device file. This section also defines order the components and modules= are positioned=0D +# within the image. The [FV] section consists of define statements, set s= tatements and=0D +# module statements.=0D +#=0D +##########################################################################= ######=0D +[FV.FvMicrocode]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D FALSE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D FALSE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +=0D +INF RuleOverride =3D MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/Microcode/Microc= odeUpdates.inf=0D +=0D +[FV.FvPreMemory]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D=0D +=0D +INF UefiCpuPkg/SecCore/SecCore.inf=0D +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode =3D=3D FALSE) || = (gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain =3D=3D FALSE= ) || (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1)=0D +#=0D +# PeiMain is needed only for FSP API mode or EDK2 build,=0D +# in FSP dispatch mode the one inside FSP Binary is launched=0D +# unless requested otherwise (PcdFspDispatchModeUseFspPeiMain =3D=3D FALSE= ).=0D +#=0D +INF MdeModulePkg/Core/Pei/PeiMain.inf=0D +!endif=0D +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf=0D +=0D +INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf=0D +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.in= f=0D +INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf=0D +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreM= em.inf=0D +INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf=0D +=0D +[FV.FvPostMemoryUncompact]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7=0D +=0D +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf=0D +=0D +# Init Board Config PCD=0D +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.i= nf=0D +INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf=0D +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPost= Mem.inf=0D +=0D +!if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable =3D=3D TRUE=0D +FILE FREEFORM =3D 4ad46122-ffeb-4a52-bfb0-518cfca02db0 {=0D + SECTION RAW =3D $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin=0D + SECTION UI =3D "Vbt"=0D +}=0D +FILE FREEFORM =3D 7BB28B99-61BB-11D5-9A5D-0090273FC14D {=0D + SECTION RAW =3D MdeModulePkg/Logo/Logo.bmp=0D +}=0D +!endif # PcdPeiDisplayEnable=0D +=0D +[FV.FvPostMemory]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D 9DFE49DB-8EF0-4D9C-B273-0036144DE917=0D +=0D +FILE FV_IMAGE =3D 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 {=0D + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUI= RED =3D TRUE {=0D + SECTION FV_IMAGE =3D FvPostMemoryUncompact=0D + }=0D +}=0D +=0D +[FV.FvUefiBootUncompact]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D A881D567-6CB0-4eee-8435-2E72D33E45B5=0D +=0D +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf=0D +=0D +INF UefiCpuPkg/CpuDxe/CpuDxe.inf=0D +INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf=0D +=0D +INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf=0D +INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf=0D +INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf=0D +INF MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.in= f=0D +INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf=0D +INF MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf=0D +INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf=0D +=0D +INF ShellPkg/Application/Shell/Shell.inf=0D +=0D +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf= =0D +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1=0D + #=0D + # Below module is used by FSP API mode=0D + #=0D + INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf=0D +!endif=0D +=0D +INF $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf=0D +=0D +[FV.FvUefiBoot]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D 0496D33D-EA79-495C-B65D-ABF607184E3B=0D +=0D +FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {=0D + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE {=0D + SECTION FV_IMAGE =3D FvUefiBootUncompact=0D + }=0D + }=0D +=0D +[FV.FvOsBootUncompact]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D A0F04529-B715-44C6-BCA4-2DEBDD01EEEC=0D +=0D +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf=0D +=0D +INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE=0D +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.in= f=0D +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf= =0D +INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf=0D +=0D +INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf=0D +INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf=0D +=0D +INF RuleOverride =3D DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/Boar= dAcpiDxe/BoardAcpiDxe.inf=0D +=0D +INF $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf= =0D +=0D +!endif=0D +=0D +[FV.FvLateSilicon]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE=0D +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxe.inf= =0D +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitD= xe.inf=0D +=0D +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmA= ccess.inf=0D +=0D +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSm= iDispatcher.inf=0D +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmC= ontrol.inf=0D +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf=0D +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf= =0D +=0D +INF RuleOverride =3D ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTab= les/SaAcpiTables.inf=0D +INF RuleOverride =3D ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTab= les/SaSsdt/SaSsdt.inf=0D +=0D +!endif=0D +=0D +[FV.FvOsBoot]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D 13BF8810-75FD-4B1A-91E6-E16C4201F80A=0D +=0D +FILE FV_IMAGE =3D B9020753-84A8-4BB6-947C-CE7D41F5CE39 {=0D + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE {=0D + SECTION FV_IMAGE =3D FvOsBootUncompact=0D + }=0D + }=0D +=0D +FILE FV_IMAGE =3D D4632741-510C-44E3-BE21-C3D6D7881485 {=0D + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE {=0D + SECTION FV_IMAGE =3D FvLateSilicon=0D + }=0D + }=0D +=0D +[FV.FvSecurityPreMemory]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16 #FV alignment and FV attributes setting.= =0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B=0D +=0D +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf= =0D +=0D +INF IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoS= amplePei.inf=0D +=0D +INF IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf=0D +=0D +[FV.FvSecurityPostMemory]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16 #FV alignment and FV attributes setting.= =0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D 4199E560-54AE-45E5-91A4-F7BC3804E14A=0D +=0D +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf= =0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE=0D +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf=0D +!endif=0D +=0D +[FV.FvSecurityLate]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D F753FE9A-EEFD-485B-840B-E032D538102C=0D +=0D +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf=0D +=0D +INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE=0D +=0D +INF $(PLATFORM_SI_PACKAGE)/Hsti/Dxe/HstiSiliconDxe.inf=0D +=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE=0D +=0D +INF $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE=0D +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf=0D +!endif=0D +=0D +!endif=0D +=0D +[FV.FvSecurity]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF=0D +=0D +FILE FV_IMAGE =3D 757CC075-1428-423D-A73C-22639706C119 {=0D + SECTION FV_IMAGE =3D FvSecurityPreMemory=0D + }=0D +=0D +FILE FV_IMAGE =3D 80BB8482-44D5-4BEC-82B5-8D87A933830B {=0D + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE {=0D + SECTION FV_IMAGE =3D FvSecurityPostMemory=0D + }=0D + }=0D +=0D +FILE FV_IMAGE =3D C83522D9-80A1-4D95-8C25-3F1370497406 {=0D + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE {=0D + SECTION FV_IMAGE =3D FvSecurityLate=0D + }=0D + }=0D +=0D +#=0D +# Pre-memory Advanced Features=0D +#=0D +[FV.FvAdvancedPreMemory]=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D 6053D78A-457E-4490-A237-31D0FBE2F305=0D +=0D +!include AdvancedFeaturePkg/Include/PreMemory.fdf=0D +=0D +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE=0D +INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf=0D +!endif=0D +=0D +#=0D +# Post-Memory Advanced Features=0D +#=0D +[FV.FvAdvancedUncompact]=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D BE3DF86F-E464-44A3-83F7-0D27E6B88C27=0D +=0D +!include AdvancedFeaturePkg/Include/PostMemory.fdf=0D +=0D +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE=0D +INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf=0D +INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf=0D +INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf=0D +!endif=0D +=0D +#=0D +# Compressed FV with Post-Memory Advanced Features=0D +#=0D +[FV.FvAdvanced]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D B23E7388-9953-45C7-9201-0473DDE5487A=0D +=0D +FILE FV_IMAGE =3D 5248467B-B87B-4E74-AC02-398AF4BCB712 {=0D + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE {=0D + SECTION FV_IMAGE =3D FvAdvancedUncompact=0D + }=0D + }=0D +=0D +##########################################################################= ######=0D +#=0D +# Rules are use with the [FV] section's module INF type to define=0D +# how an FFS file is created for a given INF file. The following Rule are = the default=0D +# rules for the different module type. User can add the customized rules t= o define the=0D +# content of the FFS file.=0D +#=0D +##########################################################################= ######=0D +=0D +!include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoar= dPkgBuildOption.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G= /OpenBoardPkgBuildOption.dsc new file mode 100644 index 000000000000..8e885cc6a4b8 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgBui= ldOption.dsc @@ -0,0 +1,151 @@ +## @file=0D +# platform build option configuration file.=0D +#=0D +# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[BuildOptions]=0D +# Define Build Options both for EDK and EDKII drivers.=0D +=0D +=0D + DEFINE DSC_S3_BUILD_OPTIONS =3D=0D +=0D + DEFINE DSC_CSM_BUILD_OPTIONS =3D=0D +=0D +!if gSiPkgTokenSpaceGuid.PcdAcpiEnable =3D=3D TRUE=0D + DEFINE DSC_ACPI_BUILD_OPTIONS =3D -DACPI_SUPPORT=3D1=0D +!else=0D + DEFINE DSC_ACPI_BUILD_OPTIONS =3D=0D +!endif=0D +=0D + DEFINE BIOS_GUARD_BUILD_OPTIONS =3D=0D +=0D + DEFINE OVERCLOCKING_BUILD_OPTION =3D=0D +=0D + DEFINE FSP_BINARY_BUILD_OPTIONS =3D=0D +=0D + DEFINE FSP_WRAPPER_BUILD_OPTIONS =3D -DFSP_WRAPPER_FLAG=0D +=0D + DEFINE SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS =3D=0D +=0D + DEFINE RESTRICTED_OPTION =3D=0D +=0D +=0D + DEFINE SV_BUILD_OPTIONS =3D=0D +=0D + DEFINE TEST_MENU_BUILD_OPTION =3D=0D +=0D +!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable =3D=3D FALSE=0D + DEFINE OPTIMIZE_DISABLE_OPTIONS =3D -Od -GL-=0D +!else=0D + DEFINE OPTIMIZE_DISABLE_OPTIONS =3D=0D +!endif=0D +=0D + DEFINE UP_SERVER_SUPPORT_BUILD_OPTIONS =3D=0D +=0D +=0D + DEFINE TPM_BUILD_OPTION =3D=0D +=0D + DEFINE TPM2_BUILD_OPTION =3D=0D +=0D + DEFINE DSC_TBT_BUILD_OPTIONS =3D=0D +=0D + DEFINE DSC_DCTT_BUILD_OPTIONS =3D=0D +=0D + DEFINE EMB_BUILD_OPTIONS =3D=0D +=0D + DEFINE DSC_MEMORY_DOWN_BUILD_OPTIONS =3D -DMEM_DOWN_FLAG=3D1=0D +=0D + DEFINE DSC_KBCEMUL_BUILD_OPTIONS =3D=0D +=0D + DEFINE BOOT_GUARD_BUILD_OPTIONS =3D=0D +=0D + DEFINE SECURE_BOOT_BUILD_OPTIONS =3D=0D +=0D + DEFINE USBTYPEC_BUILD_OPTION =3D=0D +=0D + DEFINE CAPSULE_BUILD_OPTIONS =3D=0D +=0D + DEFINE PERFORMANCE_BUILD_OPTION =3D=0D +=0D + DEFINE DEBUGUSEUSB_BUILD_OPTION =3D=0D +=0D + DEFINE DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION =3D -DDISABLE_NEW_= DEPRECATED_INTERFACES=3D1=0D +=0D + DEFINE SINITBIN_BUILD_OPTION =3D=0D +=0D + DEFINE MINTREE_FLAG_BUILD_OPTION =3D -DMINTREE_FLAG=3D1=0D +=0D +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTI= ONS) $(OVERCLOCKING_BUILD_OPTION) $(PERFORMANCE_BUILD_OPTION) $(EMB_BUILD_= OPTIONS) $(BIOS_GUARD_BUILD_OPTIONS) $(DSC_TBT_BUILD_OPTIONS)=0D +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS) $(BOOT_GUARD_BUILD_OPTIONS) $(DSC_MEMORY_DOWN_BUILD_OPTIONS) $(DEBUGU= SEUSB_BUILD_OPTION) $(DSC_S3_BUILD_OPTIONS)=0D +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS) $(FSP_BINARY_BUILD_OPTIONS) $(FSP_WRAPPER_BUILD_OPTIONS) $(SKIP_FSP_T= EMPRAM_INIT_AND_EXIT_OPTIONS)=0D +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS) $(DSC_KBCEMUL_BUILD_OPTIONS) $(CAPSULE_BUILD_OPTIONS) $(SECURE_BOOT_B= UILD_OPTIONS) $(DSC_CSM_BUILD_OPTIONS) $(DISABLE_NEW_DEPRECATED_INTERFACES_= BUILD_OPTION)=0D +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS) $(TPM2_BUILD_OPTION) $(TPM_BUILD_OPTION) $(DSC_DCTT_BUILD_OPTIONS)=0D +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS) $(DSC_ACPI_BUILD_OPTIONS) $(UP_SERVER_SUPPORT_BUILD_OPTIONS) $(USBTYP= EC_BUILD_OPTION) $(SINITBIN_BUILD_OPTION) $(MINTREE_FLAG_BUILD_OPTION)=0D +=0D +[BuildOptions.Common.EDKII]=0D +=0D +#=0D +# For IA32 Global Build Flag=0D +#=0D + *_*_IA32_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D P= I_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI=0D + *_*_IA32_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_IA32_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_IA32_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_IA32_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_IA32_NASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D +=0D +#=0D +# For IA32 Specific Build Flag=0D +#=0D +GCC: *_*_IA32_PP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D +GCC: *_*_IA32_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D P= I_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI -Wno-unused -Wl,--allow-mult= iple-definition=0D +MSFT: *_*_IA32_ASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D +MSFT: *_*_IA32_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI= =0D +MSFT: *_*_IA32_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS)=0D +MSFT: *_*_IA32_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS)=0D +MSFT: *_*_IA32_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS)=0D +MSFT: *_*_IA32_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS)=0D +=0D +#=0D +# For X64 Global Build Flag=0D +#=0D + *_*_X64_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D P= I_SPECIFICATION_VERSION=3D0x00010015=0D + *_*_X64_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_X64_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_X64_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_X64_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_X64_NASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D +=0D +=0D +#=0D +# For X64 Specific Build Flag=0D +#=0D +GCC: *_*_X64_PP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D +GCC: *_*_X64_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D P= I_SPECIFICATION_VERSION=3D0x00010015 -Wno-unused -Wl,--allow-multiple-defin= ition=0D +MSFT: *_*_X64_ASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D +MSFT: *_*_X64_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=3D0x00010015=0D +MSFT: *_*_X64_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS)=0D +MSFT: *_*_X64_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS)=0D +MSFT: *_*_X64_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D +MSFT: *_*_X64_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D +=0D +=0D +# Force PE/COFF sections to be aligned at 4KB boundaries to support page l= evel protection=0D +[BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_C= ORE]=0D + MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096=0D + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000=0D + =0D +# Force PE/COFF sections to be aligned at 4KB boundaries to support Memory= Attribute table=0D +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]=0D + MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096=0D + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000=0D +=0D +# Force PE/COFF sections to be aligned at 4KB boundaries to support NX pro= tection=0D +[BuildOptions.common.EDKII.DXE_DRIVER, BuildOptions.common.EDKII.DXE_CORE,= BuildOptions.common.EDKII.UEFI_DRIVER, BuildOptions.common.EDKII.UEFI_APPL= ICATION]=0D + #MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096=0D + #GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoar= dPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoa= rdPkgPcd.dsc new file mode 100644 index 000000000000..725596cbf71e --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd= .dsc @@ -0,0 +1,464 @@ +## @file=0D +# PCD configuration build description file for the KabylakeRvp3 board.=0D +#=0D +# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +##########################################################################= ######=0D +#=0D +# Pcd Section - list of all PCD Entries used by this board.=0D +#=0D +##########################################################################= ######=0D +=0D +[PcdsFixedAtBuild.common]=0D + ######################################=0D + # Key Boot Stage and FSP configuration=0D + ######################################=0D + #=0D + # Please select the Boot Stage here.=0D + # Stage 1 - enable debug (system deadloop after debug init)=0D + # Stage 2 - mem init (system deadloop after mem init)=0D + # Stage 3 - boot to shell only=0D + # Stage 4 - boot to OS=0D + # Stage 5 - boot to OS with security boot enabled=0D + # Stage 6 - boot with advanced features enabled=0D + #=0D + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4=0D +=0D + #=0D + # 0: FSP Wrapper is running in Dispatch mode.=0D + # 1: FSP Wrapper is running in API mode.=0D + #=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0=0D +=0D + #=0D + # FALSE: The board is not a FSP wrapper (FSP binary not used)=0D + # TRUE: The board is a FSP wrapper (FSP binary is used)=0D + #=0D + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE=0D +=0D + #=0D + # FALSE: The PEI Main included in FvPreMemory is used to dispatch all PE= IMs=0D + # (both inside FSP and outside FSP).=0D + # Pros:=0D + # * PEI Main is re-built from source and is always the latest v= ersion=0D + # * Platform code can link any desired LibraryClass to PEI Main= =0D + # (Ex: Custom DebugLib instance, SerialPortLib, etc.)=0D + # Cons:=0D + # * The PEI Main being used to execute FSP PEIMs is not the PEI= Main=0D + # that the FSP PEIMs were tested with, adding risk of breakag= e.=0D + # * Two copies of PEI Main will exist in the final binary,=0D + # #1 in FSP-M, #2 in FvPreMemory. The copy in FSP-M is never= =0D + # executed, wasting space.=0D + #=0D + # TRUE: The PEI Main included in FSP is used to dispatch all PEI= Ms=0D + # (both inside FSP and outside FSP). PEI Main will not be include= d in=0D + # FvPreMemory. This is the default and is the recommended choice.= =0D + #=0D + gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE=0D +=0D + #=0D + # FSP Base address PCD will be updated in FDF basing on flash map.=0D + #=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0=0D +=0D + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000=0D + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000=0D + gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000=0D + gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000=0D + gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000=0D +=0D +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1=0D + #=0D + # FSP API mode does not share stack with the boot loader,=0D + # so FSP needs more temporary memory for FSP heap + stack size.=0D + #=0D + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000=0D + #=0D + # FSP API mode does not need to enlarge the boot loader stack size=0D + # since the stacks are separate.=0D + #=0D + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000=0D +!else=0D + #=0D + # In FSP Dispatch mode boot loader stack size must be large=0D + # enough for executing both boot loader and FSP.=0D + #=0D + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x40000=0D +!endif=0D +=0D +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode =3D=3D FALSE) || = (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1)=0D + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid= .PcdPciExpressBaseAddress=0D + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpa= ceGuid.PcdPciExpressRegionLength=0D +!else=0D + #=0D + # FSP Dispatch mode requires more platform memory as boot loader and FSP= sharing the same=0D + # platform memory.=0D + #=0D + gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize|0x5500000=0D +!endif=0D +=0D +[PcdsFeatureFlag.common]=0D + ######################################=0D + # Edk2 Configuration=0D + ######################################=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst= |FALSE=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE=0D +=0D + ######################################=0D + # Silicon Configuration=0D + ######################################=0D + # Build switches=0D + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE=0D +=0D + # CPU=0D + gSiPkgTokenSpaceGuid.PcdBiosGuardEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE=0D + gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE=0D +=0D + # SA=0D + gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdSkycamEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdGmmEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE=0D +=0D + # ME=0D + gSiPkgTokenSpaceGuid.PcdAmtEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE=0D + gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE=0D +=0D + # Others=0D + gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdBootGuardEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdEvLoaderEnable|FALSE=0D + gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdSerialGpioEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE=0D + gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE=0D + gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdSoftwareGuardEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdSsaFlagEnable|FALSE=0D + gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE=0D +=0D + ######################################=0D + # Platform Configuration=0D + ######################################=0D + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE=0D + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE=0D + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE=0D + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE=0D + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE=0D + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE=0D + gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable|FALSE=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1=0D + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2=0D + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE=0D + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3=0D + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE=0D + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4=0D + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5=0D + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE=0D + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE=0D +!endif=0D +=0D +!if $(TARGET) =3D=3D DEBUG=0D + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE=0D +!else=0D + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE=0D +!endif=0D +=0D + ######################################=0D + # Board Configuration=0D + ######################################=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport|TRUE=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable|FALSE=0D +=0D +[PcdsFixedAtBuild.common]=0D + ######################################=0D + # Edk2 Configuration=0D + ######################################=0D +!if $(TARGET) =3D=3D RELEASE=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0=0D + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3=0D +!else=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F=0D + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07=0D +!endif=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE=0D + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1=0D +!endif=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEM= ORY_ADDRESS)=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140=0D +!endif=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable =3D=3D TRUE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1=0D +!endif=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE=0D +!if $(TARGET) =3D=3D DEBUG=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE=0D +!endif=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE=0D +!if $(TARGET) =3D=3D RELEASE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE=0D +!else=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE=0D +!endif=0D +=0D + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80=0D + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x40=0D + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0=0D + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F=0D + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44=0D + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2=0D + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800=0D + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC=0D + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08=0D +=0D + # Specifies timeout value in microseconds for the BSP to detect all APs = for the first time.=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000=0D +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode =3D=3D FALSE) || = (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1)=0D + #=0D + # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBui= ld=0D + # (They will be DynamicEx in FSP Dispatch mode)=0D + #=0D + ## Specifies max supported number of Logical Processors.=0D + # @Prompt Configure max supported number of Logical Processors=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|12=0D +=0D + ## Specifies the size of the microcode Region.=0D + # @Prompt Microcode Region size.=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0=0D +=0D + ## Specifies the AP wait loop state during POST phase.=0D + # The value is defined as below.=0D + # 1: Place AP in the Hlt-Loop state.=0D + # 2: Place AP in the Mwait-Loop state.=0D + # 3: Place AP in the Run-Loop state.=0D + # @Prompt The AP wait loop state.=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2=0D +!endif=0D +=0D + ######################################=0D + # Silicon Configuration=0D + ######################################=0D +=0D + # Refer to HstiFeatureBit.h for bit definitions=0D + gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2=0D + gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07=0D +=0D + ######################################=0D + # Platform Configuration=0D + ######################################=0D + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1=0D + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8=0D + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2=0D + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000=0D +=0D + #=0D + # The PCDs are used to control the Windows SMM Security Mitigations Tabl= e - Protection Flags=0D + #=0D + # BIT0: If set, expresses that for all synchronous SMM entries,SMM will = validate that input and output buffers lie entirely within the expected fix= ed memory regions.=0D + # BIT1: If set, expresses that for all synchronous SMM entries, SMM will= validate that input and output pointers embedded within the fixed communic= ation buffer only refer to address ranges \=0D + # that lie entirely within the expected fixed memory regions.=0D + # BIT2: Firmware setting this bit is an indication that it will not allo= w reconfiguration of system resources via non-architectural mechanisms.=0D + # BIT3-31: Reserved=0D + #=0D + gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07=0D +=0D +!if $(TARGET) =3D=3D RELEASE=0D + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402=0D +!else=0D + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B=0D +!endif=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b=0D +!if $(TARGET) =3D=3D RELEASE=0D + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70=0D +!else=0D + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 1=0D + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x00= , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00}=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 2=0D + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07= , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00}=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 3=0D + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07= , 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00}=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 4=0D + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07= , 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00}=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 5=0D + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F= , 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00}=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 6=0D + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F= , 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00}=0D +!endif=0D +=0D +=0D + ######################################=0D + # Board Configuration=0D + ######################################=0D + gBoardModulePkgTokenSpaceGuid.PcdPs2KbMsEnable|1=0D + gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0x00, 0x00, = 0x1F, 0x00}=0D +=0D +[PcdsFixedAtBuild.IA32]=0D + ######################################=0D + # Edk2 Configuration=0D + ######################################=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0=0D + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000=0D +=0D + ######################################=0D + # Platform Configuration=0D + ######################################=0D + gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000=0D +=0D +[PcdsFixedAtBuild.X64]=0D + ######################################=0D + # Edk2 Configuration=0D + ######################################=0D +=0D + # Default platform supported RFC 4646 languages: (American) English=0D + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US"= =0D +=0D +[PcdsPatchableInModule.common]=0D + ######################################=0D + # Edk2 Configuration=0D + ######################################=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046=0D +=0D + ######################################=0D + # Silicon Configuration=0D + ######################################=0D +!if $(TARGET) =3D=3D DEBUG=0D + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1=0D +!endif=0D +=0D +[PcdsDynamicDefault]=0D + ######################################=0D + # Edk2 Configuration=0D + ######################################=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0=0D +=0D + #=0D + # Set video to native resolution as Windows 8 WHCK requirement.=0D + #=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0=0D +=0D + gEfiSecurityPkgTokenSpaceGuid.PcdTcg2HashAlgorithmBitmap|0=0D + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2HashMask|0x0000001F=0D + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1=0D + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x28= , 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17}=0D +=0D + #=0D + # FSP Base address PCD will be updated in FDF basing on flash map.=0D + #=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0=0D + # Platform will pre-allocate UPD buffer and pass it to FspWrapper=0D + # Those dummy address will be patched before FspWrapper executing=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0xFFFFFFFF=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0xFFFFFFFF=0D +=0D + ######################################=0D + # Board Configuration=0D + ######################################=0D +=0D + # Thunderbolt Configuration=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcpiGpeSignature|0=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting|0=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm|0x0=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x0201001= 1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtControllerEn|0x1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtControllerType|0x1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioAccessType|0x2=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioLevel|0x1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify|0x1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI|0x1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd|56=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemRsvd|100=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd|100=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieRpNumber|0x1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSecurityMode|0x1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq|0x1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport|0x0=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWin10Support|0x0=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdExpander|0x0=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPchPcieRootPortHpe|0x00000001=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt|0x1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq|0x1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReqDelay|0x0=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtOffDelay|5000=0D +=0D +[PcdsDynamicHii.X64.DEFAULT]=0D + ######################################=0D + # Edk2 Configuration=0D + ######################################=0D + gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|= gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE=0D + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|1 # Variable: L"Timeout"=0D +!else=0D + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|5 # Variable: L"Timeout"=0D +!endif=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c b/Platform/Intel/Kabyla= keOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/D= xeGopPolicyInit.c new file mode 100644 index 000000000000..7744af6b3cfc --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c @@ -0,0 +1,175 @@ +/** @file=0D + This file initialises and Installs GopPolicy Protocol.=0D +=0D +Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "DxeGopPolicyInit.h"=0D +#include =0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED GOP_POLICY_PROTOCOL mGOPPolicy;=0D +GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mVbtSize =3D 0;=0D +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mVbtAddress =3D 0= ;=0D +=0D +//=0D +// Function implementations=0D +//=0D +=0D +/**=0D +=0D + @param[out] CurrentLidStatus=0D +=0D + @retval EFI_SUCCESS=0D + @retval EFI_UNSUPPORTED=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +GetPlatformLidStatus (=0D + OUT LID_STATUS *CurrentLidStatus=0D + )=0D +{=0D + return EFI_UNSUPPORTED;=0D +}=0D +/**=0D +=0D + @param[out] CurrentDockStatus=0D +=0D + @retval EFI_SUCCESS=0D + @retval EFI_UNSUPPORTED=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +GetPlatformDockStatus (=0D + OUT DOCK_STATUS CurrentDockStatus=0D + )=0D +{=0D + return EFI_UNSUPPORTED;=0D +}=0D +=0D +=0D +/**=0D +=0D + @param[out] VbtAddress=0D + @param[out] VbtSize=0D +=0D + @retval EFI_SUCCESS=0D + @retval EFI_NOT_FOUND=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +GetVbtData (=0D + OUT EFI_PHYSICAL_ADDRESS *VbtAddress,=0D + OUT UINT32 *VbtSize=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINTN FvProtocolCount;=0D + EFI_HANDLE *FvHandles;=0D + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;=0D + UINTN Index;=0D + UINT32 AuthenticationStatus;=0D + UINT8 *Buffer;=0D + UINTN VbtBufferSize;=0D +=0D +=0D + Status =3D EFI_NOT_FOUND;=0D + if ( mVbtAddress =3D=3D 0) {=0D + Fv =3D NULL;=0D +=0D + Buffer =3D 0;=0D + FvHandles =3D NULL;=0D + Status =3D gBS->LocateHandleBuffer (=0D + ByProtocol,=0D + &gEfiFirmwareVolume2ProtocolGuid,=0D + NULL,=0D + &FvProtocolCount,=0D + &FvHandles=0D + );=0D + if (!EFI_ERROR (Status)) {=0D + for (Index =3D 0; Index < FvProtocolCount; Index++) {=0D + Status =3D gBS->HandleProtocol (=0D + FvHandles[Index],=0D + &gEfiFirmwareVolume2ProtocolGuid,=0D + (VOID **) &Fv=0D + );=0D + VbtBufferSize =3D 0;=0D + Status =3D Fv->ReadSection (=0D + Fv,=0D + PcdGetPtr (PcdGraphicsVbtGuid),=0D + EFI_SECTION_RAW,=0D + 0,=0D + (VOID **) &Buffer,=0D + &VbtBufferSize,=0D + &AuthenticationStatus=0D + );=0D + if (!EFI_ERROR (Status)) {=0D + *VbtAddress =3D (EFI_PHYSICAL_ADDRESS)Buffer;=0D + *VbtSize =3D (UINT32)VbtBufferSize;=0D + mVbtAddress =3D *VbtAddress;=0D + mVbtSize =3D *VbtSize;=0D + Status =3D EFI_SUCCESS;=0D + break;=0D + }=0D + }=0D + } else {=0D + Status =3D EFI_NOT_FOUND;=0D + }=0D +=0D + if (FvHandles !=3D NULL) {=0D + FreePool (FvHandles);=0D + FvHandles =3D NULL;=0D + }=0D + } else {=0D + *VbtAddress =3D mVbtAddress;=0D + *VbtSize =3D mVbtSize;=0D + Status =3D EFI_SUCCESS;=0D + }=0D +=0D + return Status;=0D +}=0D +=0D +=0D +=0D +/**=0D +Initialize GOP DXE Policy=0D +=0D +@param[in] ImageHandle Image handle of this driver.=0D +=0D +@retval EFI_SUCCESS Initialization complete.=0D +@retval EFI_UNSUPPORTED The chipset is unsupported by this driver.= =0D +@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize= the driver.=0D +@retval EFI_DEVICE_ERROR Device error, driver exits abnormally.=0D +**/=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +GopPolicyInitDxe (=0D + IN EFI_HANDLE ImageHandle=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + //=0D + // Initialize the EFI Driver Library=0D + //=0D + SetMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL), 0);=0D +=0D + mGOPPolicy.Revision =3D GOP_POLICY_PROTOCOL_REVISION_03;= =0D + mGOPPolicy.GetPlatformLidStatus =3D GetPlatformLidStatus;=0D + mGOPPolicy.GetVbtData =3D GetVbtData;=0D + mGOPPolicy.GetPlatformDockStatus =3D GetPlatformDockStatus;=0D +=0D + //=0D + // Install protocol to allow access to this Policy.=0D + //=0D + Status =3D gBS->InstallMultipleProtocolInterfaces (=0D + &ImageHandle,=0D + &gGopPolicyProtocolGuid,=0D + &mGOPPolicy,=0D + NULL=0D + );=0D +=0D + return Status;=0D +}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h b/Platform/Intel/Kabyla= keOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/D= xeGopPolicyInit.h new file mode 100644 index 000000000000..17f9b545fcfb --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h @@ -0,0 +1,39 @@ +/** @file=0D +Header file for the GopPolicyInitDxe Driver.=0D +=0D +Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +#ifndef _GOP_POLICY_INIT_DXE_H_=0D +#define _GOP_POLICY_INIT_DXE_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +=0D +/**=0D +Initialize GOP DXE Policy=0D +=0D +@param[in] ImageHandle Image handle of this driver.=0D +=0D +@retval EFI_SUCCESS Initialization complete.=0D +@retval EFI_UNSUPPORTED The chipset is unsupported by this driver.= =0D +@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize= the driver.=0D +@retval EFI_DEVICE_ERROR Device error, driver exits abnormally.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +GopPolicyInitDxe(=0D + IN EFI_HANDLE ImageHandle=0D + );=0D +=0D +#endif=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h b/Platform/Intel/Kabylak= eOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/Dx= eSaPolicyInit.h new file mode 100644 index 000000000000..b49e13da54c1 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h @@ -0,0 +1,64 @@ +/** @file=0D + Header file for the SaPolicyInitDxe Driver.=0D +=0D +Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +#ifndef _SA_POLICY_INIT_DXE_H_=0D +#define _SA_POLICY_INIT_DXE_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +=0D +=0D +/**=0D + SA DXE Policy Driver Entry Point \n=0D + - Introduction \n=0D + System Agent DXE drivers behavior can be controlled by platform policy= without modifying reference code directly.=0D + Platform policy Protocol is initialized with default settings in this = funciton.=0D + This policy Protocol has to be initialized prior to System Agent initi= alization DXE drivers execution.=0D +=0D + - @pre=0D + - Runtime variable service should be ready if policy initialization re= quired.=0D +=0D + - @result=0D + SA_POLICY_PROTOCOL will be installed successfully and ready for System= Agent reference code use.=0D +=0D + - Porting Recommendations \n=0D + Policy should be initialized basing on platform design or user selecti= on (like BIOS Setup Menu)=0D +=0D + @param[in] ImageHandle - Image handle of this driver.=0D +=0D + @retval EFI_SUCCESS Initialization complete.=0D + @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.= =0D + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize= the driver.=0D + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SaPolicyInitDxe (=0D + IN EFI_HANDLE ImageHandle=0D + );=0D +=0D +/**=0D + Get data for platform policy from setup options.=0D +=0D + @param[in] SaPolicy The pointer to get SA Policy protoc= ol instance=0D +=0D + @retval EFI_SUCCESS Operation success.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +UpdateDxeSaPolicy (=0D + IN OUT SA_POLICY_PROTOCOL *SaPolicy=0D + );=0D +=0D +#endif=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c b/Platform/Intel/Kabyl= akeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/= DxeSaPolicyUpdate.c new file mode 100644 index 000000000000..fcd248fdf5cf --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c @@ -0,0 +1,66 @@ +/** @file=0D + This file is the library for SA DXE Policy initialization.=0D +=0D +Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "DxeSaPolicyInit.h"=0D +#include =0D +=0D +#define SA_VTD_RMRR_USB_LENGTH 0x20000=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mAddre= ss;=0D +GLOBAL_REMOVE_IF_UNREFERENCED UINTN mSize;= =0D +=0D +/**=0D + Update RMRR Base and Limit Address for USB.=0D +=0D +**/=0D +VOID=0D +UpdateRmrrUsbAddress (=0D + IN OUT SA_POLICY_PROTOCOL *SaPolicy=0D + )=0D +{=0D + EFI_STATUS Status;=0D + MISC_DXE_CONFIG *MiscDxeConfig;=0D +=0D + Status =3D GetConfigBlock ((VOID *)SaPolicy, &gMiscDxeConfigGuid, (VOID = *)&MiscDxeConfig);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + if (1) {=0D + mSize =3D EFI_SIZE_TO_PAGES(SA_VTD_RMRR_USB_LENGTH);=0D + mAddress =3D SIZE_4GB;=0D +=0D + Status =3D (gBS->AllocatePages) (=0D + AllocateMaxAddress,=0D + EfiReservedMemoryType,=0D + mSize,=0D + &mAddress=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + MiscDxeConfig->RmrrUsbBaseAddress[0] =3D mAddress;=0D + MiscDxeConfig->RmrrUsbBaseAddress[1] =3D mAddress + SA_VTD_RMRR_USB_LE= NGTH - 1;=0D + }=0D +}=0D +=0D +/**=0D + Get data for platform policy from setup options.=0D +=0D + @param[in] SaPolicy The pointer to get SA Policy protoc= ol instance=0D +=0D + @retval EFI_SUCCESS Operation success.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +UpdateDxeSaPolicy (=0D + IN OUT SA_POLICY_PROTOCOL *SaPolicy=0D + )=0D +{=0D + UpdateRmrrUsbAddress (SaPolicy);=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c b/Platform/Int= el/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUp= dateLib/DxeSiliconPolicyUpdateLib.c new file mode 100644 index 000000000000..d4dbb414a26f --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c @@ -0,0 +1,53 @@ +/** @file=0D +=0D +Copyright (c) 2017, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +=0D +#include "DxeSaPolicyInit.h"=0D +#include "DxeGopPolicyInit.h"=0D +=0D +/**=0D + Performs silicon late policy update.=0D +=0D + The meaning of Policy is defined by silicon code.=0D + It could be the raw data, a handle, a Protocol, etc.=0D + =0D + The input Policy must be returned by SiliconPolicyDoneLate().=0D + =0D + In FSP or non-FSP path, the board may use additional way to get=0D + the silicon policy data field based upon the input Policy.=0D +=0D + @param[in, out] Policy Pointer to policy.=0D +=0D + @return the updated policy.=0D +**/=0D +VOID *=0D +EFIAPI=0D +SiliconPolicyUpdateLate (=0D + IN VOID *Policy=0D + )=0D +{=0D + SA_POLICY_PROTOCOL *SaPolicy;=0D + EFI_STATUS Status;=0D +=0D + SaPolicy =3D Policy;=0D + UpdateDxeSaPolicy (SaPolicy);=0D +=0D + if (PcdGetBool(PcdIntelGopEnable)) {=0D + //=0D + // GOP Dxe Policy Initialization=0D + //=0D + Status =3D GopPolicyInitDxe(gImageHandle);=0D + DEBUG((DEBUG_INFO, "GOP Dxe Policy Initialization done\n"));=0D + ASSERT_EFI_ERROR(Status);=0D + }=0D +=0D + return Policy;=0D +}=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf b/Platform/I= ntel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicy= UpdateLib/DxeSiliconPolicyUpdateLib.inf new file mode 100644 index 000000000000..2abf1aef805a --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf @@ -0,0 +1,51 @@ +## @file=0D +# Component information file for Silicon Update Library=0D +#=0D +# Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D DxeSiliconUpdateLib=0D + FILE_GUID =3D C523609D-E354-416B-B24F-33468D4BD21D= =0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D SiliconUpdateLib=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + PcdLib=0D + DebugLib=0D + ConfigBlockLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + KabylakeSiliconPkg/SiPkg.dec=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + KabylakeOpenBoardPkg/OpenBoardPkg.dec=0D + IntelSiliconPkg/IntelSiliconPkg.dec=0D +=0D +[Sources]=0D + DxeSiliconPolicyUpdateLib.c=0D + DxeGopPolicyInit.c=0D + DxeSaPolicyUpdate.c=0D +=0D +[Pcd]=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid=0D +=0D +[Protocols]=0D + gEfiFirmwareVolume2ProtocolGuid ## CONSUMES=0D + gSaPolicyProtocolGuid ## CONSUMES=0D + gDxeSiPolicyProtocolGuid ## PRODUCES=0D + gGopPolicyProtocolGuid ## PRODUCES=0D +=0D +[Guids]=0D + gMiscDxeConfigGuid=0D +=0D +[Depex]=0D + gEfiVariableArchProtocolGuid=0D +=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Int= el/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUp= dateLib/PeiSiliconPolicyUpdateLib.c new file mode 100644 index 000000000000..2dce9be63c58 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c @@ -0,0 +1,601 @@ +/** @file=0D + Provides silicon policy update library functions.=0D +=0D +Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Get the next microcode patch pointer.=0D +=0D + @param[in, out] MicrocodeData - Input is a pointer to the last microcode= patch address found,=0D + and output points to the next patch addr= ess found.=0D +=0D + @retval EFI_SUCCESS - Patch found.=0D + @retval EFI_NOT_FOUND - Patch not found.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +RetrieveMicrocode (=0D + IN OUT CPU_MICROCODE_HEADER **MicrocodeData=0D + )=0D +{=0D + UINTN MicrocodeStart;=0D + UINTN MicrocodeEnd;=0D + UINTN TotalSize;=0D +=0D + if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) =3D=3D 0) || (FixedPcdGet32= (PcdFlashMicrocodeFvSize) =3D=3D 0)) {=0D + return EFI_NOT_FOUND;=0D + }=0D +=0D + ///=0D + /// Microcode binary in SEC=0D + ///=0D + MicrocodeStart =3D (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) +=0D + ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 (PcdFlashM= icrocodeFvBase))->HeaderLength +=0D + sizeof (EFI_FFS_FILE_HEADER);=0D +=0D + MicrocodeEnd =3D (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + (UINT= N) FixedPcdGet32 (PcdFlashMicrocodeFvSize);=0D +=0D + if (*MicrocodeData =3D=3D NULL) {=0D + *MicrocodeData =3D (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart;=0D + } else {=0D + if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart) = {=0D + DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart \n")= );=0D + return EFI_NOT_FOUND;=0D + }=0D +=0D + TotalSize =3D (UINTN) ((*MicrocodeData)->TotalSize);=0D + if (TotalSize =3D=3D 0) {=0D + TotalSize =3D 2048;=0D + }=0D +=0D + *MicrocodeData =3D (CPU_MICROCODE_HEADER *) ((UINTN)*MicrocodeData + T= otalSize);=0D + if (*MicrocodeData >=3D (CPU_MICROCODE_HEADER *) (UINTN) (MicrocodeEnd= ) || (*MicrocodeData)->TotalSize =3D=3D (UINT32) -1) {=0D + DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >=3D MicrocodeEnd \n"= ));=0D + return EFI_NOT_FOUND;=0D + }=0D + }=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Get the microcode patch pointer.=0D +=0D + @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or NULL i= f not found.=0D +**/=0D +EFI_PHYSICAL_ADDRESS=0D +PlatformCpuLocateMicrocodePatch (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + CPU_MICROCODE_HEADER *MicrocodeData;=0D + EFI_CPUID_REGISTER Cpuid;=0D + UINT32 UcodeRevision;=0D + UINTN MicrocodeBufferSize;=0D + VOID *MicrocodeBuffer =3D NULL;=0D +=0D + AsmCpuid (=0D + CPUID_VERSION_INFO,=0D + &Cpuid.RegEax,=0D + &Cpuid.RegEbx,=0D + &Cpuid.RegEcx,=0D + &Cpuid.RegEdx=0D + );=0D +=0D + UcodeRevision =3D GetCpuUcodeRevision ();=0D + MicrocodeData =3D NULL;=0D + while (TRUE) {=0D + ///=0D + /// Find the next patch address=0D + ///=0D + Status =3D RetrieveMicrocode (&MicrocodeData);=0D + DEBUG ((DEBUG_INFO, "MicrocodeData =3D %x\n", MicrocodeData));=0D +=0D + if (Status !=3D EFI_SUCCESS) {=0D + break;=0D + } else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData, &UcodeRevision= )) {=0D + break;=0D + }=0D + }=0D +=0D + if (EFI_ERROR (Status)) {=0D + return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL;=0D + }=0D +=0D + ///=0D + /// Check that microcode patch size is <=3D 128K max size,=0D + /// then copy the patch from FV to temp buffer for faster access.=0D + ///=0D + MicrocodeBufferSize =3D (UINTN) MicrocodeData->TotalSize;=0D +=0D + if (MicrocodeBufferSize <=3D MAX_MICROCODE_PATCH_SIZE) {=0D + MicrocodeBuffer =3D AllocatePages (EFI_SIZE_TO_PAGES (MicrocodeBufferS= ize));=0D + if (MicrocodeBuffer !=3D NULL) {=0D + DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n"));=0D + CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize);=0D +=0D + return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer;=0D + } else {=0D + DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for Microcode= Patch.\n"));=0D + }=0D + } else {=0D + DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max allowed= size of 128K.\n"));=0D + }=0D + return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL;=0D +}=0D +=0D +/**=0D + Update HSIO policy per board.=0D +=0D + @param[in] Policy - Policy PPI pointer (caller should ensure it is valid= pointer)=0D +=0D +**/=0D +VOID=0D +InstallPlatformHsioPtssTable (=0D + IN VOID *Policy=0D + )=0D +{=0D + HSIO_PTSS_TABLES *UnknowPtssTables;=0D + HSIO_PTSS_TABLES *SpecificPtssTables;=0D + HSIO_PTSS_TABLES *PtssTables;=0D + UINT8 PtssTableIndex;=0D + UINT32 UnknowTableSize;=0D + UINT32 SpecificTableSize;=0D + UINT32 TableSize;=0D + UINT32 Entry;=0D + UINT8 LaneNum;=0D + UINT8 Index;=0D + UINT8 MaxSataPorts;=0D + UINT8 MaxPciePorts;=0D + UINT8 PcieTopologyReal[PCH_MAX_PCIE_ROOT_PORTS];=0D + UINT8 PciePort;=0D + UINTN RpBase;=0D + UINTN RpDevice;=0D + UINTN RpFunction;=0D + UINT32 StrapFuseCfg;=0D + UINT8 PcieControllerCfg;=0D + PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig;=0D + PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig;=0D + EFI_STATUS Status;=0D +=0D + Status =3D GetConfigBlock (Policy, &gHsioPciePreMemConfigGuid, (VOID *) = &HsioPciePreMemConfig);=0D + ASSERT_EFI_ERROR (Status);=0D + Status =3D GetConfigBlock (Policy, &gHsioSataPreMemConfigGuid, (VOID *) = &HsioSataPreMemConfig);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + UnknowPtssTables =3D NULL;=0D + UnknowTableSize =3D 0;=0D + SpecificPtssTables =3D NULL;=0D + SpecificTableSize =3D 0;=0D +=0D + if (GetPchGeneration () =3D=3D SklPch) {=0D + switch (PchStepping ()) {=0D + case PchLpB0:=0D + case PchLpB1:=0D + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPts= sTable1);=0D + UnknowTableSize =3D PcdGet16 (PcdUnknowLpHsioPtssTable1Size);=0D + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsi= oPtssTable1);=0D + SpecificTableSize =3D PcdGet16 (PcdSpecificLpHsioPtssTable1Size);= =0D + break;=0D + case PchLpC0:=0D + case PchLpC1:=0D + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdUnknowLpHsioPts= sTable2);=0D + UnknowTableSize =3D PcdGet16 (PcdUnknowLpHsioPtssTable2Size);=0D + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdSpecificLpHsi= oPtssTable2);=0D + SpecificTableSize =3D PcdGet16 (PcdSpecificLpHsioPtssTable2Size);= =0D + break;=0D + case PchHB0:=0D + case PchHC0:=0D + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtss= Table1);=0D + UnknowTableSize =3D PcdGet16 (PcdUnknowHHsioPtssTable1Size);=0D + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsio= PtssTable1);=0D + SpecificTableSize =3D PcdGet16 (PcdSpecificHHsioPtssTable1Size);=0D + break;=0D + case PchHD0:=0D + case PchHD1:=0D + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtss= Table2);=0D + UnknowTableSize =3D PcdGet16 (PcdUnknowHHsioPtssTable2Size);=0D + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsio= PtssTable2);=0D + SpecificTableSize =3D PcdGet16 (PcdSpecificHHsioPtssTable2Size);=0D + break;=0D + default:=0D + UnknowPtssTables =3D NULL;=0D + UnknowTableSize =3D 0;=0D + SpecificPtssTables =3D NULL;=0D + SpecificTableSize =3D 0;=0D + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));=0D + }=0D + } else {=0D + switch (PchStepping ()) {=0D + case KblPchHA0:=0D + UnknowPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdUnknowHHsioPtss= Table2);=0D + UnknowTableSize =3D PcdGet16 (PcdUnknowHHsioPtssTable2Size);=0D + SpecificPtssTables =3D (VOID *) (UINTN) PcdGet32 (PcdSpecificHHsio= PtssTable2);=0D + SpecificTableSize =3D PcdGet16 (PcdSpecificHHsioPtssTable2Size);=0D + break;=0D + default:=0D + UnknowPtssTables =3D NULL;=0D + UnknowTableSize =3D 0;=0D + SpecificPtssTables =3D NULL;=0D + SpecificTableSize =3D 0;=0D + DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping\n"));=0D + }=0D + }=0D +=0D + PtssTableIndex =3D 0;=0D + MaxSataPorts =3D GetPchMaxSataPortNum ();=0D + MaxPciePorts =3D GetPchMaxPciePortNum ();=0D + ZeroMem (PcieTopologyReal, sizeof (PcieTopologyReal));=0D + //=0D + //Populate PCIe topology based on lane configuration=0D + //=0D + for (PciePort =3D 0; PciePort < MaxPciePorts; PciePort +=3D 4) {=0D + Status =3D GetPchPcieRpDevFun (PciePort, &RpDevice, &RpFunction);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + RpBase =3D MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (= UINT32) RpFunction);=0D + StrapFuseCfg =3D MmioRead32 (RpBase + R_PCH_PCIE_STRPFUSECFG);=0D + PcieControllerCfg =3D (UINT8) ((StrapFuseCfg & B_PCH_PCIE_STRPFUSECFG_= RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC);=0D + DEBUG ((DEBUG_INFO, "PCIE Port %d StrapFuseCfg Value =3D %d\n", PciePo= rt, PcieControllerCfg));=0D + }=0D + for (Index =3D 0; Index < MaxPciePorts; Index++) {=0D + DEBUG ((DEBUG_INFO, "PCIE PTSS Assigned RP %d Topology =3D %d\n", Inde= x, PcieTopologyReal[Index]));=0D + }=0D + //=0D + //Case 1: BoardId is known, Topology is known/unknown=0D + //Case 1a: SATA=0D + //=0D + PtssTables =3D SpecificPtssTables;=0D + TableSize =3D SpecificTableSize;=0D + for (Index =3D 0; Index < MaxSataPorts; Index++) {=0D + if (PchGetSataLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) {=0D + for (Entry =3D 0; Entry < TableSize; Entry++) {=0D + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) &&=0D + (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LANE= _OWN_SATA)=0D + )=0D + {=0D + PtssTableIndex++;=0D + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_PCH_HS= IO_RX_DWORD20) &&=0D + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_R= X_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) =3D=3D (UINT32) B_PCH_HSIO_RX_DWORD= 20_ICFGCTLEDATATAP_FULLRATE_5_0)) {=0D + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnab= le =3D TRUE;=0D + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag = =3D (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry]= .PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;= =0D + } else if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R= _PCH_HSIO_TX_DWORD8)) {=0D + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) = B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) =3D=3D (UINT32) B_PCH_HSIO_TX_DWORD= 8_ORATE00MARGIN_5_0) {=0D + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp= Enable =3D TRUE;=0D + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp= =3D (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSI= O_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0);= =0D + }=0D + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32) = B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) =3D=3D (UINT32) B_PCH_HSIO_TX_DWORD= 8_ORATE01MARGIN_5_0) {=0D + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp= Enable =3D TRUE;=0D + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp= =3D (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_HSI= O_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0);= =0D + }=0D + } else {=0D + ASSERT (FALSE);=0D + }=0D + }=0D + }=0D + }=0D + }=0D + //=0D + //Case 1b: PCIe=0D + //=0D + for (Index =3D 0; Index < MaxPciePorts; Index++) {=0D + if (PchGetPcieLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) {=0D + for (Entry =3D 0; Entry < TableSize; Entry++) {=0D + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) &&=0D + (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LANE= _OWN_PCIEDMI) &&=0D + (PcieTopologyReal[Index] =3D=3D PtssTables[Entry].Topology)) {= =0D + PtssTableIndex++;=0D + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_PCH_HS= IO_RX_DWORD25) &&=0D + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO_R= X_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) =3D=3D (UINT32) B_PCH_HSIO_RX_DWORD25_= CTLE_ADAPT_OFFSET_CFG_4_0)) {=0D + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable = =3D TRUE;=0D + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle = =3D (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Ent= ry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0);= =0D +=0D + } else {=0D + ASSERT (FALSE);=0D + }=0D + }=0D + }=0D + }=0D + }=0D + //=0D + //Case 2: BoardId is unknown, Topology is known/unknown=0D + //=0D + if (PtssTableIndex =3D=3D 0) {=0D + DEBUG ((DEBUG_INFO, "PTSS Settings for unknown board will be applied\n= "));=0D +=0D + PtssTables =3D UnknowPtssTables;=0D + TableSize =3D UnknowTableSize;=0D +=0D + for (Index =3D 0; Index < MaxSataPorts; Index++) {=0D + if (PchGetSataLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) {=0D + for (Entry =3D 0; Entry < TableSize; Entry++) {=0D + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) &&=0D + (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LA= NE_OWN_SATA)=0D + )=0D + {=0D + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_PCH_= HSIO_RX_DWORD20) &&=0D + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO= _RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0) =3D=3D (UINT32) B_PCH_HSIO_RX_DWO= RD20_ICFGCTLEDATATAP_FULLRATE_5_0)) {=0D + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEn= able =3D TRUE;=0D + HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag = =3D (PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[Entry= ].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0;= =0D +=0D + } else if (PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) = R_PCH_HSIO_TX_DWORD8) {=0D + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32= ) B_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0) =3D=3D (UINT32) B_PCH_HSIO_TX_DWO= RD8_ORATE00MARGIN_5_0) {=0D + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleA= mpEnable =3D TRUE;=0D + HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleA= mp =3D (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_H= SIO_TX_DWORD8_ORATE00MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE00MARGIN_5_0)= ;=0D +=0D + }=0D + if (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & (UINT32= ) B_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0) =3D=3D (UINT32) B_PCH_HSIO_TX_DWO= RD8_ORATE01MARGIN_5_0) {=0D + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleA= mpEnable =3D TRUE;=0D + HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleA= mp =3D (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) B_PCH_H= SIO_TX_DWORD8_ORATE01MARGIN_5_0) >> N_PCH_HSIO_TX_DWORD8_ORATE01MARGIN_5_0)= ;=0D + }=0D + } else {=0D + ASSERT (FALSE);=0D + }=0D + }=0D + }=0D + }=0D + }=0D + for (Index =3D 0; Index < MaxPciePorts; Index++) {=0D + if (PchGetPcieLaneNum (Index, &LaneNum) =3D=3D EFI_SUCCESS) {=0D + for (Entry =3D 0; Entry < TableSize; Entry++) {=0D + if ((LaneNum =3D=3D PtssTables[Entry].PtssTable.LaneNum) &&=0D + (PtssTables[Entry].PtssTable.PhyMode =3D=3D V_PCH_PCR_FIA_LA= NE_OWN_PCIEDMI) &&=0D + (PcieTopologyReal[Index] =3D=3D PtssTables[Entry].Topology))= {=0D + if ((PtssTables[Entry].PtssTable.Offset =3D=3D (UINT32) R_PCH_= HSIO_RX_DWORD25) &&=0D + (((UINT32) ~PtssTables[Entry].PtssTable.BitMask & B_PCH_HSIO= _RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0) =3D=3D (UINT32) B_PCH_HSIO_RX_DWORD2= 5_CTLE_ADAPT_OFFSET_CFG_4_0)) {=0D + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable = =3D TRUE;=0D + HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle = =3D (UINT8)((PtssTables[Entry].PtssTable.Value & (UINT32) ~PtssTables[E= ntry].PtssTable.BitMask) >> N_PCH_HSIO_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0= );=0D + } else {=0D + ASSERT (FALSE);=0D + }=0D + }=0D + }=0D + }=0D + }=0D + }=0D +}=0D +=0D +/**=0D + Update PreMem phase silicon policy per board.=0D +=0D + @param[in] Policy - Policy PPI pointer.=0D +=0D + @retval Policy - Policy PPI pointer.=0D +=0D +**/=0D +VOID *=0D +EFIAPI=0D +SiliconPolicyUpdatePreMem (=0D + IN VOID *Policy=0D + )=0D +{=0D + EFI_STATUS Status;=0D + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;=0D + MEMORY_CONFIG_NO_CRC *MemConfigNoCrc;=0D + VOID *Buffer;=0D + UINTN VariableSize;=0D + VOID *MemorySavedData;=0D + UINT8 SpdAddressTable[4];=0D +=0D + DEBUG((DEBUG_INFO, "\nUpdating Policy in Pre-Mem\n"));=0D +=0D + if (Policy !=3D NULL) {=0D + SpdAddressTable[0] =3D PcdGet8 (PcdMrcSpdAddressTable0);=0D + SpdAddressTable[1] =3D PcdGet8 (PcdMrcSpdAddressTable1);=0D + SpdAddressTable[2] =3D PcdGet8 (PcdMrcSpdAddressTable2);=0D + SpdAddressTable[3] =3D PcdGet8 (PcdMrcSpdAddressTable3);=0D +=0D + MiscPeiPreMemConfig =3D NULL;=0D + Status =3D GetConfigBlock (Policy, &gSaMiscPeiPreMemConfigGuid, (VOID = *) &MiscPeiPreMemConfig);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + if (MiscPeiPreMemConfig !=3D NULL) {=0D + //=0D + // Pass board specific SpdAddressTable to policy=0D + //=0D + CopyMem ((VOID *) MiscPeiPreMemConfig->SpdAddressTable, (VOID *) Spd= AddressTable, (sizeof (UINT8) * 4));=0D +=0D + //=0D + // Set size of SMRAM=0D + //=0D + MiscPeiPreMemConfig->TsegSize =3D PcdGet32 (PcdTsegSize);=0D +=0D + //=0D + // Initialize S3 Data variable (S3DataPtr). It may be used for warm = and fast boot paths.=0D + // Note: AmberLake FSP does not implement the FSPM_ARCH_CONFIG_PPI a= dded in FSP 2.1, hence=0D + // the platform specific S3DataPtr must be used instead.=0D + //=0D + VariableSize =3D 0;=0D + MemorySavedData =3D NULL;=0D + Status =3D PeiGetVariable (=0D + L"MemoryConfig",=0D + &gFspNonVolatileStorageHobGuid,=0D + &MemorySavedData,=0D + &VariableSize=0D + );=0D + DEBUG ((DEBUG_INFO, "Get L\"MemoryConfig\" gFspNonVolatileStorageHob= Guid - %r\n", Status));=0D + DEBUG ((DEBUG_INFO, "MemoryConfig Size - 0x%x\n", VariableSize));=0D + if (!EFI_ERROR (Status)) {=0D + MiscPeiPreMemConfig->S3DataPtr =3D MemorySavedData;=0D + }=0D +=0D + //=0D + // In FSP Dispatch Mode these BAR values are initialized by SiliconP= olicyInitPreMem() in=0D + // KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLib/PeiPolicyInitP= reMem.c; this function calls=0D + // PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI->PeiPreMemPolicyInit() to i= nitialize all Config Blocks=0D + // with default policy values (including these BAR values.) PEI_PREM= EM_SI_DEFAULT_POLICY_INIT_PPI=0D + // is implemented in the FSP. Make sure the value that FSP is using = matches the value we are using.=0D + //=0D + ASSERT (PcdGet64 (PcdMchBaseAddress) <=3D 0xFFFFFFFF);=0D + ASSERT (MiscPeiPreMemConfig->MchBar =3D=3D (UINT32) PcdGet64 (PcdM= chBaseAddress));=0D + ASSERT (MiscPeiPreMemConfig->SmbusBar =3D=3D PcdGet16 (PcdSmbusBaseA= ddress));=0D + }=0D + MemConfigNoCrc =3D NULL;=0D + Status =3D GetConfigBlock (Policy, &gMemoryConfigNoCrcGuid, (VOID *) &= MemConfigNoCrc);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + if (MemConfigNoCrc !=3D NULL) {=0D + MemConfigNoCrc->PlatformMemorySize =3D PcdGet32 (PcdPeiMinMemorySize= );=0D +=0D + //=0D + // Only if SpdAddressTables are all zero we need to pass hard-coded = SPD data buffer.=0D + // Otherwise FSP will retrieve SPD from DIMM basing on SpdAddressTab= les policy.=0D + //=0D + if (*((UINT32 *) (UINTN) SpdAddressTable) =3D=3D 0) {=0D + DEBUG((DEBUG_INFO, "Override MemorySpdPtr...\n"));=0D + CopyMem((VOID *) MemConfigNoCrc->SpdData->SpdData[0][0], (VOID *)(= UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize));=0D + CopyMem((VOID *) MemConfigNoCrc->SpdData->SpdData[1][0], (VOID *)(= UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize));=0D + }=0D +=0D + DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Sett= ings...\n"));=0D + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap);=0D + if (Buffer) {=0D + CopyMem ((VOID *) MemConfigNoCrc->DqByteMap->DqByteMap[0], Buffer,= 12);=0D + CopyMem ((VOID *) MemConfigNoCrc->DqByteMap->DqByteMap[1], (UINT8*= ) Buffer + 12, 12);=0D + }=0D + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram);=0D + if (Buffer) {=0D + CopyMem ((VOID *) MemConfigNoCrc->DqsMap->DqsMapCpu2Dram[0], Buffe= r, 8);=0D + CopyMem ((VOID *) MemConfigNoCrc->DqsMap->DqsMapCpu2Dram[1], (UINT= 8*) Buffer + 8, 8);=0D + }=0D +=0D + DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rc= omp Target Settings...\n"));=0D + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor);=0D + if (Buffer) {=0D + CopyMem ((VOID *) &(MemConfigNoCrc->RcompData->RcompResistor[0]), = Buffer, 6);=0D + }=0D + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget);=0D + if (Buffer) {=0D + CopyMem ((VOID *) &(MemConfigNoCrc->RcompData->RcompTarget[0]), Bu= ffer, 10);=0D + }=0D + }=0D + //=0D + // Update PCD policy=0D + //=0D + InstallPlatformHsioPtssTable (Policy);=0D + }=0D +=0D + return Policy;=0D +}=0D +=0D +/**=0D + Update PostMem phase silicon policy per board.=0D +=0D + @param[in] Policy - Policy PPI pointer.=0D +=0D + @retval Policy - Policy PPI pointer.=0D +=0D +**/=0D +VOID *=0D +EFIAPI=0D +SiliconPolicyUpdatePostMem (=0D + IN VOID *Policy=0D + )=0D +{=0D + EFI_STATUS Status;=0D + VOID *Buffer;=0D + VOID *MemBuffer;=0D + UINT32 Size;=0D + GRAPHICS_PEI_CONFIG *GtConfig;=0D + CPU_CONFIG *CpuConfig;=0D +=0D + DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n"));=0D +=0D + GtConfig =3D NULL;=0D + Status =3D GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, (VO= ID *)&GtConfig);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + if (GtConfig !=3D NULL) {=0D + //=0D + // Always enable PEI graphics initialization.=0D + //=0D + GtConfig->PeiGraphicsPeimInit =3D 1;=0D + Size =3D 0;=0D + Buffer =3D NULL;=0D + PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size);=0D + if (Buffer =3D=3D NULL) {=0D + DEBUG((DEBUG_WARN, "Could not locate VBT\n"));=0D + } else {=0D + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= );=0D + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) {=0D + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);=0D + GtConfig->GraphicsConfigPtr =3D MemBuffer;=0D + } else {=0D + DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n"));=0D + GtConfig->GraphicsConfigPtr =3D 0;=0D + }=0D + }=0D + DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", G= tConfig->GraphicsConfigPtr));=0D + DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size= ));=0D + Size =3D 0;=0D + Buffer =3D NULL;=0D + PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, = &Size);=0D + if (Buffer =3D=3D NULL) {=0D + DEBUG((DEBUG_WARN, "Could not locate Logo\n"));=0D + } else {=0D + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= );=0D + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) {=0D + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);=0D + GtConfig->LogoPtr =3D MemBuffer;=0D + GtConfig->LogoSize =3D Size;=0D + } else {=0D + DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n"));=0D + GtConfig->LogoPtr =3D 0;=0D + GtConfig->LogoSize =3D 0;=0D + }=0D + }=0D + DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", GtCon= fig->LogoPtr));=0D + DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", GtCo= nfig->LogoSize));=0D + }=0D +=0D + CpuConfig =3D NULL;=0D + Status =3D GetConfigBlock ((VOID *) Policy, &gCpuConfigGuid, (VOID *)&Cp= uConfig);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + if (CpuConfig !=3D NULL) {=0D + CpuConfig->MicrocodePatchAddress =3D PlatformCpuLocateMicrocodePatch (= );=0D + }=0D + return Policy;=0D +}=0D +=0D +/**=0D + Update late phase silicon policy per board.=0D +=0D + @param[in] Policy - Policy PPI pointer.=0D +=0D + @retval Policy - Policy PPI pointer.=0D +=0D +**/=0D +VOID *=0D +EFIAPI=0D +SiliconPolicyUpdateLate (=0D + IN VOID *Policy=0D + )=0D +{=0D + return Policy;=0D +}=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/I= ntel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicy= UpdateLib/PeiSiliconPolicyUpdateLib.inf new file mode 100644 index 000000000000..5c2da68bf935 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf @@ -0,0 +1,92 @@ +### @file=0D +# Component information file for silicon policy update library=0D +#=0D +# Copyright (c) 2019 - 2021 Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D PeiSiliconPolicyUpdateLib=0D + FILE_GUID =3D 14F5D83D-76A5-4241-BEC5-987E70E233D5= =0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D SiliconPolicyUpdateLib=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + PcdLib=0D + DebugLib=0D + ConfigBlockLib=0D + BaseMemoryLib=0D + MemoryAllocationLib=0D + PeiLib=0D + CpuPlatformLib=0D + PchPcieRpLib=0D + PchInfoLib=0D + MmPciLib=0D + IoLib=0D + PchHsioLib=0D +=0D +[Packages]=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + MdePkg/MdePkg.dec=0D + IntelFsp2Pkg/IntelFsp2Pkg.dec=0D + UefiCpuPkg/UefiCpuPkg.dec=0D + KabylakeSiliconPkg/SiPkg.dec=0D + KabylakeOpenBoardPkg/OpenBoardPkg.dec=0D + IntelSiliconPkg/IntelSiliconPkg.dec=0D +=0D +[Sources]=0D + PeiSiliconPolicyUpdateLib.c=0D +=0D +[Guids]=0D + gMemoryConfigNoCrcGuid=0D + gTianoLogoGuid ## CONSUMES=0D + gGraphicsPeiConfigGuid ## CONSUMES=0D + gCpuConfigGuid ## CONSUMES=0D + gHsioPciePreMemConfigGuid ## CONSUMES=0D + gHsioSataPreMemConfigGuid ## CONSUMES=0D + gSaMiscPeiPreMemConfigGuid ## CONSUMES=0D + gFspNonVolatileStorageHobGuid ## CONSUMES=0D +=0D +[Pcd]=0D + gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize=0D + gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase=0D + gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize=0D + gSiPkgTokenSpaceGuid.PcdMchBaseAddress=0D + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress=0D + gSiPkgTokenSpaceGuid.PcdTsegSize=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONSUME= S=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONSUME= S=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## CONSUME= S=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUME= S=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize=0D +=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size=0D +=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size=0D +=0D + # SPD Address Table=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2=0D + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_bo= ard.py b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_board.= py new file mode 100644 index 000000000000..41668120f109 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_board.py @@ -0,0 +1,68 @@ +# @ build_board.py=0D +# This is a sample code provides Optional dynamic imports=0D +# of build functions to the BuildBios.py script=0D +#=0D +# Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +=0D +"""=0D +This module serves as a sample implementation of the build extension=0D +scripts=0D +"""=0D +=0D +=0D +def pre_build_ex(config, functions):=0D + """Additional Pre BIOS build function=0D +=0D + :param config: The environment variables to be used in the build proce= ss=0D + :type config: Dictionary=0D + :param functions: A dictionary of function pointers=0D + :type functions: Dictionary=0D + :returns: nothing=0D + """=0D + print("pre_build_ex")=0D + return None=0D +=0D +=0D +def build_ex(config, functions):=0D + """Additional BIOS build function=0D +=0D + :param config: The environment variables to be used in the build proce= ss=0D + :type config: Dictionary=0D + :param functions: A dictionary of function pointers=0D + :type functions: Dictionary=0D + :returns: config dictionary=0D + :rtype: Dictionary=0D + """=0D + print("build_ex")=0D + return None=0D +=0D +=0D +def post_build_ex(config, functions):=0D + """Additional Post BIOS build function=0D +=0D + :param config: The environment variables to be used in the post=0D + build process=0D + :type config: Dictionary=0D + :param functions: A dictionary of function pointers=0D + :type functions: Dictionary=0D + :returns: config dictionary=0D + :rtype: Dictionary=0D + """=0D + print("post_build_ex")=0D + return None=0D +=0D +=0D +def clean_ex(config, functions):=0D + """Additional clean function=0D +=0D + :param config: The environment variables to be used in the build proce= ss=0D + :type config: Dictionary=0D + :param functions: A dictionary of function pointers=0D + :type functions: Dictionary=0D + :returns: config dictionary=0D + :rtype: Dictionary=0D + """=0D + print("clean_ex")=0D + return None=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_co= nfig.cfg b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_conf= ig.cfg new file mode 100644 index 000000000000..f6ae4b342aa0 --- /dev/null +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.cfg @@ -0,0 +1,36 @@ +# @ build_config.cfg=0D +# This is the KabylakeRvp3 board specific build settings=0D +#=0D +# Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +=0D +=0D +[CONFIG]=0D +WORKSPACE_PLATFORM_BIN =3D=0D +EDK_SETUP_OPTION =3D=0D +openssl_path =3D=0D +PLATFORM_BOARD_PACKAGE =3D KabylakeOpenBoardPkg=0D +PROJECT =3D KabylakeOpenBoardPkg/KabylakeRvp3=0D +BOARD =3D KabylakeRvp3=0D +FLASH_MAP_FDF =3D KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/FlashMapIn= clude.fdf=0D +PROJECT_DSC =3D KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc=0D +BOARD_PKG_PCD_DSC =3D KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.ds= c=0D +ADDITIONAL_SCRIPTS =3D KabylakeOpenBoardPkg/KabylakeRvp3/build_board.py=0D +PrepRELEASE =3D DEBUG=0D +SILENT_MODE =3D FALSE=0D +EXT_CONFIG_CLEAR =3D=0D +CapsuleBuild =3D FALSE=0D +EXT_BUILD_FLAGS =3D=0D +CAPSULE_BUILD =3D 0=0D +TARGET =3D DEBUG=0D +TARGET_SHORT =3D D=0D +PERFORMANCE_BUILD =3D FALSE=0D +FSP_WRAPPER_BUILD =3D TRUE=0D +FSP_BIN_PKG =3D AmberLakeFspBinPkg=0D +FSP_BIN_PKG_FOR_API_MODE =3D KabylakeFspBinPkg=0D +FSP_PKG_NAME =3D AmberLakeFspPkg=0D +FSP_BINARY_BUILD =3D FALSE=0D +FSP_TEST_RELEASE =3D FALSE=0D +SECURE_BOOT_ENABLE =3D FALSE=0D +BIOS_INFO_GUID =3D C83BCE0E-6F16-4D3C-8D9F-4D6F5A032929=0D --=20 2.31.1