From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web08.31227.1629150936433545725 for ; Mon, 16 Aug 2021 14:55:36 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: nathaniel.l.desimone@intel.com) X-IronPort-AV: E=McAfee;i="6200,9189,10078"; a="301531423" X-IronPort-AV: E=Sophos;i="5.84,327,1620716400"; d="scan'208";a="301531423" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Aug 2021 14:55:34 -0700 X-IronPort-AV: E=Sophos;i="5.84,327,1620716400"; d="scan'208";a="519914266" Received: from nldesimo-desk1.amr.corp.intel.com ([10.255.228.201]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Aug 2021 14:55:34 -0700 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Chasel Chiu , Sai Chaganty , Benjamin Doron , Michael Kubacki Subject: [edk2-platforms] [PATCH V2] KabylakeSiliconPkg: Default for PeciC10Reset should be 1 Date: Mon, 16 Aug 2021 14:53:44 -0700 Message-Id: <20210816215344.29742-1-nathaniel.l.desimone@intel.com> X-Mailer: git-send-email 2.27.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The default value for CpuConfigLibPreMemConfig->PeciC10Reset should be 1 so that Peci Reset on C10 exit is disabled. Other bug fixes in KabylakeSiliconPkg\Cpu\Library\PeiCpuPolicyLibPreMem\PeiCpuPolicyLib.c 1. PCI configuration space can only be read 32-bits at a time. Converted MmioRead64 to MmioRead32. 2. Added a RShiftU64() call to prevent compiler instrinsics from being inserted. Since this is a 64-bit integer shift done in IA-32 mode it is possible for intrinsic calls to be added. Cc: Chasel Chiu Cc: Sai Chaganty Cc: Benjamin Doron Cc: Michael Kubacki Signed-off-by: Nate DeSimone --- .../PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c | 30 +++++++++++++++---- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c index 35041322a7..9a334d8ec2 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c @@ -1,7 +1,7 @@ /** @file This file is PeiCpuPolicy library. -Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -45,13 +45,31 @@ LoadCpuConfigLibPreMemConfigDefault ( CpuConfigLibPreMemConfig->BootFrequency = 1; // Maximum non-turbo Performance CpuConfigLibPreMemConfig->ActiveCoreCount = 0; // All cores active CpuConfigLibPreMemConfig->VmxEnable = CPU_FEATURE_ENABLE; - CpuConfigLibPreMemConfig->CpuRatio = ((AsmReadMsr64 (MSR_PLATFORM_INFO) >> N_PLATFORM_INFO_MAX_RATIO) & B_PLATFORM_INFO_RATIO_MASK); + CpuConfigLibPreMemConfig->CpuRatio = RShiftU64 (AsmReadMsr64 (MSR_PLATFORM_INFO), N_PLATFORM_INFO_MAX_RATIO) & B_PLATFORM_INFO_RATIO_MASK; + /// /// FCLK Frequency /// - CpuFamily = GetCpuFamily(); - CpuSku = GetCpuSku(); - MchBar = MmioRead64 (MmPciBase (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN) + R_SA_MCHBAR) &~BIT0; + CpuFamily = GetCpuFamily (); + CpuSku = GetCpuSku (); + + DEBUG_CODE_BEGIN (); + /// + /// Ensure the upper 7-bits [38:32] of MCHBAR are zero so we can access MCHBAR in 32-bit mode. + /// + MchBar = MmioRead32 (MmPciBase (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN) + R_SA_MCHBAR + 0x4) & 0x7F; + if (MchBar != 0x0) { + DEBUG (( + DEBUG_ERROR, + "Error: [%a]:[%dL] MCHBAR configured to >4GB\n", + __FUNCTION__, + __LINE__ + )); + } + ASSERT (MchBar == 0x0); + DEBUG_CODE_END (); + + MchBar = MmioRead32 (MmPciBase (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN) + R_SA_MCHBAR) &~BIT0; if (IsPchLinkDmi (CpuFamily) && (MmioRead16 (MmPciBase (SA_PEG_BUS_NUM, SA_PEG_DEV_NUM, SA_PEG10_FUN_NUM) + PCI_VENDOR_ID_OFFSET) != 0xFFFF)) { PegDisabled = MmioRead32 ((UINTN) MchBar + R_SA_MCHBAR_BIOS_RESET_CPL_OFFSET) & BIT3; } else { @@ -67,6 +85,8 @@ LoadCpuConfigLibPreMemConfigDefault ( } else { CpuConfigLibPreMemConfig->FClkFrequency = 0; // 800MHz } + + CpuConfigLibPreMemConfig->PeciC10Reset = 1; // Disables Peci Reset on C10 exit } /** -- 2.27.0.windows.1