From: "Jeremy Linton" <jeremy.linton@arm.com>
To: devel@edk2.groups.io
Cc: pete@akeo.ie, ardb+tianocore@kernel.org, awarkentin@vmware.com,
Sunny.Wang@arm.com, samer.el-haj-mahmoud@arm.com,
Jeremy Linton <jeremy.linton@arm.com>
Subject: [PATCH v3 2/7] Platform/RaspberryPi: Break XHCI into its own SSDT
Date: Thu, 19 Aug 2021 23:16:14 -0500 [thread overview]
Message-ID: <20210820041619.87248-3-jeremy.linton@arm.com> (raw)
In-Reply-To: <20210820041619.87248-1-jeremy.linton@arm.com>
Lets prepare to switch between XHCI and PCI by moving
the XHCI definition into its own SSDT. That way we can
select it based on the menu settings. The resource
producer/consumer flag is also corrected.
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 1 +
Platform/RaspberryPi/AcpiTables/Dsdt.asl | 3 --
Platform/RaspberryPi/AcpiTables/Xhci.asl | 35 ++++++++++++++--------
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 8 +++++
4 files changed, 31 insertions(+), 16 deletions(-)
diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
index 1ddc9ca5fe..f3e8d950c1 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -38,6 +38,7 @@
SpcrPl011.aslc
Pptt.aslc
SsdtThermal.asl
+ Xhci.asl
[Packages]
ArmPkg/ArmPkg.dec
diff --git a/Platform/RaspberryPi/AcpiTables/Dsdt.asl b/Platform/RaspberryPi/AcpiTables/Dsdt.asl
index 1ee6379f46..b594d50bdf 100644
--- a/Platform/RaspberryPi/AcpiTables/Dsdt.asl
+++ b/Platform/RaspberryPi/AcpiTables/Dsdt.asl
@@ -64,9 +64,6 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)
Scope (\_SB_)
{
include ("Pep.asl")
-#if (RPI_MODEL == 4)
- include ("Xhci.asl")
-#endif
Device (CPU0)
{
diff --git a/Platform/RaspberryPi/AcpiTables/Xhci.asl b/Platform/RaspberryPi/AcpiTables/Xhci.asl
index bc3fea60f9..9b37277956 100644
--- a/Platform/RaspberryPi/AcpiTables/Xhci.asl
+++ b/Platform/RaspberryPi/AcpiTables/Xhci.asl
@@ -9,6 +9,8 @@
#include <IndustryStandard/Bcm2711.h>
+#include "AcpiTables.h"
+
/*
* The following can be used to remove parenthesis from
* defined macros that the compiler complains about.
@@ -24,12 +26,17 @@
*/
#define XHCI_REG_LENGTH 0x1000
-Device (SCB0) {
- Name (_HID, "ACPI0004")
- Name (_UID, 0x0)
- Name (_CCA, 0x0)
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4XHCI", 2)
+{
+ Scope (\_SB_)
+ {
+
+ Device (SCB0) {
+ Name (_HID, "ACPI0004")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
- Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
+ Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
/*
* Container devices with _DMA must have _CRS, meaning SCB0
* to provide all resources that XHC0 consumes (except
@@ -57,15 +64,15 @@ Device (SCB0) {
Add (MMBE, XHCI_REG_LENGTH - 1, MMBE)
Add (MMLE, XHCI_REG_LENGTH - 1, MMLE)
Return (RBUF)
- }
+ }
- Name (_DMA, ResourceTemplate() {
+ Name (_DMA, ResourceTemplate() {
/*
* XHC0 is limited to DMA to first 3GB. Note this
* only applies to PCIe, not GENET or other devices
* next to the A72.
*/
- QWordMemory (ResourceConsumer,
+ QWordMemory (ResourceProducer,
,
MinFixed,
MaxFixed,
@@ -79,10 +86,10 @@ Device (SCB0) {
,
,
)
- })
+ })
- Device (XHC0)
- {
+ Device (XHC0)
+ {
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x0) // _UID: Unique ID
Name (_CCA, 0x0) // _CCA: Cache Coherency Attribute
@@ -131,5 +138,7 @@ Device (SCB0) {
Debug = "xHCI enable"
Store (0x6, CMND)
}
- }
-}
+ } // end XHC0
+ } //end SCB0
+ } //end scope sb
+} //end definition block
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 87f6b4e7bb..7c5786303d 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -814,6 +814,14 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {
PcdToken(PcdSdIsArasan),
SsdtEmmcNameOpReplace
},
+#if (RPI_MODEL == 4)
+ {
+ SIGNATURE_64 ('R', 'P', 'I', '4', 'X', 'H', 'C', 'I'),
+ 0,
+ PcdToken(PcdXhciPci),
+ NULL
+ },
+#endif
{ // DSDT
SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
0,
--
2.13.7
next prev parent reply other threads:[~2021-08-20 4:16 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-20 4:16 [PATCH v3 0/7] RPi4: Enable ACPI PCIe conduit Jeremy Linton
2021-08-20 4:16 ` [PATCH v3 1/7] Platform/RaspberryPi: Add XHCI/PCI selection menu Jeremy Linton
2021-08-20 20:14 ` Andrei Warkentin
2021-08-20 20:31 ` Samer El-Haj-Mahmoud
2021-08-20 4:16 ` Jeremy Linton [this message]
2021-08-20 20:15 ` [PATCH v3 2/7] Platform/RaspberryPi: Break XHCI into its own SSDT Andrei Warkentin
2021-08-20 4:16 ` [PATCH v3 3/7] Platform/RaspberryPi: Add PCIe SSDT Jeremy Linton
2021-08-20 20:15 ` Andrei Warkentin
2021-08-20 4:16 ` [PATCH v3 4/7] Silicon/Broadcom/Bcm27xx: Relax PCIe device restriction Jeremy Linton
2021-08-20 20:16 ` Andrei Warkentin
2021-08-20 4:16 ` [PATCH v3 5/7] Silicon/Broadcom/Bcm27xx: Move linkup check into the cfg accessor Jeremy Linton
2021-08-20 20:16 ` Andrei Warkentin
2021-08-22 13:37 ` Ard Biesheuvel
2021-08-22 13:47 ` Ard Biesheuvel
2021-08-20 4:16 ` [PATCH v3 6/7] Platform/RaspberryPi: Enable NVMe boot on CM4 Jeremy Linton
2021-08-20 20:16 ` Andrei Warkentin
2021-08-20 20:37 ` Samer El-Haj-Mahmoud
2021-08-20 4:16 ` [PATCH v3 7/7] Platform/RaspberryPi: Add Linux quirk support Jeremy Linton
2021-08-20 20:15 ` Andrei Warkentin
2021-08-20 20:35 ` Samer El-Haj-Mahmoud
2021-08-20 20:27 ` [PATCH v3 0/7] RPi4: Enable ACPI PCIe conduit Samer El-Haj-Mahmoud
[not found] ` <7d39c23-6578-6bb9-ab5f-9d242d7ff42d@invisible.ca>
2021-08-22 13:55 ` Ard Biesheuvel
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