From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web09.80078.1629432985195318332 for ; Thu, 19 Aug 2021 21:16:25 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: jeremy.linton@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C2E441474; Thu, 19 Aug 2021 21:16:24 -0700 (PDT) Received: from u200856.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 762DC3F40C; Thu, 19 Aug 2021 21:16:24 -0700 (PDT) From: "Jeremy Linton" To: devel@edk2.groups.io Cc: pete@akeo.ie, ardb+tianocore@kernel.org, awarkentin@vmware.com, Sunny.Wang@arm.com, samer.el-haj-mahmoud@arm.com, Jeremy Linton , =?UTF-8?q?Ren=C3=A9=20Treffer?= Subject: [PATCH v3 4/7] Silicon/Broadcom/Bcm27xx: Relax PCIe device restriction Date: Thu, 19 Aug 2021 23:16:16 -0500 Message-Id: <20210820041619.87248-5-jeremy.linton@arm.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210820041619.87248-1-jeremy.linton@arm.com> References: <20210820041619.87248-1-jeremy.linton@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable The CM4 has an actual PCIe slot, so the device filtering need to be a little less restrictive WRT busses with more than 1 device given that switches can now appear in the topology. Since it is possible to start numbering the busses with a non-zero value, the bus restriction should be based on the secondary side of the root port. This isn't likely but its better than hard-coding the limit. Suggested-by: Ren=C3=A9 Treffer Signed-off-by: Jeremy Linton --- .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 21 ++++++++++++++-= ------ 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSeg= mentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegm= entLib.c index 44ce3b4b99..6d15e82fa2 100644 --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib= .c +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib= .c @@ -19,6 +19,7 @@ #include #include #include +#include =20 typedef enum { PciCfgWidthUint8 =3D 0, @@ -78,6 +79,9 @@ PciSegmentLibGetConfigBase ( UINT64 Base; UINT64 Offset; UINT32 Dev; + UINT32 Bus; + UINT32 Data; + UINT32 HostPortSec; =20 Base =3D PCIE_REG_BASE; Offset =3D Address & 0xFFF; /* Pick off the 4k register offset= */ @@ -89,17 +93,20 @@ PciSegmentLibGetConfigBase ( Base +=3D PCIE_EXT_CFG_DATA; if (mPciSegmentLastAccess !=3D Address) { Dev =3D EFI_PCI_ADDR_DEV (Address); + Bus =3D EFI_PCI_ADDR_BUS (Address); + HostPortSec =3D MmioRead8 (PCIE_REG_BASE + + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET)= ; + /* - * Scan things out directly rather than translating the "bus" to a= device, etc.. - * only we need to limit each bus to a single device. + * There can only be a single device on bus 1 (downstream of root)= . + * Subsequent busses (behind a PCIe switch) can have more. */ - if (Dev < 1) { - MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); - mPciSegmentLastAccess =3D Address; - } else { - mPciSegmentLastAccess =3D 0; + if (Dev > 0 && (Bus <=3D HostPortSec)) { return 0xFFFFFFFF; } + + MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); + mPciSegmentLastAccess =3D Address; } } return Base + Offset; --=20 2.13.7