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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?Xgx50OarUWeD+o5ra8Ef56ZVN43Rf8IITEhMDIvZBUiUiGCkfMLUuiKLYHqs?= =?us-ascii?Q?BdyhMwl9rJcUnwjsbwDEY/FqWX7IRrnrrMgXFmE76NwkXI6mcOHulKTEPV9Y?= =?us-ascii?Q?5FWs11ShPxi6K2mXRSnfQv/gfzxcA7O0Z33W57i/mm5Aj3YqaKjG46rrkeVA?= =?us-ascii?Q?yx3zx6RdNUafPwXF1Ab9NhbBzCXaREKnd06QumwyRsnfSURKMi53FQ3Rhg9g?= =?us-ascii?Q?accjm+qKulx1enXCCqwGh6jdfK0aY+cGMBIZK1Nsy8Ckso/m1eXeyGcBRsFE?= =?us-ascii?Q?G809HOGhnDOBnz4rJbaXEIrG1g2uvdd0rOIqpFYtIicfssAZodt8eIFRAi06?= =?us-ascii?Q?SXHJBUMZgruMMw6yjNo+y5/jry+RHwM0l7dHKpTJT2Htfx632X2SZ6NWaw8N?= =?us-ascii?Q?Uu1eNjwJOqIHvzCJ+4HopGKRNdwRNvMMLIK4reXZWDWF7BUZJ2ImqcEKudP5?= =?us-ascii?Q?HHeYjTLkWmZNaW88ei+nx5d90pBTtt8wGBqypsPnM6D82pLuI5jmwLHEA8cV?= =?us-ascii?Q?0gbi9lNDS1GvELZuo+S7vXx4Re2Ze85rmK8CXhaiqLWc9J9rCShEL1ayzZr3?= =?us-ascii?Q?rAzM2SMRh3djGw/XhkRixAi0DfM+KDGyICcvbZAmC39x4Zs2MmoFrtPUOmiW?= =?us-ascii?Q?CX5xYE/E6TS6Y1Emv86KRYBmwKmwDf43HTrJmcofiQXwU4IHJKQ/CEKCPvs+?= =?us-ascii?Q?zohdlNyJLZEfvDUtd1X2jKGPWkhmirgfkl+3o4fVmHy56qI7E59U+9l/FJFa?= =?us-ascii?Q?K4CNZp/m9Kfk7W2sELSrk6TFhWOUCQLDwSbYTOEuKLNtnrIJVOOXCWTqgnH8?= =?us-ascii?Q?8e/QrI4AaUjOFvBruJyYJ4zwrRmOsPZfwcUeDAxf561rFklkxelVHbDU++m2?= =?us-ascii?Q?5ljtWCvD0o4pPIX+Zh95arVz75r/xJrjuhn94CiLrEEm49/yyJJnubryBOTT?= =?us-ascii?Q?VZahwscGGJVwGfIdIAS83kv2261Siql7hqUJgINK3UKNCZNl2/Hy/inWHM25?= =?us-ascii?Q?1d9dqPWYSGW4TxtI+DRBFW1Pinr4U7523pJqW0jPdOj0oYL1S+wtHYwMqZ3i?= =?us-ascii?Q?A2RaSgf76sevPrH+mRLaKILKQObWEzyN7ESDe6IsSMpC5ZJw59qS91aGf2L1?= =?us-ascii?Q?YOh6n7BxGvJMeJBryd48bu4w7+XJgsjG5GgFQuduxYxB/k370axfz/OGj1ib?= =?us-ascii?Q?IvwOnv2NeJbQWZzEuLVrAfCdwWloFnjknW8Be6l/GpFQnhHnI6h3aAgceIsv?= =?us-ascii?Q?E22RJ3XOrX9nlTqXOxe5CszsqIx/btmeGKe8ygcwh3fBalvy056zInRriOyo?= =?us-ascii?Q?V6nbKNefzwdJLC0dSSxLLRBT?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: bdc5a41d-5716-4cef-af17-08d96d640483 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2021 16:17:39.1440 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Rtl3pIxwWwZkgugPt3mQh6wl/6I5FCWOivAZT6Le4JPSj0njbQCp58ODF/klDnYGMxxbA2wrNeUXxQel1xGKLg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4415 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Michael Roth CPUID instructions are issued during early boot to do things like probe for SEV support. Currently these are handled by a minimal #VC handler that uses the MSR-based GHCB protocol to fetch the CPUID values from the hypervisor. When SEV-SNP is enabled, use the firmware-validated CPUID values from the CPUID page instead [1]. [1]: SEV SNP Firmware ABI Specification, Rev. 0.8, 8.13.2.6 Cc: Michael Roth Cc: James Bottomley Cc: Min Xu Cc: Jiewen Yao Cc: Tom Lendacky Cc: Jordan Justen Cc: Ard Biesheuvel Cc: Erdem Aktas Signed-off-by: Michael Roth Signed-off-by: Brijesh Singh --- OvmfPkg/ResetVector/Ia32/AmdSev.asm | 80 +++++++++++++++++++++++++++-- 1 file changed, 75 insertions(+), 5 deletions(-) diff --git a/OvmfPkg/ResetVector/Ia32/AmdSev.asm b/OvmfPkg/ResetVector/Ia32= /AmdSev.asm index 2386b15c0ce0..3ce3dd2785cb 100644 --- a/OvmfPkg/ResetVector/Ia32/AmdSev.asm +++ b/OvmfPkg/ResetVector/Ia32/AmdSev.asm @@ -36,6 +36,18 @@ BITS 32 %define GHCB_CPUID_REGISTER_SHIFT 30 %define CPUID_INSN_LEN 2 =20 +; #VC handler offsets/sizes for accessing SNP CPUID page +; +%define SNP_CPUID_ENTRY_SZ 48 +%define SNP_CPUID_COUNT 0 +%define SNP_CPUID_ENTRY 16 +%define SNP_CPUID_ENTRY_EAX_IN 0 +%define SNP_CPUID_ENTRY_ECX_IN 4 +%define SNP_CPUID_ENTRY_EAX 24 +%define SNP_CPUID_ENTRY_EBX 28 +%define SNP_CPUID_ENTRY_ECX 32 +%define SNP_CPUID_ENTRY_EDX 36 + =20 %define SEV_GHCB_MSR 0xc0010130 %define SEV_STATUS_MSR 0xc0010131 @@ -545,11 +557,61 @@ SevEsIdtNotCpuid: TerminateVmgExit TERM_VC_NOT_CPUID iret =20 - ; - ; Total stack usage for the #VC handler is 44 bytes: - ; - 12 bytes for the exception IRET (after popping error code) - ; - 32 bytes for the local variables. - ; +; Use the SNP CPUID page to handle the cpuid lookup +; +; Modified: EAX, EBX, ECX, EDX +; +; Relies on the stack setup/usage in #VC handler: +; +; On entry, +; [esp + VC_CPUID_FUNCTION] contains EAX input to cpuid instruction +; +; On return, stores corresponding results of CPUID lookup in: +; [esp + VC_CPUID_RESULT_EAX] +; [esp + VC_CPUID_RESULT_EBX] +; [esp + VC_CPUID_RESULT_ECX] +; [esp + VC_CPUID_RESULT_EDX] +; +SnpCpuidLookup: + mov eax, [esp + VC_CPUID_FUNCTION] + mov ebx, [SNP_CPUID_BASE + SNP_CPUID_COUNT] + mov ecx, SNP_CPUID_BASE + SNP_CPUID_ENTRY + ; Zero these out now so we can simply return if lookup fails + mov dword[esp + VC_CPUID_RESULT_EAX], 0 + mov dword[esp + VC_CPUID_RESULT_EBX], 0 + mov dword[esp + VC_CPUID_RESULT_ECX], 0 + mov dword[esp + VC_CPUID_RESULT_EDX], 0 + +SnpCpuidCheckEntry: + cmp ebx, 0 + je VmmDoneSnpCpuid + cmp dword[ecx + SNP_CPUID_ENTRY_EAX_IN], eax + jne SnpCpuidCheckEntryNext + ; As with SEV-ES handler we assume requested CPUID sub-leaf/index is 0 + cmp dword[ecx + SNP_CPUID_ENTRY_ECX_IN], 0 + je SnpCpuidEntryFound + +SnpCpuidCheckEntryNext: + dec ebx + add ecx, SNP_CPUID_ENTRY_SZ + jmp SnpCpuidCheckEntry + +SnpCpuidEntryFound: + mov eax, [ecx + SNP_CPUID_ENTRY_EAX] + mov [esp + VC_CPUID_RESULT_EAX], eax + mov eax, [ecx + SNP_CPUID_ENTRY_EBX] + mov [esp + VC_CPUID_RESULT_EBX], eax + mov eax, [ecx + SNP_CPUID_ENTRY_EDX] + mov [esp + VC_CPUID_RESULT_ECX], eax + mov eax, [ecx + SNP_CPUID_ENTRY_ECX] + mov [esp + VC_CPUID_RESULT_EDX], eax + jmp VmmDoneSnpCpuid + +; +; Total stack usage for the #VC handler is 44 bytes: +; - 12 bytes for the exception IRET (after popping error code) +; - 32 bytes for the local variables. +; SevEsIdtVmmComm: ; ; If we're here, then we are an SEV-ES guest and this @@ -577,6 +639,13 @@ SevEsIdtVmmComm: ; Save the CPUID function being requested mov [esp + VC_CPUID_FUNCTION], eax =20 + ; If SEV-SNP is enabled, use the CPUID page to handle the CPUID + ; instruction. + mov ecx, SEV_STATUS_MSR + rdmsr + bt eax, 2 + jc SnpCpuidLookup + ; The GHCB CPUID protocol uses the following mapping to request ; a specific register: ; 0 =3D> EAX, 1 =3D> EBX, 2 =3D> ECX, 3 =3D> EDX @@ -634,6 +703,7 @@ VmmDone: mov ecx, SEV_GHCB_MSR wrmsr =20 +VmmDoneSnpCpuid: mov eax, [esp + VC_CPUID_RESULT_EAX] mov ebx, [esp + VC_CPUID_RESULT_EBX] mov ecx, [esp + VC_CPUID_RESULT_ECX] --=20 2.17.1