From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) by mx.groups.io with SMTP id smtpd.web08.13751.1631116431786605770 for ; Wed, 08 Sep 2021 08:53:52 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=qBH4aos9; spf=pass (domain: nuviainc.com, ip: 209.85.221.42, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f42.google.com with SMTP id v10so4037267wrd.4 for ; Wed, 08 Sep 2021 08:53:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=Ur17tkKToz4cYAlerixIfqITZsH2Y/Ov2rPwaWIgJME=; b=qBH4aos9lzmrv2W3Hb/ADobLPnvI+Zm4jv2flN6HaGX6Blxtx5a5S0AksAFsKwEyu3 5DFylTPNCYDvql8qMwzJzKJiXcdiM6VTNGnR5D/6uqvKnFY2IiwFhYfDFuz2dmjNuKfi AT6dajwK1y/3Dm/Vpq12YAQet5DHp6zDSfgO6d+CbW2wjOa4u8QaTi2O0B96LuaT7TQN la5nPgtxat+brWcUgnDscU64jemNHBUM3bBTtoh/sf4ol05amxi1EG0eF9BtD1AsCsZ3 50skea8rbUhcn8nXrJilNnsiDZ7TmFj0Tmrgh8hV3wt3ZT2sQFaQnV7smLXHbjIPRjay BkLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=Ur17tkKToz4cYAlerixIfqITZsH2Y/Ov2rPwaWIgJME=; b=6ysVGCt0PjjPL/fkP+Hwf0sFlZ1vkHFUQaT32LvnqlTbZRd35zbfi+BF9KNxTjZA7u 7wBNCNbn7h1P4dR3RjHX7bxe/XnYLSrjNCvC8i4h4JBdqjFmF3V6Yv/r3KKHUJFNjFeF DgVtXIA+o2PuWlNRBsNTOxPjbnt0BYZnLLmeiqmFqM4gHhl1CJaJT7NRsLvVdluwfL8M GMvP2LNwO8aFGrsgj4jmrMMsePrdmJ/mYnLHSZHgvHeYMyStLeIa9r2Yo8EmpPkSiwlC ug5UMks0pF4R5l343gQKm5mkUxhMnqlFN4rAr22q4HhGTsw3CszvcSdsGXkVp+BrJcTJ 6vGQ== X-Gm-Message-State: AOAM5308YIWIOKSuV4ZL9PDkfoBUUKsmN2wxZwy/V0M8Uzd+eWpakUBZ kwLYdYfn/DQl1nX5UDjkAFTBsKXlhqkDB5mgBc3wa9SQioACoQKIqz6tloaWcs1eJRMs7t5lfi4 3xSJwXlccmktQJlbs0tYV7YLpx/9glDXuaZp4uc43d6KStmcZ5tSEbUzOQtmxbzCphHgV X-Google-Smtp-Source: ABdhPJwoN9tSoIM9s8bVC6mrDzHgZNeK9moLflF/bX6b5DvlTkk7VXJZvspDrF1L/r1h5HyoQy5h6A== X-Received: by 2002:adf:fd8c:: with SMTP id d12mr4932907wrr.21.1631116429889; Wed, 08 Sep 2021 08:53:49 -0700 (PDT) Return-Path: Received: from leviathan (cpc92314-cmbg19-2-0-cust559.5-4.cable.virginm.net. [82.11.186.48]) by smtp.gmail.com with ESMTPSA id h8sm2411370wmb.35.2021.09.08.08.53.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Sep 2021 08:53:49 -0700 (PDT) Date: Wed, 8 Sep 2021 16:53:47 +0100 From: "Leif Lindholm" To: devel@edk2.groups.io, abner.chang@hpe.com Cc: 'Gerd Hoffmann' , "Yao, Jiewen" , gaoliming , 'Ard Biesheuvel' , "Kinney, Michael D" , "Ni, Ray" , "Schaefer, Daniel" , 'Sunil V L' , 'Ard Biesheuvel' Subject: Re: [edk2-devel] [RFC] RISC-V QEMU virtual package Message-ID: <20210908155347.uw3y5hpslybojile@leviathan> References: <005f01d7a2bb$6d8e5ef0$48ab1cd0$@byosoft.com.cn> <20210907172229.geh4zcz7pvxoyyj6@leviathan> <20210908133705.kc4unk3nizradc4j@sirius.home.kraxel.org> MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Sep 08, 2021 at 15:33:34 +0000, Abner Chang wrote: > > > I prefer to have RISC-V instance because I > > > am not sure if any fw_cfg interface changes would be made on RISC-V > > > QEMU. > > > > The fw_cfg interface should not diverge. ia32/x64 works a bit different > > because there is a separate io address space on that architecture and > > fw_cfg uses that for historical reasons. All platforms using the mmio > > variant of the fw_cfg interface should work alike though. > > Hmm, ok. > We can have the common one for both ARM and RISC-V if there is no > potential issues in the future as you mentioned. We can also add > #defined (MDE_CPU_RISCV64) to avoid the build error as ARM and > RISC-V share the same code. Well, if it's a single file, we can easily make sure it doesn't break. And we help improving the code quality. It's very easy for code that gets shoved into architecture-specific subtrees to start growing architecture-specific statements that don't actually describe anything architecture-specific - because that sets the stage for how the code is interpreted. > One more question, there is already a QemuFwCfgLib library for > ia32/x64. The naming of QemuFwCfgCommonLib under Library seems > confusing. How about we put this library under /FDT and also name > it as QemuFwCfgLib? Because ARM/RISC-V fw_cfg also depends on FDT. I mean, I would more prefer to rename the x86 one, since that one becomes the special case. Dependency isn't what should dictate hierarchy. The FwCfg interface is about a lot more than FDT. / Leif