* [PATCH v5 00/10] Added support for FT2000/4 chip
@ 2021-09-09 9:47 Ling Jia
2021-09-09 9:47 ` [PATCH v5 01/10] Silicon/Phytium: Added PlatformLib to FT2000/4 Ling Jia
` (5 more replies)
0 siblings, 6 replies; 7+ messages in thread
From: Ling Jia @ 2021-09-09 9:47 UTC (permalink / raw)
To: devel; +Cc: Leif Lindholm, Ling Jia
This series added packages to support FT2000/4 chip.
Platform/Phytium: Added DurianPkg, include DurianPkg.dsc and DurianPkg.fdf.
Silicon/Phytium: Added FT2000-4Pkg and PhytiumCommonPkg.
The modules could be runed at the silicon of FT2000/4.
They supported Acpi parameter configuration, Pci bus scaning,
flash read-write and erase abd operating system boot function.
Maintainers.txt: Added maintainers and reviewers for the DurianPkg.
The public git repository is :
https://github.com/jialing2020/edk2-platforms/tree/Phytium_Opensource_For_FT2000-4_v5
About patch 7:
This is a set of special communication protocol for
ft2000/4 chip QSPI controller. It has twoaccess modes:
direct address access and command port access.
At present, the read and write operations of flash
are completed through direct address access
(address mapping has been done on the hardware,
and the write access is configured to put the data
into the buffer first and merge and write multiple times).
The erase operation is completed through command port access.
Every time you operate norflash, you need to configure the
command code, command format and other information through
the command port register (such as erasing 0xd8), if the
command requires an address, fill in the address port register;
if the command requires data, access it in the order of high-
order data register and low-order data register.
Once the low-order data register is accessed, trigger
the controller to send a command to flash.
Ling Jia (10):
Silicon/Phytium: Added PlatformLib to FT2000/4
Silicon/Phytium: Added Acpi support to FT2000/4
Silicon/Phytium: Added SMBIOS support to FT2000/4
Silicon/Phytium: Added PciSegmentLib to FT2000/4
Silicon/Phytium: Added PciHostBridgeLib to FT2000/4
Silicon/Phytium: Added Spi driver support to FT2000/4
Silicon/Phytium: Added flash driver support to Phytium Silicon
Silicon/Phytium: Added fvb driver for norflash
Silicon/Phytium: Added Rtc driver to FT2000/4
Maintainers.txt: Added maintainers and reviewers for the DurianPkg
Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec | 52 +
Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc | 345 +++++
Platform/Phytium/DurianPkg/DurianPkg.dsc | 331 +++++
Platform/Phytium/DurianPkg/DurianPkg.fdf | 235 ++++
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf | 56 +
Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 47 +
Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf | 44 +
Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf | 48 +
Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 47 +
Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf | 28 +
Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.inf | 55 +
Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.inf | 39 +
Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 53 +
Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf | 61 +
Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h | 59 +
Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h | 95 ++
Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.h | 24 +
Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h | 104 ++
Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h | 80 ++
Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol.h | 74 +
Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiProtocol.h | 51 +
Silicon/Phytium/PhytiumCommonPkg/Include/SystemServiceInterface.h | 112 ++
Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 943 +++++++++++++
Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c | 202 +++
Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c | 412 ++++++
Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 181 +++
Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c | 1434 ++++++++++++++++++++
Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.c | 137 ++
Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLibMem.c | 156 +++
Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.c | 462 +++++++
Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 250 ++++
Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c | 1304 ++++++++++++++++++
Maintainers.txt | 8 +
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl | 209 +++
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc | 80 ++
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl | 85 ++
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl | 15 +
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl | 65 +
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc | 77 ++
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc | 83 ++
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc | 89 ++
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc | 67 +
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc | 65 +
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc | 219 +++
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc | 73 +
Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/AArch64/PhytiumPlatformHelper.S | 76 ++
Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc | 119 ++
47 files changed, 8851 insertions(+)
create mode 100644 Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
create mode 100644 Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc
create mode 100644 Platform/Phytium/DurianPkg/DurianPkg.dsc
create mode 100644 Platform/Phytium/DurianPkg/DurianPkg.fdf
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.inf
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.inf
create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.h
create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h
create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h
create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol.h
create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiProtocol.h
create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Include/SystemServiceInterface.h
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.c
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLibMem.c
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.c
create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform.c
create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc
create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/AArch64/PhytiumPlatformHelper.S
create mode 100644 Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc
--
2.25.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v5 01/10] Silicon/Phytium: Added PlatformLib to FT2000/4
2021-09-09 9:47 [PATCH v5 00/10] Added support for FT2000/4 chip Ling Jia
@ 2021-09-09 9:47 ` Ling Jia
2021-09-09 9:47 ` [PATCH v5 02/10] Silicon/Phytium: Added Acpi support " Ling Jia
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Ling Jia @ 2021-09-09 9:47 UTC (permalink / raw)
To: devel; +Cc: Leif Lindholm, Ling Jia
The PlatformLib supported the system library for FT2000/4 chip.
Platform/Phytium: Added the dsc and fdf files of DurianPkg.
Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec | 41 +++
Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc | 345 ++++++++++++++++++++
Platform/Phytium/DurianPkg/DurianPkg.dsc | 298 +++++++++++++++++
Platform/Phytium/DurianPkg/DurianPkg.fdf | 210 ++++++++++++
Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.inf | 55 ++++
Silicon/Phytium/PhytiumCommonPkg/Include/SystemServiceInterface.h | 112 +++++++
Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.c | 137 ++++++++
Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLibMem.c | 156 +++++++++
Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/AArch64/PhytiumPlatformHelper.S | 76 +++++
Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc | 119 +++++++
10 files changed, 1549 insertions(+)
diff --git a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
new file mode 100644
index 0000000000..48f430c88d
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
@@ -0,0 +1,41 @@
+## @file
+# This package provides common Phytium silicon modules.
+#
+# Copyright (C) 2020, Phytium Technology Co,Ltd. All rights reserved.
+#
+# SPDX-License-Identifier:BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001b
+ PACKAGE_NAME = PhytiumCommnonPkg
+ PACKAGE_GUID = b34af0b4-3e7c-11eb-a9d0-0738806d2dec
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes]
+ Include # Root include for the package
+
+[Guids.common]
+ gPhytiumPlatformTokenSpaceGuid = { 0x8c3abed4, 0x1fc8, 0x46d3, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xde, 0x76 } }
+
+[PcdsFixedAtBuild.common]
+ gPhytiumPlatformTokenSpaceGuid.PcdSystemIoBase|0x0|UINT64|0x00000000
+ gPhytiumPlatformTokenSpaceGuid.PcdSystemIoSize|0x0|UINT64|0x00000001
+
+ #
+ # PCI configuration address space
+ #
+ gPhytiumPlatformTokenSpaceGuid.PcdPciConfigBase|0x0|UINT64|0x00000002
+ gPhytiumPlatformTokenSpaceGuid.PcdPciConfigSize|0x0|UINT64|0x00000003
+
+[Protocols]
diff --git a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc
new file mode 100644
index 0000000000..121fe0e7c5
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc
@@ -0,0 +1,345 @@
+## @file
+# This package provides common open source Phytium silicon modules.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
+#
+# SPDX-License-Identifier:BSD-2-Clause-Patent
+#
+##
+
+
+[LibraryClasses.common]
+ #
+ # ARM Architectural Libraries
+ #
+ ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+ ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+ ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+ ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+ ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+ ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+
+ AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
+ AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+ BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+ BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.inf
+
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+ CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+ !if $(TARGET) == RELEASE
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+ !else
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ !endif
+
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+ DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
+
+ OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
+
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+ PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+ PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecureLibNull.inf
+ PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+
+ RngLib|MdePkg/Library/BaseRngLibTimerLib/BaseRngLibTimerLib.inf
+ ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
+
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
+
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+ TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+
+ VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+ VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf
+
+ #
+ # Scsi Requirements
+ #
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+
+ #
+ # USB Requirements
+ #
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+ #
+ # Networking Requirements
+ #
+ DpcLib|NetworkPkg/Library/DxeDpcLib/DxeDpcLib.inf
+ IpIoLib|NetworkPkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+ NetLib|NetworkPkg/Library/DxeNetLib/DxeNetLib.inf
+ UdpIoLib|NetworkPkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+ HttpLib|NetworkPkg/Library/DxeHttpLib/DxeHttpLib.inf
+
+[LibraryClasses.common.SEC]
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
+ DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
+ ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+ LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+ HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+ PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+ PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+
+[LibraryClasses.common.SEC, LibraryClasses.common.PEIM]
+ MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLib.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+ #
+ # UiApp dependencies
+ #
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ !if $(SECURE_BOOT_ENABLE) == TRUE
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
+ !endif
+
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+
+ !if $(TARGET) != RELEASE
+ DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf
+ !endif
+
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
+ VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLibRuntimeDxe.inf
+
+[LibraryClasses.AARCH64.DXE_RUNTIME_DRIVER]
+ EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf
+
+[LibraryClasses.ARM, LibraryClasses.AARCH64]
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+ #
+ # Add support for GCC stack protector
+ #
+ NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVER]
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+
+[BuildOptions]
+ RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+
+[BuildOptions.AARCH64.EDKII.DXE_RUNTIME_DRIVER]
+ GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+ gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
+
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+ # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+ gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+
+ gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultLangDeprecate|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE
+
+[PcdsFixedAtBuild.common]
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+ gEfiNetworkPkgTokenSpaceGuid.PcdAllowHttpConnections|TRUE
+
+!if $(TARGET) == RELEASE
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+!endif
+
+ # DEBUG_INIT 0x00000001 // Initialization
+ # DEBUG_WARN 0x00000002 // Warnings
+ # DEBUG_LOAD 0x00000004 // Load events
+ # DEBUG_FS 0x00000008 // EFI File system
+ # DEBUG_POOL 0x00000010 // Alloc & Free's
+ # DEBUG_PAGE 0x00000020 // Alloc & Free's
+ # DEBUG_INFO 0x00000040 // Verbose
+ # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers
+ # DEBUG_VARIABLE 0x00000100 // Variable
+ # DEBUG_BM 0x00000400 // Boot Manager
+ # DEBUG_BLKIO 0x00001000 // BlkIo Driver
+ # DEBUG_NET 0x00004000 // SNI Driver
+ # DEBUG_UNDI 0x00010000 // UNDI Driver
+ # DEBUG_LOADFILE 0x00020000 // UNDI Driver
+ # DEBUG_EVENT 0x00080000 // Event messages
+ # DEBUG_GCD 0x00100000 // Global Coherency Database changes
+ # DEBUG_CACHE 0x00200000 // Memory range cachability changes
+ # DEBUG_ERROR 0x80000000 // Error
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|200000
+
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|65
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04
+ gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04
+ gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04
+!endif
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000
+!else
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x4000
+!endif
+
+ # Default platform supported RFC 4646 languages: English & French & Chinese Simplified.
+ # Default Value of PlatformLangCodes Variable.
+ gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US;zh-Hans"
+
+ # Default current RFC 4646 language: Chinese Simplified.
+ # Default Value of PlatformLang Variable.
+ gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLang|"en-US"
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+
+ #
+ # ACPI Table Version
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
+
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt|67
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
+
+[PcdsDynamicDefault.common.DEFAULT]
+ ## This PCD defines the video horizontal resolution.
+ # This PCD could be set to 0 then video resolution could be at highest resolution.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|640
+ ## This PCD defines the video vertical resolution.
+ # This PCD could be set to 0 then video resolution could be at highest resolution.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|480
+
+ ## This PCD defines the Console output row and the default value is 80 according to UEFI spec.
+ # This PCD could be set to 0 then console output could be at max column and max row.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|128
+ ## This PCD defines the Console output column and the default value is 25 according to UEFI spec.
+ # This PCD could be set to 0 then console output could be at max column and max row.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|40
+
+ ## Specify the video horizontal resolution of text setup.
+ # @Prompt Video Horizontal Resolution of Text Setup
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
+
+ ## Specify the video vertical resolution of text setup.
+ # @Prompt Video Vertical Resolution of Text Setup
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
+
+ ## Specify the console output column of text setup.
+ # @Prompt Console Output Column of Text Setup
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|128
+ ## Specify the console output row of text setup.
+ # @Prompt Console Output Row of Text Setup
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|40
+
+ ## The number of seconds that the firmware will wait before initiating the original default boot selection.
+ # A value of 0 indicates that the default boot selection is to be initiated immediately on boot.
+ # The value of 0xFFFF then firmware will wait for user input before booting.
+ # @Prompt Boot Timeout (s)
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|5
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/DurianPkg/DurianPkg.dsc
new file mode 100644
index 0000000000..b523ecd658
--- /dev/null
+++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc
@@ -0,0 +1,298 @@
+## @file
+# This package provides common open source Phytium Platform modules.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
+#
+# SPDX-License-Identifier:BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = DurianPkg
+ PLATFORM_GUID = 8f7ac876-3e7c-11eb-86cb-33f68535d613
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001001c
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+ SUPPORTED_ARCHITECTURES = AARCH64
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Platform/Phytium/DurianPkg/DurianPkg.fdf
+
+!include Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc
+
+[LibraryClasses.common]
+ # Phytium Platform library
+ ArmPlatformLib|Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.inf
+
+ # PL011 UART Driver and Dependency Libraries
+ SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+ PL011UartClockLib|ArmPlatformPkg/Library/PL011UartClockLib/PL011UartClockLib.inf
+ PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFixedAtBuild.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"Durian Platform"
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"V1.0"
+
+ gArmTokenSpaceGuid.PcdVFPEnabled|1
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0x101
+ gArmTokenSpaceGuid.PcdArmPrimaryCore|0x0
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|4
+
+ #
+ # NV Storage PCDs.
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0xe00000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0xe10000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0xe20000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
+
+ # Size of the region used by UEFI in permanent memory (Reserved 64MB)
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000
+
+ #
+ # PL011 - Serial Terminal
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x28001000
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
+ gArmPlatformTokenSpaceGuid.PL011UartClkInHz|48000000
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+
+ #
+ # ARM General Interrupt Controller
+ #
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x29900000
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x29980000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x29c00000
+
+ # System IO space
+ gPhytiumPlatformTokenSpaceGuid.PcdSystemIoBase|0x0
+ gPhytiumPlatformTokenSpaceGuid.PcdSystemIoSize|0x40000000
+
+ #
+ # System Memory (2GB ~ 4GB - 64MB), the top 64MB is reserved for
+ # PBF(the processor basic firmware, Mainly deals the initialization
+ # of the chip).
+ #
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x7B000000
+
+ # Stack Size
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000
+
+ #
+ # Designware PCI Root Complex
+ #
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x40000000
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|28
+ gPhytiumPlatformTokenSpaceGuid.PcdPciConfigBase|0x40000000
+ gPhytiumPlatformTokenSpaceGuid.PcdPciConfigSize|0x10000000
+ gArmTokenSpaceGuid.PcdPciBusMin|0
+ gArmTokenSpaceGuid.PcdPciBusMax|255
+ gArmTokenSpaceGuid.PcdPciIoBase|0x00000
+ gArmTokenSpaceGuid.PcdPciIoSize|0xf00000
+ gArmTokenSpaceGuid.PcdPciIoTranslation|0x50000000
+ gArmTokenSpaceGuid.PcdPciMmio32Base|0x58000000
+ gArmTokenSpaceGuid.PcdPciMmio32Size|0x28000000
+ gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0
+ gArmTokenSpaceGuid.PcdPciMmio64Base|0x1000000000
+ gArmTokenSpaceGuid.PcdPciMmio64Size|0x1000000000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ #
+ # PCD database
+ #
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+ OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
+ }
+
+ ArmPlatformPkg/PrePi/PeiMPCore.inf {
+ <LibraryClasses>
+ ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+ }
+
+ #
+ # Dxe core entry
+ #
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
+
+ #
+ # DXE driver
+ #
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+ }
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+ #
+ # Common Arm Timer and Gic Components
+ #
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+ #
+ # security system
+ #
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {
+ <LibraryClasses>
+ NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf
+ }
+
+ #
+ # network, mod for https boot.
+ #
+ NetworkPkg/SnpDxe/SnpDxe.inf
+ NetworkPkg/DpcDxe/DpcDxe.inf
+ NetworkPkg/MnpDxe/MnpDxe.inf
+ NetworkPkg/ArpDxe/ArpDxe.inf
+ NetworkPkg/Dhcp4Dxe/Dhcp4Dxe.inf
+ NetworkPkg/Ip4Dxe/Ip4Dxe.inf
+ NetworkPkg/Mtftp4Dxe/Mtftp4Dxe.inf
+ NetworkPkg/Udp4Dxe/Udp4Dxe.inf
+ NetworkPkg/VlanConfigDxe/VlanConfigDxe.inf
+
+ NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+ NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+ NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+ NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+ NetworkPkg/TcpDxe/TcpDxe.inf
+
+ NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+
+ NetworkPkg/DnsDxe/DnsDxe.inf
+ NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
+ NetworkPkg/HttpDxe/HttpDxe.inf
+
+ #
+ # FV Filesystem
+ #
+ MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
+
+ #
+ # Common Console Components
+ # ConIn,ConOut,StdErr
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
+
+ #
+ # Hii database init
+ #
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ FatPkg/EnhancedFatDxe/Fat.inf
+
+ #
+ # Generic Watchdog Timer
+ #
+ ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+
+ #
+ # Usb Support
+ #
+ MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ #
+ # IDE/AHCI Support
+ #
+ MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+
+ #
+ # PCI Support
+ #
+ ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
+ #
+ # The following 2 module perform the same work except one operate variable.
+ # Only one of both should be put into fdf.
+ #
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+
+ #
+ # NVME Support
+ #
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+
+ #
+ # Bds
+ #
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ MdeModulePkg/Universal/DriverSampleDxe/DriverSampleDxe.inf
+ MdeModulePkg/Application/UiApp/UiApp.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+ }
+ MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf
+
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/DurianPkg/DurianPkg.fdf
new file mode 100644
index 0000000000..9d75b072c6
--- /dev/null
+++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf
@@ -0,0 +1,210 @@
+## @file
+# This package provides common open source Phytium Platform modules.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
+#
+# SPDX-License-Identifier:BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.PHYTIUM]
+BaseAddress = 0x88000000|gArmTokenSpaceGuid.PcdFdBaseAddress
+Size = 0x01000000|gArmTokenSpaceGuid.PcdFdSize
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize = 0x10000
+NumBlocks = 0x100
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x200000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize = 0x40
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 16 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ APRIORI DXE {
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+ }
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+
+ #
+ # Variable services
+ #
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # SATA Controller
+ #
+ INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+ INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+ INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+
+ #
+ # NVMe boot devices
+ #
+ INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ #
+ # Usb Support
+ #
+ INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ #
+ # NetWork
+ #
+ INF NetworkPkg/SnpDxe/SnpDxe.inf
+ INF NetworkPkg/DpcDxe/DpcDxe.inf
+ INF NetworkPkg/MnpDxe/MnpDxe.inf
+ INF NetworkPkg/ArpDxe/ArpDxe.inf
+ INF NetworkPkg/Dhcp4Dxe/Dhcp4Dxe.inf
+ INF NetworkPkg/Ip4Dxe/Ip4Dxe.inf
+ INF NetworkPkg/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF NetworkPkg/Udp4Dxe/Udp4Dxe.inf
+ INF NetworkPkg/VlanConfigDxe/VlanConfigDxe.inf
+
+ #
+ # UEFI applications
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/DriverSampleDxe/DriverSampleDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePi/PeiMPCore.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+!include Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.inf b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.inf
new file mode 100644
index 0000000000..40c070767a
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.inf
@@ -0,0 +1,55 @@
+#/** @file
+# Library for Phytium Platform.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PlatformLib
+ FILE_GUID = fac08f56-40fe-11eb-a2a3-27b46864b1f3
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
+
+[LibraryClasses]
+ ArmSmcLib
+ HobLib
+
+[Sources.common]
+ PlatformLib.c
+ PlatformLibMem.c
+
+[Sources.AARCH64]
+ AArch64/PhytiumPlatformHelper.S
+
+[Guids]
+
+[FixedPcd]
+ gPhytiumPlatformTokenSpaceGuid.PcdSystemIoBase
+ gPhytiumPlatformTokenSpaceGuid.PcdSystemIoSize
+ gPhytiumPlatformTokenSpaceGuid.PcdPciConfigBase
+ gPhytiumPlatformTokenSpaceGuid.PcdPciConfigSize
+ gArmTokenSpaceGuid.PcdPciBusMin
+ gArmTokenSpaceGuid.PcdPciBusMax
+ gArmTokenSpaceGuid.PcdPciIoBase
+ gArmTokenSpaceGuid.PcdPciIoSize
+ gArmTokenSpaceGuid.PcdPciIoTranslation
+ gArmTokenSpaceGuid.PcdPciMmio32Base
+ gArmTokenSpaceGuid.PcdPciMmio32Size
+ gArmTokenSpaceGuid.PcdPciMmio32Translation
+ gArmTokenSpaceGuid.PcdPciMmio64Base
+ gArmTokenSpaceGuid.PcdPciMmio64Size
+
+[Pcd]
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
diff --git a/Silicon/Phytium/PhytiumCommonPkg/Include/SystemServiceInterface.h b/Silicon/Phytium/PhytiumCommonPkg/Include/SystemServiceInterface.h
new file mode 100644
index 0000000000..2661b305ba
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/Include/SystemServiceInterface.h
@@ -0,0 +1,112 @@
+/** @file
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SYSTEM_SERVICE_INTERFACE_H_
+#define SYSTEM_SERVICE_INTERFACE_H_
+
+/* SMC function IDs for OEM Service queries */
+#define PHYTIUM_OEM_SVC_PSSI_VERSION 0x8200ff03
+#define PHYTIUM_OEM_SVC_PBF_VERSION 0x82000001
+#define PHYTIUM_OEM_SVC_CPU_VERSION 0xc2000002
+#define PHYTIUM_OEM_SVC_CPU_MAPS 0xc2000003
+#define PHYTIUM_OEM_SVC_CPU_CONF 0xc2000004
+#define PHYTIUM_OEM_SVC_MEM_REGIONS 0xc2000005
+#define PHYTIUM_OEM_SVC_MCU_DIMMS 0xc2000006
+#define PHYTIUM_OEM_SVC_PCI_CONTROLLER 0xc2000007
+#define PHYTIUM_OEM_SVC_HOST_BRIDGE 0xc2000008
+#define PHYTIUM_OEM_SVC_GET_FLASH_CMD 0xC200000C
+
+#define PHYTIUM_IOBASE_MASK 0xfffffff
+#define PHYTIUM_MEMIO32_MASK 0xffffffff
+#define PHYTIUM_MEMIO64_MASK 0xffffffffff
+
+#pragma pack(1)
+
+typedef struct {
+ UINT64 CpuMapCount;
+ UINT64 CpuMap[1];
+} PHYTIUM_CPU_MAP_INFO;
+
+
+typedef struct {
+ UINT64 CpuFreq; // Hz
+ UINT64 CpuL3CacheSize; // Byte
+ UINT64 CpuL3CacheLineSize; // Byte
+} PHYTIUM_CPU_CORE_INFO;
+
+typedef struct {
+ UINT64 CupVersion; //cpu version
+ PHYTIUM_CPU_CORE_INFO CpuCoreInfo; //cpu core info
+ PHYTIUM_CPU_MAP_INFO CpuMapInfo; //cpu map info
+} PHYTIUM_CPU_INFO;
+
+typedef struct {
+ UINT64 MemSize; // MB
+ UINT64 MemDramId;
+ UINT64 MemModuleId;
+ UINT64 MemSerial;
+ UINT64 MemSlotNumber;
+ UINT64 MemFeatures;
+} PHYTIUM_MCU_DIMM;
+
+#define MCU_DIMM_MAXCOUNT 2
+
+typedef struct {
+ UINT64 MemFreq; // MHz
+ UINT64 MemDimmCount;
+ PHYTIUM_MCU_DIMM McuDimm[1];
+} PHYTIUM_MCU_DIMMS;
+
+typedef struct {
+ UINT64 MemStart;
+ UINT64 MemSize;
+ UINT64 MemNodeId;
+} PHYTIUM_MEMORY_BLOCK;
+
+typedef struct {
+ UINT64 MemBlockCount;
+ PHYTIUM_MEMORY_BLOCK MemBlock[1];
+} PHYTIUM_MEMORY_INFO;
+
+typedef struct {
+ UINT8 PciLane;
+ UINT8 PciSpeed;
+ UINT8 Reserved[6];
+} PHYTIUM_PCI_BLOCK;
+
+typedef struct {
+ UINT64 PciCount;
+ PHYTIUM_PCI_BLOCK PciBlock[1];
+} PHYTIUM_PCI_CONTROLLER;
+
+typedef struct {
+ UINT8 BusStart;
+ UINT8 BusEnd;
+ UINT8 Reserved[6];
+ UINT64 PciConfigBase;
+ UINT64 IoBase;
+ UINT64 IoSize;
+ UINT64 Mem32Base;
+ UINT64 Mem32Size;
+ UINT64 Mem64Base;
+ UINT64 Mem64Size;
+ UINT16 IntA;
+ UINT16 IntB;
+ UINT16 IntC;
+ UINT16 IntD;
+} PHYTIUM_PCI_HOST_BLOCK;
+
+typedef struct {
+ UINT64 PciHostCount;
+ PHYTIUM_PCI_HOST_BLOCK PciHostBlock[1];
+} PHYTIUM_PCI_HOST_BRIDGE;
+
+#pragma pack ()
+
+
+#endif // SYSTEM_SERVICE_INTERFACE_H_
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.c b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.c
new file mode 100644
index 0000000000..6a8d226574
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.c
@@ -0,0 +1,137 @@
+/** @file
+ Library for Phytium platform.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
+ARM_CORE_INFO mPhytiumMpCoreInfoTable[] = {
+ {
+ 0x0, 0x0, // Cluster 0, Core 0
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (UINT64)0xFFFFFFFF
+ }
+};
+
+/*
+ This function geted the current Boot Mode.
+
+ This function returns the boot reason on the platform.
+
+ @return Return the current Boot Mode of the platform.
+
+*/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+
+/**
+ Initialize controllers that must setup in the normal world.
+
+ This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+ in the PEI phase.
+
+ @retval EFI_SUCCESS ArmPlatformInitialize() is executed successfully.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ return RETURN_SUCCESS;
+}
+
+
+/**
+ This function Inited the system (or sometimes called permanent) memory.
+
+ This memory is generally represented by the DRAM.
+
+ @param[in] None.
+
+ @retval None.
+
+**/
+VOID
+ArmPlatformInitializeSystemMemory (
+ VOID
+ )
+{
+ // Nothing to do here
+}
+
+
+/**
+ This function geted the information of core.
+
+ @param[out] CoreCount The count of CoreInfoTable.
+ @param[out] ArmCoreTable The pointer of CoreInfoTable.
+
+ @retval EFI_SUCCESS PrePeiCoreGetMpCoreInfo() is executed successfully.
+
+**/
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ *CoreCount = PcdGet32 (PcdCoreCount);
+ *ArmCoreTable = mPhytiumMpCoreInfoTable;
+
+ return EFI_SUCCESS;
+}
+
+//
+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is
+// undefined in the contect of PrePeiCore
+//
+EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =
+{
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &mArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+
+/**
+ This function geted the information of Ppitable.
+
+ @param[out] PpiListSize The size of Ppitable.
+ @param[out] PpiList The pointer of Ppitable.
+
+ @retval None.
+
+**/
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ *PpiListSize = sizeof (gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+}
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLibMem.c b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLibMem.c
new file mode 100644
index 0000000000..4f93b24d37
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLibMem.c
@@ -0,0 +1,156 @@
+/** @file
+ Library of memory map for Phytium platform.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/ArmSmcLib.h>
+#include <SystemServiceInterface.h>
+
+// Number of Virtual Memory Map Descriptors
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 32
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+ )
+{
+ ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
+ PHYTIUM_MEMORY_BLOCK *MemBlock;
+ PHYTIUM_MEMORY_INFO *MemInfo;
+ ARM_SMC_ARGS ArmSmcArgs;
+ UINT32 MemBlockCnt;
+ UINT32 Index1;
+ UINT32 Index2;
+
+ MemBlock = NULL;
+ MemInfo = NULL;
+ MemBlockCnt = 0;
+ Index1 = 0;
+ Index2 = 0;
+ CacheAttributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ ASSERT (VirtualMemoryMap != NULL);
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages \
+ (EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * \
+ MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+ if (VirtualMemoryTable == NULL) {
+ return;
+ }
+
+ ResourceAttributes =
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED;
+
+ MemInfo = AllocatePages (1);
+ ASSERT (MemInfo != NULL);
+
+ ArmSmcArgs.Arg0 = PHYTIUM_OEM_SVC_MEM_REGIONS;
+ ArmSmcArgs.Arg1 = (UINTN) MemInfo;
+ ArmSmcArgs.Arg2 = EFI_PAGE_SIZE;
+ ArmCallSmc (&ArmSmcArgs);
+ if (ArmSmcArgs.Arg0 == 0) {
+ MemBlockCnt = MemInfo->MemBlockCount;
+ MemBlock = MemInfo->MemBlock;
+ } else {
+ ASSERT (FALSE);
+ }
+
+ //Soc Io Space
+ VirtualMemoryTable[Index1].PhysicalBase = PcdGet64 (PcdSystemIoBase);
+ VirtualMemoryTable[Index1].VirtualBase = PcdGet64 (PcdSystemIoBase);
+ VirtualMemoryTable[Index1].Length = PcdGet64 (PcdSystemIoSize);
+ VirtualMemoryTable[Index1].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ //
+ // PCI Configuration Space
+ //
+ VirtualMemoryTable[++Index1].PhysicalBase = PcdGet64 (PcdPciConfigBase);
+ VirtualMemoryTable[Index1].VirtualBase = PcdGet64 (PcdPciConfigBase);
+ VirtualMemoryTable[Index1].Length = PcdGet64 (PcdPciConfigSize);
+ VirtualMemoryTable[Index1].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ //
+ // PCI Memory Space
+ //
+ VirtualMemoryTable[++Index1].PhysicalBase = PcdGet64 (PcdPciIoBase) + PcdGet64 (PcdPciIoTranslation);
+ VirtualMemoryTable[Index1].VirtualBase = PcdGet64 (PcdPciIoBase) + PcdGet64 (PcdPciIoTranslation);
+ VirtualMemoryTable[Index1].Length = PcdGet64 (PcdPciIoSize);
+ VirtualMemoryTable[Index1].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ //
+ // PCI Memory Space
+ //
+ VirtualMemoryTable[++Index1].PhysicalBase = PcdGet32 (PcdPciMmio32Base);
+ VirtualMemoryTable[Index1].VirtualBase = PcdGet32 (PcdPciMmio32Base);
+ VirtualMemoryTable[Index1].Length = PcdGet32 (PcdPciMmio32Size);
+ VirtualMemoryTable[Index1].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ //
+ // 64-bit PCI Memory Space
+ //
+ VirtualMemoryTable[++Index1].PhysicalBase = PcdGet64 (PcdPciMmio64Base);
+ VirtualMemoryTable[Index1].VirtualBase = PcdGet64 (PcdPciMmio64Base);
+ VirtualMemoryTable[Index1].Length = PcdGet64 (PcdPciMmio64Size);
+ VirtualMemoryTable[Index1].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ //DDR
+ for (Index2 = 0; Index2 < MemBlockCnt; Index2++) {
+ VirtualMemoryTable[++Index1].PhysicalBase = MemBlock->MemStart;
+ VirtualMemoryTable[Index1].VirtualBase = MemBlock->MemStart;
+ VirtualMemoryTable[Index1].Length = MemBlock->MemSize;
+ VirtualMemoryTable[Index1].Attributes = CacheAttributes;
+
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ MemBlock->MemStart,
+ MemBlock->MemSize
+ );
+
+ MemBlock++;
+ }
+
+ // End of Table
+ VirtualMemoryTable[++Index1].PhysicalBase = 0;
+ VirtualMemoryTable[Index1].VirtualBase = 0;
+ VirtualMemoryTable[Index1].Length = 0;
+ VirtualMemoryTable[Index1].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+
+ for (Index2 = 0; Index2 < Index1; Index2++) {
+ DEBUG ((DEBUG_ERROR, "PhysicalBase %12lx VirtualBase %12lx Length %12lx Attributes %12lx\n",\
+ VirtualMemoryTable[Index2].PhysicalBase, VirtualMemoryTable[Index2].VirtualBase, \
+ VirtualMemoryTable[Index2].Length, VirtualMemoryTable[Index2].Attributes));
+ }
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/AArch64/PhytiumPlatformHelper.S b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/AArch64/PhytiumPlatformHelper.S
new file mode 100644
index 0000000000..cce23b7861
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/AArch64/PhytiumPlatformHelper.S
@@ -0,0 +1,76 @@
+#
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLibV8.h>
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <AutoGen.h>
+
+.text
+.align 2
+
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
+
+PrimaryCoreMpid: .word 0x0
+
+
+ASM_PFX(ArmPlatformPeiBootAction):
+ // Save MPIDR_EL1[23:0] in a variable.
+ mov x20, x30
+ bl ASM_PFX(ArmReadMpidr)
+ lsl w0, w0, #8
+ lsr w0, w0, #8
+ ldr x1, =PrimaryCoreMpid
+ str w0, [x1]
+ ret x20
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
+ ldr x0, =PrimaryCoreMpid
+ ldr w0, [x0]
+ ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ASM_PFX(ArmPlatformIsPrimaryCore):
+ mov x20, x30
+ bl ASM_PFX(ArmReadMpidr)
+ lsl w0, w0, #8
+ lsr w0, w0, #8
+ ldr x1, =PrimaryCoreMpid
+ ldr w1, [x1]
+ cmp w0, w1
+ cset x0, eq
+ ret x20
+
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+// With this function: CorePos = (ClusterId * 4) + CoreId
+ASM_PFX(ArmPlatformGetCorePosition):
+ and x1, x0, #ARM_CORE_MASK
+ and x0, x0, #ARM_CLUSTER_MASK
+ add x0, x1, x0, LSR #6
+ ret
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc
new file mode 100644
index 0000000000..641266c601
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc
@@ -0,0 +1,119 @@
+## @file
+# This package provides common open source Phytium silicon modules.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
+#
+# SPDX-License-Identifier:BSD-2-Clause-Patent
+#
+##
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) FIXED {
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) FIXED {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.USER_DEFINED.BIOSINFO]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW BIN Align = 16 $(INF_OUTPUT)/$(MODULE_NAME).acpi
+ }
+
+[Rule.Common.UEFI_APPLICATION.UI]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="Enter Setup"
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ACPI |.acpi
+ RAW ASL |.aml
+ }
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v5 02/10] Silicon/Phytium: Added Acpi support to FT2000/4
2021-09-09 9:47 [PATCH v5 00/10] Added support for FT2000/4 chip Ling Jia
2021-09-09 9:47 ` [PATCH v5 01/10] Silicon/Phytium: Added PlatformLib to FT2000/4 Ling Jia
@ 2021-09-09 9:47 ` Ling Jia
2021-09-09 9:47 ` [PATCH v5 03/10] Silicon/Phytium: Added SMBIOS " Ling Jia
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Ling Jia @ 2021-09-09 9:47 UTC (permalink / raw)
To: devel; +Cc: Leif Lindholm, Ling Jia
Added Acpi driver and table to FT2000/4,
the ACPI Tables providing library AcpiTables.inf uses
a lot of information that is available in the form of PCDs
for differnt platforms.
Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Platform/Phytium/DurianPkg/DurianPkg.dsc | 6 +
Platform/Phytium/DurianPkg/DurianPkg.fdf | 7 +
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf | 56 +++++
Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 53 +++++
Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h | 80 +++++++
Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 250 ++++++++++++++++++++
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl | 209 ++++++++++++++++
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc | 80 +++++++
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl | 85 +++++++
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl | 15 ++
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl | 65 +++++
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc | 77 ++++++
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc | 83 +++++++
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc | 89 +++++++
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc | 67 ++++++
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc | 65 +++++
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc | 219 +++++++++++++++++
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc | 73 ++++++
18 files changed, 1579 insertions(+)
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/DurianPkg/DurianPkg.dsc
index b523ecd658..6f38acb636 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.dsc
+++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc
@@ -279,6 +279,12 @@
#
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+ #
+ # ACPI Support
+ #
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf
+ Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
#
# Bds
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/DurianPkg/DurianPkg.fdf
index 9d75b072c6..f435f7cb51 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.fdf
+++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf
@@ -111,6 +111,13 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ #
+ # ACPI Support
+ #
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ INF RuleOverride=ACPITABLE Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf
+ INF Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
#
# Multiple Console IO support
#
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf
new file mode 100644
index 0000000000..e3fd86f197
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf
@@ -0,0 +1,56 @@
+#/** @file
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = AcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ AcpiSsdtRootPci.asl
+ Dsdt/Dsdt.asl
+ Fadt.aslc
+ Iort.aslc
+ Gtdt.aslc
+ Madt.aslc
+ Mcfg.aslc
+ Pptt.aslc
+ Spcr.aslc
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gArmPlatformTokenSpaceGuid.PL011UartClkInHz
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+ gArmPlatformTokenSpaceGuid.PcdWatchdogCount
diff --git a/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
new file mode 100644
index 0000000000..0f6d46fdba
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
@@ -0,0 +1,53 @@
+#/** @file
+# Sample ACPI Platform Driver.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = AcpiPlatform
+ FILE_GUID = d51068e8-40dc-11eb-9322-1f6d234e9e6e
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = AcpiPlatformEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources]
+ AcpiPlatform.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
+
+[LibraryClasses]
+ BaseMemoryLib
+ DebugLib
+ DxeServicesLib
+ UefiLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Guids]
+
+[Protocols]
+ gEfiAcpiTableProtocolGuid ## CONSUMES
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile ## CONSUMES
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+
+[Depex]
+ gEfiAcpiTableProtocolGuid
diff --git a/Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h b/Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h
new file mode 100644
index 0000000000..e34df30aa0
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h
@@ -0,0 +1,80 @@
+/** @file
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PLATFORM_H_
+#define PLATFORM_H_
+
+#include <IndustryStandard/Acpi.h>
+
+#define EFI_ACPI_6_1_GIC_ITS_INIT(GicITSHwId, GicITSBase) \
+ { \
+ EFI_ACPI_6_1_GIC_ITS, sizeof (EFI_ACPI_6_1_GIC_ITS_STRUCTURE), EFI_ACPI_RESERVED_WORD, \
+ GicITSHwId, GicITSBase, EFI_ACPI_RESERVED_DWORD \
+ }
+
+#define EFI_ACPI_5_1_GICR_STRUCTURE_INIT( \
+ GicRBase, GicRlength) \
+ { \
+ EFI_ACPI_5_1_GICR, sizeof (EFI_ACPI_5_1_GICR_STRUCTURE), EFI_ACPI_RESERVED_WORD, \
+ GicRBase, GicRlength \
+ }
+
+#define EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT( \
+ ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) \
+ { \
+ 3, sizeof (EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE),ProximityDomain , \
+ ACPIProcessorUID, Flags, ClockDomain \
+ }
+
+#define EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT( \
+ ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, Flags) \
+ { \
+ 1, sizeof (EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE),ProximityDomain , EFI_ACPI_RESERVED_WORD, \
+ AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, EFI_ACPI_RESERVED_DWORD, Flags, \
+ EFI_ACPI_RESERVED_QWORD \
+ }
+
+#define EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, PmuIrq, \
+ GicBase, GicVBase, GicHBase, GsivId, GicRBase, ProcessorPowerEfficiencyClass) \
+ { \
+ EFI_ACPI_6_1_GIC, sizeof (EFI_ACPI_6_1_GIC_STRUCTURE), EFI_ACPI_RESERVED_WORD, \
+ GicId, AcpiCpuUid, Flags, 0, PmuIrq, 0, GicBase, GicVBase, GicHBase, \
+ GsivId, GicRBase, Mpidr, ProcessorPowerEfficiencyClass, {0, 0, 0} \
+ }
+
+#define EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, GicDistVector, GicVersion) \
+ { \
+ EFI_ACPI_6_1_GICD, sizeof (EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE), EFI_ACPI_RESERVED_WORD, \
+ GicDistHwId, GicDistBase, GicDistVector, GicVersion, \
+ {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE} \
+ }
+
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_PHYTIUM_OEM_ID 'F','T','-','L','T','D' // OEMID 6 bytes long
+#define EFI_ACPI_PHYTIUM_OEM_TABLE_ID SIGNATURE_64('P','H','Y','T','I','U','M',' ') // OEM table id 8 bytes long
+#define EFI_ACPI_PHYTIUM_OEM_REVISION 0x20201111
+#define EFI_ACPI_PHYTIUM_CREATOR_ID SIGNATURE_32('P','H','Y','T')
+#define EFI_ACPI_PHYTIUM_CREATOR_REVISION 0x20201111
+
+// A macro to initialise the common header part of EFI ACPI tables as defined by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define PHYTIUM_ACPI_HEADER(Signature, Type, Revision) { \
+ Signature, /* UINT32 Signature */ \
+ sizeof (Type), /* UINT32 Length */ \
+ Revision, /* UINT8 Revision */ \
+ 0, /* UINT8 Checksum */ \
+ { EFI_ACPI_PHYTIUM_OEM_ID }, /* UINT8 OemId[6] */ \
+ EFI_ACPI_PHYTIUM_OEM_TABLE_ID, /* UINT64 OemTableId */ \
+ EFI_ACPI_PHYTIUM_OEM_REVISION, /* UINT32 OemRevision */ \
+ EFI_ACPI_PHYTIUM_CREATOR_ID, /* UINT32 CreatorId */ \
+ EFI_ACPI_PHYTIUM_CREATOR_REVISION /* UINT32 CreatorRevision */ \
+ }
+
+#endif // PLATFORM_H_
diff --git a/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform.c
new file mode 100644
index 0000000000..c48ed74f53
--- /dev/null
+++ b/Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform.c
@@ -0,0 +1,250 @@
+/** @file
+ Sample ACPI Platform Driver.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <PiDxe.h>
+#include <Protocol/AcpiTable.h>
+#include <Protocol/FirmwareVolume2.h>
+
+/**
+ Locate the first instance of a protocol. If the protocol requested is an
+ FV protocol, then it will return the first FV that contains the ACPI table
+ storage file.
+
+ @param[out] Instance Return pointer to the first instance of the protocol.
+
+ @return EFI_SUCCESS The function completed successfully.
+
+ @return EFI_NOT_FOUND The protocol could not be located.
+
+ @return EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol.
+
+**/
+EFI_STATUS
+LocateFvInstanceWithTables (
+ OUT EFI_FIRMWARE_VOLUME2_PROTOCOL **Instance
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN NumberOfHandles;
+ EFI_FV_FILETYPE FileType;
+ UINT32 FvStatus;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ UINTN Size;
+ UINTN Index;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FvInstance;
+
+ FvStatus = 0;
+
+ //
+ // Locate protocol.
+ //
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ NULL,
+ &NumberOfHandles,
+ &HandleBuffer
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // Defined errors at this time are not found and out of resources.
+ //
+ return Status;
+ }
+
+ //
+ // Looking for FV with ACPI storage file
+ //
+
+ for (Index = 0; Index < NumberOfHandles; Index++) {
+ //
+ // Get the protocol on this handle
+ // This should not fail because of LocateHandleBuffer
+ //
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gEfiFirmwareVolume2ProtocolGuid,
+ (VOID **)&FvInstance
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // See if it has the ACPI storage file
+ //
+ Status = FvInstance->ReadFile (
+ FvInstance,
+ (EFI_GUID *)PcdGetPtr (PcdAcpiTableStorageFile),
+ NULL,
+ &Size,
+ &FileType,
+ &Attributes,
+ &FvStatus
+ );
+
+ //
+ // If we found it, then we are done
+ //
+ if (Status == EFI_SUCCESS) {
+ *Instance = FvInstance;
+ break;
+ }
+ }
+
+ //
+ // Free any allocated buffers
+ //
+ gBS->FreePool (HandleBuffer);
+
+ return Status;
+}
+
+
+/**
+ This function calculates and updates an UINT8 checksum.
+
+ @param[in] Buffer Pointer to buffer to checksum.
+
+ @param[in] Size Number of bytes to checksum.
+
+**/
+VOID
+AcpiPlatformChecksum (
+ IN UINT8 *Buffer,
+ IN UINTN Size
+ )
+{
+ UINTN ChecksumOffset;
+
+ ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum);
+
+ //
+ // Set checksum to 0 first
+ //
+ Buffer[ChecksumOffset] = 0;
+
+ //
+ // Update checksum value
+ //
+ Buffer[ChecksumOffset] = CalculateCheckSum8 (Buffer, Size);
+}
+
+
+/**
+ This function is the entrypoint of the acpi platform.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+
+ @retval other Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+AcpiPlatformEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
+ INTN Instance;
+ EFI_ACPI_COMMON_HEADER *CurrentTable;
+ UINTN TableHandle;
+ UINT32 FvStatus;
+ UINTN TableSize;
+ UINTN Size;
+
+ Instance = 0;
+ CurrentTable = NULL;
+ TableHandle = 0;
+
+ //
+ // Find the AcpiTable protocol
+ //
+ Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **)&AcpiTable);
+ if (EFI_ERROR (Status)) {
+ return EFI_ABORTED;
+ }
+
+ //
+ // Locate the firmware volume protocol
+ //
+ Status = LocateFvInstanceWithTables (&FwVol);
+ if (EFI_ERROR (Status)) {
+ return EFI_ABORTED;
+ }
+ //
+ // Read tables from the storage file.
+ //
+ while (Status == EFI_SUCCESS) {
+
+ Status = FwVol->ReadSection (
+ FwVol,
+ (EFI_GUID *)PcdGetPtr (PcdAcpiTableStorageFile),
+ EFI_SECTION_RAW,
+ Instance,
+ (VOID **)&CurrentTable,
+ &Size,
+ &FvStatus
+ );
+ if ( ! EFI_ERROR (Status)) {
+ //
+ // Add the table
+ //
+ TableHandle = 0;
+
+ TableSize = ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length;
+ ASSERT (Size >= TableSize);
+
+ //
+ // Checksum ACPI table
+ //
+ AcpiPlatformChecksum ((UINT8 *)CurrentTable, TableSize);
+
+ //
+ // Install ACPI table
+ //
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ CurrentTable,
+ TableSize,
+ &TableHandle
+ );
+
+ //
+ // Free memory allocated by ReadSection
+ //
+ gBS->FreePool (CurrentTable);
+
+ if (EFI_ERROR (Status)) {
+ return EFI_ABORTED;
+ }
+
+ //
+ // Increment the instance
+ //
+ Instance++;
+ CurrentTable = NULL;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl
new file mode 100644
index 0000000000..667f8cc8fb
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl
@@ -0,0 +1,209 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Platform.h>
+
+#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
+ Device (Link_Name) { \
+ Name (_HID, EISAID ("PNP0C0F")) \
+ Name (_UID, Unique_Id) \
+ Name (_PRS, ResourceTemplate () { \
+ Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
+ }) \
+ Method (_CRS, 0) { Return (_PRS) } \
+ Method (_SRS, 1) { } \
+ Method (_DIS) { } \
+ }
+
+#define PRT_ENTRY(Address, Pin, Link) \
+ Package (4) { \
+ Address, \
+ Pin, \
+ Link, \
+ Zero \
+ }
+
+#define ROOT_PRT_ENTRY(Dev, Pin, Link) PRT_ENTRY(Dev * 0x10000 + 0xFFFF, Pin, Link)
+
+
+DefinitionBlock ("SsdtPci.aml", "SSDT", 2, "FT-LTD", "PHYTIUM ", EFI_ACPI_PHYTIUM_OEM_REVISION) {
+ Scope (_SB) {
+ //
+ // PCI Root Complex
+ //
+ LNK_DEVICE (1, LNKA, 60)
+ LNK_DEVICE (2, LNKB, 61)
+ LNK_DEVICE (3, LNKC, 62)
+ LNK_DEVICE (4, LNKD, 63)
+
+ // reserve ECAM memory range
+ Device (RES0)
+ {
+ Name (_HID, EISAID ("PNP0C02"))
+ Name (_UID, 0)
+ Name (_CRS, ResourceTemplate () {
+ QWordMemory (ResourceConsumer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0, // Granularity
+ 0x40000000, // Range Minimum
+ 0x4FFFFFFF, // Range Maximum
+ 0, // Translation Offset
+ 0x10000000, // Length
+ ,,)
+ })
+ }
+
+ Device (PCI0)
+ {
+ Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge
+ Name (_CID, EISAID ("PNP0A03")) // Compatible PCI Root Bridge
+ Name (_SEG, Zero) // PCI Segment Group number
+ Name (_BBN, 0) // PCI Base Bus Number
+ Name (_CCA, 1)
+
+ // Root Complex
+ Device (RP0) {
+ Name (_ADR, 0x00000000) // Dev 0, Func 0
+ }
+ // PCI Routing Table
+ Name (_PRT, Package () {
+ ROOT_PRT_ENTRY (0, 0, LNKA), // INTA
+ ROOT_PRT_ENTRY (0, 1, LNKB), // INTB
+ ROOT_PRT_ENTRY (0, 2, LNKC), // INTC
+ ROOT_PRT_ENTRY (0, 3, LNKD), // INTD
+
+ ROOT_PRT_ENTRY (1, 0, LNKA), // INTA
+ ROOT_PRT_ENTRY (1, 1, LNKB), // INTB
+ ROOT_PRT_ENTRY (1, 2, LNKC), // INTC
+ ROOT_PRT_ENTRY (1, 3, LNKD), // INTD
+
+ ROOT_PRT_ENTRY (2, 0, LNKA), // INTA
+ ROOT_PRT_ENTRY (2, 1, LNKB), // INTB
+ ROOT_PRT_ENTRY (2, 2, LNKC), // INTC
+ ROOT_PRT_ENTRY (2, 3, LNKD), // INTD
+
+ ROOT_PRT_ENTRY (3, 0, LNKA), // INTA
+ ROOT_PRT_ENTRY (3, 1, LNKB), // INTB
+ ROOT_PRT_ENTRY (3, 2, LNKC), // INTC
+ ROOT_PRT_ENTRY (3, 3, LNKD), // INTD
+
+ ROOT_PRT_ENTRY (4, 0, LNKA), // INTA
+ ROOT_PRT_ENTRY (4, 1, LNKB), // INTB
+ ROOT_PRT_ENTRY (4, 2, LNKC), // INTC
+ ROOT_PRT_ENTRY (4, 3, LNKD), // INTD
+
+ ROOT_PRT_ENTRY (5, 0, LNKA), // INTA
+ ROOT_PRT_ENTRY (5, 1, LNKB), // INTB
+ ROOT_PRT_ENTRY (5, 2, LNKC), // INTC
+ ROOT_PRT_ENTRY (5, 3, LNKD), // INTD
+ })
+
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber (
+ ResourceProducer,
+ MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0, // AddressMinimum - Minimum Bus Number
+ 255, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 256 // RangeLength - Number of Busses
+ )
+
+ DWordMemory ( // 32-bit BAR Windows
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x58000000, // Min Base Address
+ 0x7FFFFFFF, // Max Base Address
+ 0x00000000, // Translate
+ 0x28000000 // Length
+ )
+
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x1000000000, // Min Base Address
+ 0x1FFFFFFFFF, // Max Base Address
+ 0x0000000000, // Translate
+ 0x1000000000 // Length
+ )
+
+ DWordIo ( // IO window
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x00000000, // Granularity
+ 0x00000000, // Min Base Address
+ 0x00efffff, // Max Base Address
+ 0x50000000, // Translate
+ 0x00f00000, // Length
+ ,,, TypeTranslation
+ )
+ }) // Name(RBUF)
+
+ Return (RBUF)
+ } // Method(_CRS)
+
+ //
+ // OS Control Handoff
+ //
+ Name (SUPP, Zero) // PCI _OSC Support Field value
+ Name (CTRL, Zero) // PCI _OSC Control Field value
+
+ /*
+ See [1] 6.2.10, [2] 4.5
+ */
+ Method (_OSC, 4) {
+ // Check for proper UUID
+ If (LEqual (Arg0, ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField (Arg3, 0, CDW1)
+ CreateDWordField (Arg3, 4, CDW2)
+ CreateDWordField (Arg3, 8, CDW3)
+
+ // Save Capabilities DWord2 & 3
+ Store (CDW2, SUPP)
+ Store (CDW3, CTRL)
+
+ // Only allow native hot plug control if OS supports:
+ // * ASPM
+ // * Clock PM
+ // * MSI/MSI-X
+ If (LNotEqual (And (SUPP, 0x16), 0x16)) {
+ And (CTRL, 0x1E, CTRL) // Mask bit 0 (and undefined bits)
+ }
+
+ // Do not allow native PME, AER (no dependencies)
+ // Never allow SHPC (no SHPC controller in this system)
+ And (CTRL, 0x10, CTRL)
+
+ If (LNotEqual (Arg1, One)) { // Unknown revision
+ Or (CDW1, 0x08, CDW1)
+ }
+
+ If (LNotEqual (CDW3, CTRL)) { // Capabilities bits were masked
+ Or (CDW1, 0x10, CDW1)
+ }
+ // Update DWORD3 in the buffer
+ Store (CTRL, CDW3)
+ Return (Arg3)
+ } Else {
+ Or (CDW1, 4, CDW1) // Unrecognized UUID
+ Return (Arg3)
+ }
+ }
+ }
+ }
+}
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc
new file mode 100644
index 0000000000..5349f6364b
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc
@@ -0,0 +1,80 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/DebugPort2Table.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <Platform.h>
+
+#define NUMBER_DEBUG_DEVICE_INFO 1
+#define NUMBER_OF_GENERIC_ADDRESS 1
+#define NAMESPACE_STRING_SIZE 8
+
+#pragma pack(1)
+
+typedef struct {
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT DdiHeader;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE Address[NUMBER_OF_GENERIC_ADDRESS];
+ UINT32 AddressSize[NUMBER_OF_GENERIC_ADDRESS];
+ CHAR8 NamespaceString[NAMESPACE_STRING_SIZE];
+} EFI_ACPI_DBG2_DDI_STRUCT;
+
+typedef struct {
+ EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Desc;
+ EFI_ACPI_DBG2_DDI_STRUCT Ddi[NUMBER_DEBUG_DEVICE_INFO];
+} EFI_ACPI_DEBUG_PORT_2_TABLE;
+
+#pragma pack()
+
+EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 = {
+ {
+ PHYTIUM_ACPI_HEADER (
+ EFI_ACPI_6_1_DEBUG_PORT_2_TABLE_SIGNATURE,
+ EFI_ACPI_DEBUG_PORT_2_TABLE,
+ EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION
+ ),
+ OFFSET_OF (EFI_ACPI_DEBUG_PORT_2_TABLE, Ddi),
+ NUMBER_DEBUG_DEVICE_INFO
+ },
+ {
+ {
+ {
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
+ sizeof (EFI_ACPI_DBG2_DDI_STRUCT),
+ NUMBER_OF_GENERIC_ADDRESS,
+ NAMESPACE_STRING_SIZE,
+ OFFSET_OF (EFI_ACPI_DBG2_DDI_STRUCT, NamespaceString),
+ 0,
+ 0,
+ EFI_ACPI_DBG2_PORT_TYPE_SERIAL,
+ EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART,
+ {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE},
+ OFFSET_OF (EFI_ACPI_DBG2_DDI_STRUCT, Address),
+ OFFSET_OF (EFI_ACPI_DBG2_DDI_STRUCT, AddressSize),
+ },
+ {
+ {
+ EFI_ACPI_6_1_SYSTEM_MEMORY,
+ 32,
+ 0,
+ EFI_ACPI_6_1_DWORD,
+ FixedPcdGet64 (PcdSerialRegisterBase)
+ }
+ },
+ {
+ 0x1000
+ },
+ "COM0"
+ }
+ }
+};
+
+VOID * CONST ReferenceAcpiTable = &Dbg2;
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl
new file mode 100644
index 0000000000..219a129fa5
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl
@@ -0,0 +1,85 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+Scope (_SB)
+{
+ Device (CLU0) {
+ Name (_HID, "ACPI0010")
+ Name (_UID, 0)
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+ Device (CPU0) {
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0)
+ Name (_DSD, Package () {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"clock-name", "c0"},
+ Package () {"clock-domain", 0},
+ }
+ })
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+ }
+
+ Device (CPU1) {
+ Name (_HID, "ACPI0007")
+ Name (_UID, 1)
+ Name (_DSD, Package () {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"clock-name", "c0"},
+ Package () {"clock-domain", 0},
+ }
+ })
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+ }
+ }
+
+ Device (CLU1) {
+ Name (_HID, "ACPI0010")
+ Name (_UID, 1)
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+ Device (CPU2) {
+ Name (_HID, "ACPI0007")
+ Name (_UID, 2)
+ Name (_DSD, Package () {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"clock-name", "c1"},
+ Package () {"clock-domain", 1},
+ }
+ })
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+ }
+
+ Device (CPU3) {
+ Name (_HID, "ACPI0007")
+ Name (_UID, 3)
+ Name (_DSD, Package () {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"clock-name", "c1"},
+ Package () {"clock-domain", 1},
+ }
+ })
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+ }
+ }
+}
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl
new file mode 100644
index 0000000000..b21431ca36
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl
@@ -0,0 +1,15 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Platform.h>
+
+DefinitionBlock ("DsdtTable.aml", "DSDT", 2, "FT-LTD", "PHYTIUM ", EFI_ACPI_PHYTIUM_OEM_REVISION) {
+ include ("Cpu.asl")
+ include ("Uart.asl")
+}
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl
new file mode 100644
index 0000000000..25752036b5
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl
@@ -0,0 +1,65 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+Scope (_SB)
+{
+ //UART 0
+ Device (UAR0) {
+ Name (_HID, "ARMH0011")
+ Name (_UID, 0)
+ Name (_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x28000000, 0x1000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 38 }
+ })
+
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+ }
+
+ //UART 1
+ Device (UAR1) {
+ Name (_HID, "ARMH0011")
+ Name (_UID, 1)
+ Name (_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x28001000, 0x1000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {39}
+ })
+
+ Method (_STA, 0, NotSerialized) { Return (0x0F) }
+ }
+
+ //UART 2
+ Device (UAR2) {
+ Name (_HID, "ARMH0011")
+ Name (_UID, 2)
+ Name (_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x28002000, 0x1000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {40}
+ })
+
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+ }
+
+ //UART 3
+ Device (UAR3) {
+ Name (_HID, "ARMH0011")
+ Name (_UID, 3)
+ Name (_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x28003000, 0x1000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {41}
+ })
+
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+ }
+}
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc
new file mode 100644
index 0000000000..10612c1368
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc
@@ -0,0 +1,77 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Platform.h>
+
+EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+ PHYTIUM_ACPI_HEADER (
+ EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE,
+ EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+ ),
+ 0, // UINT32 FirmwareCtrl
+ 0, // UINT32 Dsdt
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
+ EFI_ACPI_6_1_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile
+ 0, // UINT16 SciInt
+ 0, // UINT32 SmiCmd
+ 0, // UINT8 AcpiEnable
+ 0, // UINT8 AcpiDisable
+ 0, // UINT8 S4BiosReq
+ 0, // UINT8 PstateCnt
+ 0, // UINT32 Pm1aEvtBlk
+ 0, // UINT32 Pm1bEvtBlk
+ 0, // UINT32 Pm1aCntBlk
+ 0, // UINT32 Pm1bCntBlk
+ 0, // UINT32 Pm2CntBlk
+ 0, // UINT32 PmTmrBlk
+ 0, // UINT32 Gpe0Blk
+ 0, // UINT32 Gpe1Blk
+ 0, // UINT8 Pm1EvtLen
+ 0, // UINT8 Pm1CntLen
+ 0, // UINT8 Pm2CntLen
+ 0, // UINT8 PmTmrLen
+ 0, // UINT8 Gpe0BlkLen
+ 0, // UINT8 Gpe1BlkLen
+ 0, // UINT8 Gpe1Base
+ 0, // UINT8 CstCnt
+ 0, // UINT16 PLvl2Lat
+ 0, // UINT16 PLvl3Lat
+ 0, // UINT16 FlushSize
+ 0, // UINT16 FlushStride
+ 0, // UINT8 DutyOffset
+ 0, // UINT8 DutyWidth
+ 0, // UINT8 DayAlrm
+ 0, // UINT8 MonAlrm
+ 0, // UINT8 Century
+ 0, // UINT16 IaPcBootArch
+ 0, // UINT8 Reserved1
+ EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE ResetReg
+ 0, // UINT8 ResetValue
+ EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
+ EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
+ 0, // UINT64 XFirmwareCtrl
+ 0, // UINT64 XDsdt
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XGpe0Blk
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XGpe1Blk
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE SleepControlReg
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE SleepStatusReg
+ 0 // UINT64 Hypervisor Vendor Identify
+};
+
+VOID * CONST ReferenceAcpiTable = &Fadt;
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc
new file mode 100644
index 0000000000..67468db2d4
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc
@@ -0,0 +1,83 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <Platform.h>
+
+#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
+#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0
+#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
+#define GTDT_GLOBAL_FLAGS_LEVEL 0
+
+#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED 0
+#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH 0
+#define GTDT_TIMER_ALWAYS_ON_CAPABILITY EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY
+
+#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED \
+ | EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY)
+
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
+ EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[2];
+} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES;
+
+#pragma pack ()
+
+EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
+ {
+ PHYTIUM_ACPI_HEADER (
+ EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES,
+ EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
+ ),
+ 0xFFFFFFFFFFFFFFFF, // UINT64 PhysicalAddress
+ 0, // UINT32 Reserved
+ FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
+ FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
+ 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress
+ 2,
+ sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE)
+ },
+
+ {
+ {
+ 1, //Type
+ 28, //Size of this structure
+ 0, //reserved
+ 0x2800a000, //RefreshFrame Physical Address
+ 0x2800b000, //WatchdogControlFrame Physical Address
+ 48, //Watchdog Timer GSIV
+ 0, //Watchdog Timer Flags high level
+ },
+
+ {
+ 1,
+ 28,
+ 0,
+ 0x28016000,
+ 0x28017000,
+ 49,
+ 0,
+ }
+ }
+};
+
+VOID * CONST ReferenceAcpiTable = &Gtdt;
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc
new file mode 100644
index 0000000000..4239499b68
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc
@@ -0,0 +1,89 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <IndustryStandard/IoRemappingTable.h>
+#include <Platform.h>
+
+#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name)
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE Node;
+ UINT32 Identifiers[1];
+} PHYTIUM_ITS_NODE;
+
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Node;
+ EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping;
+} PHYTIUM_RC_NODE;
+
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort;
+ PHYTIUM_ITS_NODE ItsNode;
+ PHYTIUM_RC_NODE RcNode[1];
+} PHYTIUM_IO_REMAPPING_STRUCTURE;
+
+#define __PHYTIUM_ID_MAPPING(In, Num, Out, Ref, Flags) \
+ { \
+ In, \
+ Num, \
+ Out, \
+ FIELD_OFFSET (PHYTIUM_IO_REMAPPING_STRUCTURE, Ref), \
+ Flags \
+ }
+
+STATIC PHYTIUM_IO_REMAPPING_STRUCTURE Iort = {
+ {
+ PHYTIUM_ACPI_HEADER (EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE,
+ PHYTIUM_IO_REMAPPING_STRUCTURE,
+ EFI_ACPI_IO_REMAPPING_TABLE_REVISION),
+ 2, // NumNodes
+ sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset
+ 0 // Reserved
+ }, {
+ // ItsNode
+ {
+ {
+ EFI_ACPI_IORT_TYPE_ITS_GROUP, // Type
+ sizeof (PHYTIUM_ITS_NODE), // Length
+ 0x0, // Revision
+ 0x0, // Reserved
+ 0x0, // NumIdMappings
+ 0x0, // IdReference
+ },
+ 1,
+ }, {
+ 0x0
+ },
+ }, {
+ {
+ // PciRcNode
+ {
+ {
+ EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type
+ sizeof (PHYTIUM_RC_NODE), // Length
+ 0x0, // Revision
+ 0x0, // Reserved
+ 0x1, // NumIdMappings
+ FIELD_OFFSET (PHYTIUM_RC_NODE, RcIdMapping), // IdReference
+ },
+ EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCoherent
+ 0x0, // AllocationHints
+ 0x0, // Reserved
+ EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM, // MemoryAccessFlags
+ EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute
+ 0x0, // PciSegmentNumber
+ },
+ __PHYTIUM_ID_MAPPING (0x0, 0xffff, 0x0, ItsNode, 0),
+ }
+ }
+};
+#pragma pack()
+#
+VOID * CONST ReferenceAcpiTable = &Iort;
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc
new file mode 100644
index 0000000000..ef6d94837f
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc
@@ -0,0 +1,67 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <Platform.h>
+
+
+#define PLATFORM_GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
+
+#define EFI_GICC_STRUCTURE(AcpiCpuUid, Mpidr, GicRBaseOffset) \
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(0, AcpiCpuUid, Mpidr, EFI_ACPI_6_1_GIC_ENABLED, 23, \
+ FixedPcdGet64(PcdGicInterruptInterfaceBase), FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, \
+ FixedPcdGet64(PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicRedistributorsBase) + GicRBaseOffset, 0)
+#define CORE_NUM 4
+//
+// Multiple APIC Description Table
+//
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[CORE_NUM];
+ EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[1];
+} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+//
+// Multiple APIC Description Table
+//
+EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+ {
+ PHYTIUM_ACPI_HEADER (
+ EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ ),
+ //
+ // MADT specific fields
+ //
+ 0, // LocalApicAddress
+ 0, // Flags
+ },
+ {
+ EFI_GICC_STRUCTURE (0x00, PLATFORM_GET_MPID (0x00, 0), 0x000000),
+ EFI_GICC_STRUCTURE (0x01, PLATFORM_GET_MPID (0x00, 1), 0x020000),
+ EFI_GICC_STRUCTURE (0x02, PLATFORM_GET_MPID (0x01, 0), 0x040000),
+ EFI_GICC_STRUCTURE (0x03, PLATFORM_GET_MPID (0x01, 1), 0x060000),
+ },
+
+ EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT (0, FixedPcdGet32 (PcdGicDistributorBase), 0, 0x3),
+ {
+ EFI_ACPI_6_1_GIC_ITS_INIT (0, FixedPcdGet64 (PcdGicDistributorBase) + 0x20000),
+ }
+};
+
+VOID * CONST ReferenceAcpiTable = &Madt;
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc
new file mode 100644
index 0000000000..34eebd6aee
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc
@@ -0,0 +1,65 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Platform.h>
+
+#define ACPI_6_1_MCFG_VERSION 0x1
+
+#pragma pack(1)
+typedef struct
+{
+ UINT64 BaseAddress;
+ UINT16 SegGroupNum;
+ UINT8 StartBusNum;
+ UINT8 EndBusNum;
+ UINT32 Reserved2;
+} EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE;
+
+typedef struct
+{
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 Reserved1;
+} EFI_ACPI_6_1_MCFG_TABLE_CONFIG;
+
+typedef struct
+{
+ EFI_ACPI_6_1_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;
+ EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE Config_Structure[1];
+} EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE;
+#pragma pack()
+
+EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg=
+{
+ {
+ {
+ EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE),
+ ACPI_6_1_MCFG_VERSION,
+ 0x00, // Checksum will be updated at runtime
+ {EFI_ACPI_PHYTIUM_OEM_ID},
+ EFI_ACPI_PHYTIUM_OEM_TABLE_ID,
+ EFI_ACPI_PHYTIUM_OEM_REVISION,
+ EFI_ACPI_PHYTIUM_CREATOR_ID,
+ EFI_ACPI_PHYTIUM_CREATOR_REVISION
+ },
+ 0x0000000000000000, //Reserved
+ },
+ {
+ {
+ 0x40000000, //Base Address
+ 0, //Segment Group Number
+ 0, //Start Bus Number
+ 0xff, //End Bus Number
+ 0x00000000, //Reserved
+ },
+ }
+};
+
+VOID * CONST ReferenceAcpiTable = &Mcfg;
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc
new file mode 100644
index 0000000000..ae1a21df23
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc
@@ -0,0 +1,219 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Platform.h>
+
+#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name)
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core;
+ UINT32 Offset[2];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE DCache;
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE ICache;
+} PHYTIUM_PPTT_CORE;
+
+typedef struct {
+ EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster;
+ UINT32 Offset[1];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L2Cache;
+ PHYTIUM_PPTT_CORE Cores[2];
+} PHYTIUM_PPTT_CLUSTER;
+
+typedef struct {
+ EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 Offset[1];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L3Cache;
+ PHYTIUM_PPTT_CLUSTER Clusters[2];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_ID ID;
+} PHYTIUM_PPTT_PACKAGE;
+
+typedef struct {
+ EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt;
+ PHYTIUM_PPTT_PACKAGE Packages[1];
+} PHYTIUM_PPTT_TABLE;
+#pragma pack()
+
+#define PPTT_CORE(pid, cid, id) { \
+ { \
+ EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \
+ FIELD_OFFSET (PHYTIUM_PPTT_CORE, DCache), \
+ {}, \
+ { \
+ 0, /* PhysicalPackage */ \
+ EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */ \
+ }, \
+ FIELD_OFFSET (PHYTIUM_PPTT_TABLE, \
+ Packages[pid].Clusters[cid]), /* Parent */ \
+ 8 * (pid) + 4 * (cid) + (id), /* AcpiProcessorId */ \
+ 2, /* NumberOfPrivateResources */\
+ }, { \
+ FIELD_OFFSET (PHYTIUM_PPTT_TABLE, \
+ Packages[pid].Clusters[cid].Cores[id].DCache), \
+ FIELD_OFFSET (PHYTIUM_PPTT_TABLE, \
+ Packages[pid].Clusters[cid].Cores[id].ICache), \
+ }, { \
+ EFI_ACPI_6_2_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \
+ {}, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 1, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 1, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ SIZE_32KB, /* Size */ \
+ 256, /* NumberOfSets */ \
+ 2, /* Associativity */ \
+ { \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
+ }, \
+ 64 /* LineSize */ \
+ }, { \
+ EFI_ACPI_6_2_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \
+ {}, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 1, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 0, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ SIZE_32KB, /* Size */ \
+ 256, /* NumberOfSets */ \
+ 2, /* Associativity */ \
+ { \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ, /* AllocationType */ \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
+ 0, /* WritePolicy */ \
+ }, \
+ 64 /* LineSize */ \
+ } \
+}
+
+#define PPTT_CLUSTER(pid, cid) { \
+ { \
+ EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \
+ FIELD_OFFSET (PHYTIUM_PPTT_CLUSTER, L2Cache), \
+ {}, \
+ { \
+ 0, /* PhysicalPackage */ \
+ EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \
+ }, \
+ FIELD_OFFSET (PHYTIUM_PPTT_TABLE, Packages[pid]), /* Parent */ \
+ 0, /* AcpiProcessorId */ \
+ 1, /* NumberOfPrivateResources */ \
+ }, { \
+ FIELD_OFFSET (PHYTIUM_PPTT_TABLE, Packages[pid].Clusters[cid].L2Cache), \
+ }, { \
+ EFI_ACPI_6_2_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \
+ {}, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 1, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 1, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ SIZE_2MB, /* Size */ \
+ 2048, /* NumberOfSets */ \
+ 16, /* Associativity */ \
+ { \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
+ }, \
+ 64 /* LineSize */ \
+ }, { \
+ PPTT_CORE (pid, cid, 0), \
+ PPTT_CORE (pid, cid, 1), \
+ } \
+}
+
+#define PPTT_PANEL(pid) { \
+ { \
+ EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \
+ FIELD_OFFSET (PHYTIUM_PPTT_PACKAGE, L3Cache), \
+ {}, \
+ { \
+ 1, /* PhysicalPackage */ \
+ EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \
+ }, \
+ 0, /* Parent */ \
+ 0, /* AcpiProcessorId */ \
+ 1, /* NumberOfPrivateResources */ \
+ }, { \
+ FIELD_OFFSET (PHYTIUM_PPTT_TABLE, Packages[pid].L3Cache), \
+ }, { \
+ EFI_ACPI_6_2_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \
+ {}, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 0, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 1, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ SIZE_4MB, /* Size */ \
+ 4096, /* NumberOfSets */ \
+ 16, /* Associativity */ \
+ { \
+ 0, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
+ }, \
+ 64 /* LineSize */ \
+ }, { \
+ PPTT_CLUSTER (pid, 0), \
+ PPTT_CLUSTER (pid, 1), \
+ }, { \
+ EFI_ACPI_6_2_PPTT_TYPE_ID, \
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID), \
+ {0}, \
+ 0x54594850, \
+ 0x3, \
+ 0x1, \
+ 0, \
+ 0, \
+ 0, \
+ } \
+}
+
+
+STATIC PHYTIUM_PPTT_TABLE mPhytiumPpttTable = {
+ {
+ PHYTIUM_ACPI_HEADER (EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ PHYTIUM_PPTT_TABLE,
+ EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION),
+ },
+ {
+ PPTT_PANEL (0)
+ }
+};
+
+VOID * CONST ReferenceAcpiTable = &mPhytiumPpttTable;
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc
new file mode 100644
index 0000000000..00ffb7e7a9
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc
@@ -0,0 +1,73 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <Platform.h>
+
+///
+/// SPCR Flow Control
+///
+#define SPCR_FLOW_CONTROL_NONE 0
+
+
+STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
+ PHYTIUM_ACPI_HEADER (EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION),
+ // UINT8 InterfaceType;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,
+ // UINT8 Reserved1[3];
+ {
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE
+ },
+ // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;
+ ARM_GAS32 (FixedPcdGet64 (PcdSerialRegisterBase)),
+ // UINT8 InterruptType;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
+ // UINT8 Irq;
+ 0, // Not used on ARM
+ // UINT32 GlobalSystemInterrupt;
+ FixedPcdGet32 (PL011UartInterrupt),
+ // UINT8 BaudRate;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
+ // UINT8 Parity;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
+ // UINT8 StopBits;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
+ // UINT8 FlowControl;
+ SPCR_FLOW_CONTROL_NONE,
+ // UINT8 TerminalType;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
+ // UINT8 Reserved2;
+ EFI_ACPI_RESERVED_BYTE,
+ // UINT16 PciDeviceId;
+ 0xFFFF,
+ // UINT16 PciVendorId;
+ 0xFFFF,
+ // UINT8 PciBusNumber;
+ 0x00,
+ // UINT8 PciDeviceNumber;
+ 0x00,
+ // UINT8 PciFunctionNumber;
+ 0x00,
+ // UINT32 PciFlags;
+ 0x00000000,
+ // UINT8 PciSegment;
+ 0x00,
+ // UINT32 Reserved3;
+ EFI_ACPI_RESERVED_DWORD
+};
+
+VOID * CONST ReferenceAcpiTable = &Spcr;
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v5 03/10] Silicon/Phytium: Added SMBIOS support to FT2000/4
2021-09-09 9:47 [PATCH v5 00/10] Added support for FT2000/4 chip Ling Jia
2021-09-09 9:47 ` [PATCH v5 01/10] Silicon/Phytium: Added PlatformLib to FT2000/4 Ling Jia
2021-09-09 9:47 ` [PATCH v5 02/10] Silicon/Phytium: Added Acpi support " Ling Jia
@ 2021-09-09 9:47 ` Ling Jia
2021-09-09 9:47 ` [PATCH v5 04/10] Silicon/Phytium: Added PciSegmentLib " Ling Jia
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Ling Jia @ 2021-09-09 9:47 UTC (permalink / raw)
To: devel; +Cc: Leif Lindholm, Ling Jia
This driver installs SMBIOS information for FT2000/4.
Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Platform/Phytium/DurianPkg/DurianPkg.dsc | 6 +
Platform/Phytium/DurianPkg/DurianPkg.fdf | 6 +
Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 47 +
Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 943 ++++++++++++++++++++
4 files changed, 1002 insertions(+)
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/DurianPkg/DurianPkg.dsc
index 6f38acb636..28e52e15e3 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.dsc
+++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc
@@ -286,6 +286,12 @@
Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf
Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ #
+ # SMBIOS
+ #
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
+
#
# Bds
#
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/DurianPkg/DurianPkg.fdf
index f435f7cb51..3106a43fb7 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.fdf
+++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf
@@ -178,6 +178,12 @@ READ_LOCK_STATUS = TRUE
#
INF ShellPkg/Application/Shell/Shell.inf
+ #
+ # SMBIOS
+ #
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ INF Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
+
#
# Bds
#
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf b/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
new file mode 100644
index 0000000000..69a021e048
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
@@ -0,0 +1,47 @@
+#/** @file
+# This driver installs SMBIOS information for Phytium.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = SmbiosPlatformDxe
+ FILE_GUID = d64f09f8-40dc-11eb-9be6-f7a038f956ba
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = SmbiosTablePublishEntry
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+[Sources]
+ SmbiosPlatformDxe.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ IoLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Guids]
+ gEfiGlobalVariableGuid
+
+[Protocols]
+ gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED
+
+[Guids]
+
+[Depex]
+ gEfiSmbiosProtocolGuid
diff --git a/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c b/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
new file mode 100644
index 0000000000..4a1f77dfb2
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
@@ -0,0 +1,943 @@
+/** @file
+ This driver installs SMBIOS information for Phytium Durian platforms.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include <IndustryStandard/SmBios.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Platform.h>
+#include <Protocol/Smbios.h>
+
+// SMBIOS tables often reference each other using
+// fixed constants, define a list of these constants
+// for our hardcoded tables
+
+#define TYPE0_STRINGS \
+ "PHYTIUM LTD\0" /* Vendor */ \
+ "V1.0\0" /* BiosVersion */ \
+ __DATE__"\0" /* BiosReleaseDate */
+
+#define TYPE1_STRINGS \
+ "PHYTIUM LTD\0" /* Manufacturer */ \
+ "Phytium Durian Development Platform\0" /* Product Name */ \
+ "None\0" /* Version */ \
+ "Not Set\0" /* SerialNumber */ \
+ "Not set\0" /* SKUNumber */ \
+ "FT-2000/4\0" /* Family */ \
+
+#define TYPE2_STRINGS \
+ "PHYTIUM LTD\0" /* Manufacturer */ \
+ "Phytium Durian Development Platform\0" /* Product Name */ \
+ "None\0" /* Version */ \
+ "Not Set\0" /* Serial */ \
+ "Not Set\0" /* BaseBoardAssetTag */ \
+ "Not Set\0" /* BaseBoardChassisLocation */
+
+#define TYPE3_STRINGS \
+ "PHYTIUM LTD\0" /* Manufacturer */ \
+ "None\0" /* Version */ \
+ "Not Set\0" /* Serial */ \
+ "Not Set\0" /* AssetTag */
+
+#define TYPE4_STRINGS \
+ "FT-2000/4\0" /* socket type */ \
+ "PHYTIUM LTD\0" /* manufactuer */ \
+ "FT-2000/4\0" /* processor version */ \
+ "Not Set\0" /* SerialNumber */ \
+ "Not Set\0" /* processor 2 description */ \
+ "Not Set\0" /* AssetTag */
+
+
+#define TYPE7_STRINGS \
+ "L1 Instruction\0" /* L1I */ \
+ "L1 Data\0" /* L1D */ \
+ "L2\0" /* L2 */
+
+#define TYPE7_L1DATA_STRINGS \
+ "L1 Data Cache\0" /* L1 data */
+
+
+#define TYPE7_L1INS_STRINGS \
+ "L1 Instruction Cache\0" /* L1 ins */
+
+#define TYPE7_L2_STRINGS \
+ "L2 Cache\0" /* L2 */
+
+#define TYPE7_L3_STRINGS \
+ "L3 Cache\0" /* L3 */
+
+
+#define TYPE9_STRINGS \
+ "PCIE_SLOT0\0" /* Slot0 */ \
+ "PCIE_SLOT1\0" /* Slot1 */ \
+ "PCIE_SLOT2\0" /* Slot2 */ \
+ "PCIE_SLOT3\0" /* Slot3 */
+
+#define TYPE9_STRINGS_PCIE0X16 \
+ "PCIE0_X16\0"
+
+#define TYPE9_STRINGS_PCIE0X1 \
+ "PCIE0_X1\0"
+
+#define TYPE9_STRINGS_PCIE1X16 \
+ "PCIE1_X16\0"
+
+#define TYPE9_STRINGS_PCIE1X1 \
+ "PCIE1_X1\0"
+
+#define TYPE13_STRINGS \
+ "en|US|iso8859-1\0" \
+ "zh|CN|unicode\0"
+
+
+#define TYPE16_STRINGS \
+ "\0" /* nothing */
+
+#define TYPE17_STRINGS_CHANNEL0 \
+ "SOCKET 0 CHANNEL 0 DIMM 0\0" /* location */ \
+ "Bank0\0" /* bank description */ \
+ "Not Set\0" \
+ "Not Set\0" \
+ "Not Set\0" \
+ "Not Set\0"
+
+#define TYPE17_STRINGS_CHANNEL1 \
+ "SOCKET 0 CHANNEL 1 DIMM 0\0" /* location */ \
+ "Bank0\0" \
+ "Not Set\0" \
+ "Not Set\0" \
+ "Not Set\0" \
+ "Not Set\0"
+
+
+#define TYPE19_STRINGS \
+ "\0" /* nothing */
+
+#define TYPE32_STRINGS \
+ "\0" /* nothing */
+
+#define TYPE39_STRINGS \
+ "Not specified\0" /* not specified*/ \
+ "Not specified\0" /* not specified*/ \
+ "Not specified\0" /* not specified*/ \
+ "Not specified\0" /* not specified*/ \
+ "Not specified\0" /* not specified*/ \
+ "Not specified\0" /* not specified*/ \
+ "Not specified\0" /* not specified*/
+
+#define TYPE38_STRINGS \
+ "\0"
+
+//
+// Type definition and contents of the default SMBIOS table.
+// This table covers only the minimum structures required by
+// the SMBIOS specification (section 6.2, version 3.0)
+//
+#pragma pack(1)
+typedef struct {
+ SMBIOS_TABLE_TYPE0 Base;
+ INT8 Strings[sizeof (TYPE0_STRINGS)];
+} ARM_TYPE0;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE1 Base;
+ UINT8 Strings[sizeof (TYPE1_STRINGS)];
+} ARM_TYPE1;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE2 Base;
+ UINT8 Strings[sizeof (TYPE2_STRINGS)];
+} ARM_TYPE2;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE3 Base;
+ UINT8 Strings[sizeof (TYPE3_STRINGS)];
+} ARM_TYPE3;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE4 Base;
+ UINT8 Strings[sizeof (TYPE4_STRINGS)];
+} ARM_TYPE4;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE7 Base;
+ UINT8 Strings[sizeof (TYPE7_L1DATA_STRINGS)];
+} ARM_TYPE7_L1DATA;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE7 Base;
+ UINT8 Strings[sizeof (TYPE7_L1INS_STRINGS)];
+} ARM_TYPE7_L1INS;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE7 Base;
+ UINT8 Strings[sizeof (TYPE7_L2_STRINGS)];
+} ARM_TYPE7_L2;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE7 Base;
+ UINT8 Strings[sizeof (TYPE7_L3_STRINGS)];
+} ARM_TYPE7_L3;
+
+
+typedef struct {
+ SMBIOS_TABLE_TYPE9 Base;
+ UINT8 Strings[sizeof (TYPE9_STRINGS)];
+} ARM_TYPE9;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE9 Base;
+ UINT8 Strings[sizeof (TYPE9_STRINGS_PCIE0X16)];
+} ARM_TYPE9_PCIE0X16;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE9 Base;
+ UINT8 Strings[sizeof (TYPE9_STRINGS_PCIE0X1)];
+} ARM_TYPE9_PCIE0X1;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE9 Base;
+ UINT8 Strings[sizeof (TYPE9_STRINGS_PCIE1X16)];
+} ARM_TYPE9_PCIE1X16;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE9 Base;
+ UINT8 Strings[sizeof (TYPE9_STRINGS_PCIE1X1)];
+} ARM_TYPE9_PCIE1X1;
+
+
+typedef struct {
+ SMBIOS_TABLE_TYPE13 Base;
+ UINT8 Strings[sizeof (TYPE13_STRINGS)];
+} ARM_TYPE13;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE16 Base;
+ UINT8 Strings[sizeof (TYPE16_STRINGS)];
+} ARM_TYPE16;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE17 Base;
+ UINT8 Strings[sizeof (TYPE17_STRINGS_CHANNEL0)];
+} ARM_TYPE17_CHANNEL0;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE17 Base;
+ UINT8 Strings[sizeof (TYPE17_STRINGS_CHANNEL1)];
+} ARM_TYPE17_CHANNEL1;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE19 Base;
+ UINT8 Strings[sizeof (TYPE19_STRINGS)];
+} ARM_TYPE19;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE32 Base;
+ UINT8 Strings[sizeof (TYPE32_STRINGS)];
+} ARM_TYPE32;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE38 Base;
+ UINT8 Strings[sizeof (TYPE38_STRINGS)];
+} ARM_TYPE38;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE39 Base;
+ UINT8 Strings[sizeof (TYPE39_STRINGS)];
+} ARM_TYPE39;
+
+enum SMBIOS_REFRENCE_HANDLES {
+ SMBIOS_HANDLE_L1I = 0x1000,
+ SMBIOS_HANDLE_L1D,
+ SMBIOS_HANDLE_L2,
+ SMBIOS_HANDLE_L3,
+ SMBIOS_HANDLE_MOTHERBOARD,
+ SMBIOS_HANDLE_CHASSIS,
+ SMBIOS_HANDLE_CLUSTER,
+ SMBIOS_HANDLE_MEMORY,
+ SMBIOS_HANDLE_DIMM_0,
+ SMBIOS_HANDLE_DIMM_1
+};
+
+#define SERIAL_LEN 10 //this must be less than the buffer len allocated in the type1 structure
+
+#pragma pack()
+
+//BIOS Information (Type 0)
+ARM_TYPE0 BiosInfo_Type0 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_BIOS_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE0), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED
+ },
+ 1, //Vendor
+ 2, //BiosVersion
+ 0x8800, //BiosSegment
+ 3, //BiosReleaseDate
+ 0xFF, //BiosSize
+ { //BiosCharacteristics
+ 0, // Reserved :2
+ 0, // Unknown :1
+ 0, // BiosCharacteristicsNotSupported :1
+ 0, // IsaIsSupported :1
+ 0, // McaIsSupported :1
+ 0, // EisaIsSupported :1
+ 1, // PciIsSupported :1
+ 0, // PcmciaIsSupported :1
+ 0, // PlugAndPlayIsSupported :1
+ 0, // ApmIsSupported :1
+ 1, // BiosIsUpgradable :1
+ 0, // BiosShadowingAllowed :1
+ 0, // VlVesaIsSupported :1
+ 0, // EscdSupportIsAvailable :1
+ 1, // BootFromCdIsSupported :1
+ 1, // SelectableBootIsSupported :1
+ 0, // RomBiosIsSocketed :1
+ 0, // BootFromPcmciaIsSupported :1
+ 0, // EDDSpecificationIsSupported :1
+ 0, // JapaneseNecFloppyIsSupported :1
+ 0, // JapaneseToshibaFloppyIsSupported :1
+ 0, // Floppy525_360IsSupported :1
+ 0, // Floppy525_12IsSupported :1
+ 0, // Floppy35_720IsSupported :1
+ 0, // Floppy35_288IsSupported :1
+ 0, // PrintScreenIsSupported :1
+ 0, // Keyboard8042IsSupported :1
+ 0, // SerialIsSupported :1
+ 0, // PrinterIsSupported :1
+ 0, // CgaMonoIsSupported :1
+ 0, // NecPc98 :1
+ 0 // ReservedForVendor :3
+ },
+ {
+ 0x03, //BIOSCharacteristicsExtensionBytes[0]
+ 0x0D //BIOSCharacteristicsExtensionBytes[1]
+ },
+ 0xFF, //SystemBiosMajorRelease;
+ 0xFF, //SystemBiosMinorRelease;
+ 0xFF, //EmbeddedControllerFirmwareMajorRelease;
+ 0xFF, //EmbeddedControllerFirmwareMinorRelease;
+ },
+ TYPE0_STRINGS
+};
+
+//System Information (Type 1).
+ARM_TYPE1 SystemInfo_Type1 = {
+ {
+ { // Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, // Type,
+ sizeof (SMBIOS_TABLE_TYPE1), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED // Handle
+ },
+ 1, // Manufacturer
+ 2, // ProductName
+ 3, // Version
+ 4, // SerialNumber
+ { // Uuid
+ 0x12345678, 0x1234, 0x5678, {0x90, 0xab, 0xcd, 0xde, 0xef, 0xaa, 0xbb, 0xcc}
+ },
+ SystemWakeupTypePowerSwitch, // SystemWakeupType
+ 5, // SKUNumber,
+ 6 // Family
+ },
+ TYPE1_STRINGS
+};
+
+//Base Board (or Module) Information (Type 2)
+ARM_TYPE2 BaseboardInfo_Type2 = {
+ {
+ { // Hdr
+ EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // Type,
+ sizeof (SMBIOS_TABLE_TYPE2), // UINT8 Length
+ SMBIOS_HANDLE_MOTHERBOARD // Handle
+ },
+ 1, // BaseBoardManufacturer
+ 2, // BaseBoardProductName
+ 3, // BaseBoardVersion
+ 4, // BaseBoardSerialNumber
+ 5, // BaseBoardAssetTag
+ { // FeatureFlag
+ 1, // Motherboard :1
+ 0, // RequiresDaughterCard :1
+ 0, // Removable :1
+ 1, // Replaceable :1
+ 0, // HotSwappable :1
+ 0 // Reserved :3
+ },
+ 6, // BaseBoardChassisLocation
+ 0, // ChassisHandle;
+ BaseBoardTypeMotherBoard, // BoardType;
+ 0, // NumberOfContainedObjectHandles;
+ {
+ 0
+ } // ContainedObjectHandles[1];
+ },
+ TYPE2_STRINGS
+};
+
+//System Enclosure or Chassis (Type 3)
+ARM_TYPE3 SystemEnclosure_Type3 = {
+ {
+ { // Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE , // Type,
+ sizeof (SMBIOS_TABLE_TYPE3), // UINT8 Length
+ SMBIOS_HANDLE_CHASSIS // Handle
+ },
+ 1, // Manufactrurer
+ MiscChassisTypeMainServerChassis, // Type
+ 2, // Version
+ 3, // SerialNumber
+ 4, // AssetTag
+ ChassisStateSafe, // BootupState
+ ChassisStateSafe, // PowerSupplyState
+ ChassisStateSafe, // ThermalState
+ ChassisSecurityStatusNone, // SecurityState
+ {
+ 0, // OemDefined[0]
+ 0, // OemDefined[1]
+ 0, // OemDefined[2]
+ 0 // OemDefined[3]
+ },
+ 2, // Height
+ 1, // NumberofPowerCords
+ 0, // ContainedElementCount
+ 0, // ContainedElementRecordLength
+ { // ContainedElements[0]
+ {
+ 0, // ContainedElementType
+ 0, // ContainedElementMinimum
+ 0 // ContainedElementMaximum
+ }
+ }
+ },
+ TYPE3_STRINGS
+};
+
+//Processor Infomation (Type 4)
+ARM_TYPE4 ProcessorInfo_Type4 = {
+ {
+ { //Header
+ EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, //Type
+ sizeof (SMBIOS_TABLE_TYPE4), //Length
+ SMBIOS_HANDLE_CLUSTER //Handle
+ },
+ 1, //Socket
+ CentralProcessor, //ProcessorType
+ ProcessorFamilyIndicatorFamily2, //ProcessorFamily
+ 2, //ProcessorManufacture
+ { //ProcessorId
+ { //Signature
+ 0
+ },
+ { //FeatureFlags
+ 0
+ }
+ },
+ 3, //ProcessorVersion
+ { //Voltage
+ 0, 0, 0, 1, 0, 1
+ },
+ 1, //ExternalClock
+ 1, //MaxSpeed
+ 0, //CurrentSpeed
+ 0x41, //Status
+ ProcessorUpgradeUnknown, //ProcessorUpgrade
+ SMBIOS_HANDLE_L1D, //L1Ins
+ SMBIOS_HANDLE_L2, //L1Data
+ SMBIOS_HANDLE_L3, //L2
+ 4, //SerialNumber
+ 5, //AssetTag
+ 6, //PartNumber
+
+ 4, //CoreCount
+ 0, //EnabledCoreCount
+ 0, //ThreadCount
+ 0x00EC, //ProcessorCharacteristics
+
+ ProcessorFamilyARMv8, //ProcessorFamily2
+
+ 0, //CoreCount2
+ 0, //EnabledCoreCount2
+ 0 //ThreadCount2
+ },
+ TYPE4_STRINGS
+};
+
+//Cache Information (Type7) L1 DATA
+ARM_TYPE7_L1DATA L1Data_Type7 = {
+ {
+ { //Header
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type
+ sizeof (SMBIOS_TABLE_TYPE7), //Length
+ SMBIOS_HANDLE_L1D //Handle
+ },
+ 1, //SocketDesignation
+ 0x0180, //CacheConfiguration
+ 0, //MaximumCacheSize
+ 0, //InstalledSize
+ { //SupportedSRAMType
+ 0, 0, 0, 0, 0, 1, 0, 0
+ },
+ { //CurrentSRAMType
+ 0, 0, 0, 0, 0, 1, 0, 0
+ },
+ 0, //CacheSpeed
+ CacheErrorSingleBit, //ErrorCorrectionType
+ CacheTypeData, //SystemCacheType
+ CacheAssociativity8Way, //Associativity
+ 128,
+ 128
+ },
+ TYPE7_L1DATA_STRINGS
+};
+
+//Cache Information (Type7) L1 INS
+ARM_TYPE7_L1INS L1Ins_Type7 = {
+ {
+ { //Header
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type
+ sizeof (SMBIOS_TABLE_TYPE7), //Length
+ SMBIOS_HANDLE_L1I //Handle
+ },
+ 1, //SocketDesignation
+ 0x0180, //CacheConfiguration
+ 0, //MaximumCacheSize
+ 0, //InstalledSize
+ { //SupportedSRAMType
+ 0, 0, 0, 0, 0, 1, 0, 0
+ },
+ { //CurrentSRAMType
+ 0, 0, 0, 0, 0, 1, 0, 0
+ },
+ 0, //CacheSpeed
+ CacheErrorParity, //ErrorCorrectionType
+ CacheTypeInstruction, //SystemCacheType
+ CacheAssociativity8Way, //Associativity
+ 128,
+ 128
+ },
+ TYPE7_L1INS_STRINGS
+};
+
+//Cache Information (Type7) L2
+ARM_TYPE7_L2 L2_Type7 = {
+ {
+ { //Header
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type
+ sizeof (SMBIOS_TABLE_TYPE7), //Length
+ SMBIOS_HANDLE_L2 //Handle
+ },
+ 1, //SocketDesignation
+ 0x0281, //CacheConfiguration
+ 0, //MaximumCacheSize
+ 0, //InstalledSize
+ { //SupportedSRAMType
+ 0, 0, 0, 0, 0, 1, 0, 0
+ },
+ { //CurrentSRAMType
+ 0, 0, 0, 0, 0, 1, 0, 0
+ },
+ 0, //CacheSpeed
+ CacheErrorSingleBit, //ErrorCorrectionType
+ CacheTypeUnified, //SystemCacheType
+ CacheAssociativity8Way, //Associativity
+ 4096,
+ 4096
+ },
+ TYPE7_L2_STRINGS
+};
+
+//Cache Information (Type7) L3
+ARM_TYPE7_L3 L3_Type7 = {
+ {
+ { //Header
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type
+ sizeof (SMBIOS_TABLE_TYPE7), //Length
+ SMBIOS_HANDLE_L3 //Handle
+ },
+ 1, //SocketDesignation
+ 0x0281, //CacheConfiguration
+ 0, //MaximumCacheSize
+ 0, //InstalledSize
+ { //SupportedSRAMType
+ 0, 0, 0, 0, 0, 1, 0, 0
+ },
+ { //CurrentSRAMType
+ 0, 0, 0, 0, 0, 1, 0, 0
+ },
+ 0, //CacheSpeed
+ CacheErrorSingleBit, //ErrorCorrectionType
+ CacheTypeUnified, //SystemCacheType
+ CacheAssociativity8Way, //Associativity
+ 4096,
+ 4096
+ },
+ TYPE7_L3_STRINGS
+};
+
+//PCIE0_X16 (Type 9)
+ARM_TYPE9_PCIE0X16 Pcie0X16_Type9 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED
+ },
+ 1,
+ SlotTypePciX,
+ SlotDataBusWidth16X,
+ SlotUsageInUse,
+ SlotLengthLong,
+ 0,
+ {0, 0, 1, 1, 0, 0, 0, 0}, //unknown
+ {1, 0, 0, 0, 0}, //PME and SMBUS
+ 0,
+ 0,
+ 0,
+ },
+ TYPE9_STRINGS_PCIE0X16
+};
+
+//PCIE0_X1 (Type 9)
+ARM_TYPE9_PCIE0X1 Pcie0X1_Type9 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED
+ },
+ 1,
+ SlotTypePciX,
+ SlotDataBusWidth1X,
+ SlotUsageAvailable,
+ SlotLengthShort,
+ 1,
+ {0, 0, 1, 1, 0, 0, 0, 0}, //unknown
+ {1, 0, 0, 0, 0}, //PME and SMBUS
+ 0xFF,
+ 0xFF,
+ 0xFF,
+ },
+ TYPE9_STRINGS_PCIE0X1
+};
+
+//PCIE1_X16 (Type 9)
+ARM_TYPE9_PCIE1X16 Pcie1X16_Type9 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED
+ },
+ 1,
+ SlotTypePciX,
+ SlotDataBusWidth16X,
+ SlotUsageAvailable,
+ SlotLengthLong,
+ 2,
+ {0, 0, 1, 1, 0, 0, 0, 0}, //unknown
+ {1, 0, 0, 0, 0}, //PME and SMBUS
+ 0xFF,
+ 0xFF,
+ 0xFF,
+ },
+ TYPE9_STRINGS_PCIE1X16
+};
+
+//PCIE1_X1 (Type 9)
+ARM_TYPE9_PCIE1X1 Pcie1X1_Type9 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED
+ },
+ 1,
+ SlotTypePciX,
+ SlotDataBusWidth1X,
+ SlotUsageAvailable,
+ SlotLengthShort,
+ 3,
+ {0, 0, 1, 1, 0, 0, 0, 0}, //unknown
+ {1, 0, 0, 0, 0}, //PME and SMBUS
+ 0xFF,
+ 0xFF,
+ 0xFF,
+ },
+ TYPE9_STRINGS_PCIE1X1
+};
+
+//Bios Language Information (Type13)
+ARM_TYPE13 BiosLangInfo_Type13 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE13), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED
+ },
+ 2,
+ 0,
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ 2
+ },
+ TYPE13_STRINGS
+};
+
+//Physical Memory Array (Type 16)
+ARM_TYPE16 MemArray_Type16 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE16), // UINT8 Length
+ SMBIOS_HANDLE_MEMORY
+ },
+ MemoryArrayLocationSystemBoard,
+ MemoryArrayUseSystemMemory,
+ MemoryErrorCorrectionNone,
+ 0x1000000, //16G
+ 0xFFFE,
+ 2
+ },
+ TYPE16_STRINGS
+};
+
+//Memory Device (Type17)
+ARM_TYPE17_CHANNEL0 MemDev_Type17_0 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_MEMORY_DEVICE, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE17), // UINT8 Length
+ SMBIOS_HANDLE_DIMM_0
+ },
+ SMBIOS_HANDLE_MEMORY, //array to which this module belongs
+ 0xFFFE, //no errors
+ 64, //single DIMM, no ECC is 64bits (for ecc this would be 72)
+ 64, //data width of this device (64-bits)
+ 0x4000, //16GB
+ 0x09, //FormFactor
+ 0, //not part of a set
+ 1, //right side of board
+ 2, //bank 0
+ MemoryTypeDdr4, //LP DDR4
+ {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, //unbuffered
+ 2400, //2400Mhz DDR
+ 3, //Manufacturer
+ 4, //serial
+ 5, //asset tag
+ 6, //part number
+ 0, //attrbute
+ 0x2000, // 8G
+ 2400, //2400MHz
+ 1500, //Max V
+ 1500, //Max V
+ 1500, //Configure V
+ },
+ TYPE17_STRINGS_CHANNEL0
+};
+
+//Memory Device (Type17)
+ARM_TYPE17_CHANNEL1 MemDev_Type17_1 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_MEMORY_DEVICE, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE17), // UINT8 Length
+ SMBIOS_HANDLE_DIMM_1
+ },
+ SMBIOS_HANDLE_MEMORY, //array to which this module belongs
+ 0xFFFE, //no errors
+ 64, //single DIMM, no ECC is 64bits (for ecc this would be 72)
+ 64, //data width of this device (64-bits)
+ 0x2000, //8GB
+ 0x09, //FormFactor
+ 0, //not part of a set
+ 1, //right side of board
+ 2, //bank 0
+ MemoryTypeDdr4, //LP DDR4
+ {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0}, //unbuffered
+ 2400, //2400Mhz DDR
+ 3, //varies between diffrent production runs
+ 4, //serial
+ 5, //asset tag
+ 6, //part number
+ 0, //attrbute
+ 0x4000, // 16G
+ 2400, //2400MHz
+ 1500, //Max V
+ 1500, //Max V
+ 1500, //Configure V
+ },
+ TYPE17_STRINGS_CHANNEL1
+};
+
+//Memory Array Mapped Address (Type 19)
+ARM_TYPE19 MemArrayMapAddr_Type19 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE19), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED
+ },
+ 0,
+ 0x1000000, //16G
+ SMBIOS_HANDLE_MEMORY, //handle
+ 2,
+ 0, //starting addr of first 2GB
+ 0, //ending addr of first 2GB
+ },
+ TYPE19_STRINGS
+};
+
+//System Boot Information (Type 32)
+ARM_TYPE32 SystemBoot_Type32 = {
+ {
+ {
+ EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // Type,
+ sizeof (SMBIOS_TABLE_TYPE32), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED
+ },
+ { // Reserved[6]
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0
+ },
+ BootInformationStatusNoError // BootInformationStatus
+ },
+ TYPE32_STRINGS
+};
+
+VOID *DefaultCommonTables[]=
+{
+ &BiosInfo_Type0,
+ &SystemInfo_Type1,
+ &BaseboardInfo_Type2,
+ &SystemEnclosure_Type3,
+ &ProcessorInfo_Type4,
+ &L1Data_Type7,
+ &L1Ins_Type7,
+ &L2_Type7,
+ &L3_Type7,
+ &Pcie0X16_Type9,
+ &Pcie0X1_Type9,
+ &Pcie1X16_Type9,
+ &Pcie1X1_Type9,
+ &MemArray_Type16,
+ &MemDev_Type17_0,
+ &MemDev_Type17_1,
+ &MemArrayMapAddr_Type19,
+ &BiosLangInfo_Type13,
+ &SystemBoot_Type32,
+ NULL
+};
+
+
+/**
+ Installed a whole table worth of structructures.
+
+ @param[in] Smbios The Pointer of Smbios Protocol.
+
+ @retval EFI_SUCCESS Table data successfully installed.
+ @retval Other Table data was not installed.
+
+**/
+EFI_STATUS
+InstallStructures (
+ IN EFI_SMBIOS_PROTOCOL *Smbios,
+ IN VOID *DefaultTables[]
+ )
+{
+ EFI_STATUS Status;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ UINT32 TableEntry;
+
+ Status = EFI_SUCCESS;
+
+ for ( TableEntry =0; DefaultTables[TableEntry] != NULL; TableEntry++)
+ {
+ SmbiosHandle = ((EFI_SMBIOS_TABLE_HEADER *)DefaultTables[TableEntry])->Handle;
+ Status = Smbios->Add (
+ Smbios,
+ NULL,
+ &SmbiosHandle,
+ (EFI_SMBIOS_TABLE_HEADER *) DefaultTables[TableEntry]
+ );
+ if (EFI_ERROR (Status))
+ break;
+ }
+
+ return Status;
+}
+
+
+/**
+ Installed All SMBIOS information.
+
+ @param[in] Smbios The Pointer of Smbios Protocol.
+
+ @retval EFI_SUCCESS SMBIOS information successfully installed.
+ @retval Other SMBIOS information was not installed.
+
+**/
+STATIC
+EFI_STATUS
+InstallAllStructures (
+ IN EFI_SMBIOS_PROTOCOL *Smbios
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+
+ Status = InstallStructures (Smbios, DefaultCommonTables);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+
+/**
+ Find the smbios protocol and installed SMBIOS information
+ for ARM platforms.
+
+ @param[in] ImageHandle Module's image handle.
+ @param[in] SystemTable Pointer of EFI_SYSTEM_TABLE.
+
+ @retval EFI_SUCCESS Smbios data successfully installed.
+ @retval Other Smbios data was not installed.
+
+**/
+EFI_STATUS
+EFIAPI
+SmbiosTablePublishEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_SMBIOS_PROTOCOL *Smbios;
+
+ //
+ // Find the SMBIOS protocol
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiSmbiosProtocolGuid,
+ NULL,
+ (VOID **)&Smbios
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = InstallAllStructures (Smbios);
+
+ return Status;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v5 04/10] Silicon/Phytium: Added PciSegmentLib to FT2000/4
2021-09-09 9:47 [PATCH v5 00/10] Added support for FT2000/4 chip Ling Jia
` (2 preceding siblings ...)
2021-09-09 9:47 ` [PATCH v5 03/10] Silicon/Phytium: Added SMBIOS " Ling Jia
@ 2021-09-09 9:47 ` Ling Jia
2021-09-09 9:47 ` [PATCH v5 05/10] Silicon/Phytium: Added PciHostBridgeLib " Ling Jia
2021-09-09 10:22 ` [PATCH v5 00/10] Added support for FT2000/4 chip Leif Lindholm
5 siblings, 0 replies; 7+ messages in thread
From: Ling Jia @ 2021-09-09 9:47 UTC (permalink / raw)
To: devel; +Cc: Leif Lindholm, Ling Jia
The PCI Segment Library for Phytium platform.
with multiple RCs.
Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Platform/Phytium/DurianPkg/DurianPkg.dsc | 9 +-
Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf | 28 +
Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c | 1434 ++++++++++++++++++++
3 files changed, 1464 insertions(+), 7 deletions(-)
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/DurianPkg/DurianPkg.dsc
index 28e52e15e3..093b2cd9db 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.dsc
+++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc
@@ -35,7 +35,8 @@
PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf
[LibraryClasses.common.DXE_DRIVER]
-
+ # Pci dependencies
+ PciSegmentLib|Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf
################################################################################
#
@@ -262,12 +263,6 @@
MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
- #
- # PCI Support
- #
- ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
- MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
-
#
# The following 2 module perform the same work except one operate variable.
# Only one of both should be put into fdf.
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf
new file mode 100644
index 0000000000..67360016ef
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf
@@ -0,0 +1,28 @@
+#/** @file
+# PCI Segment Library for Phytium platform with multiple RCs.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PciSegmentLib
+ FILE_GUID = fa5173d2-40fe-11eb-9b2f-cb20dc669fd3
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciSegmentLib
+
+[Sources]
+ PciSegmentLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c
new file mode 100644
index 0000000000..273443fd5d
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c
@@ -0,0 +1,1434 @@
+/** @file
+ PCI Segment Library for SoC with multiple RCs.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+
+#define PCI_SEG_CONFIG_BASE 0x40000000
+#define PCIE_BIF_MODE 0x29100800
+
+typedef enum {
+ PciCfgWidthUint8 = 0,
+ PciCfgWidthUint16,
+ PciCfgWidthUint32,
+ PciCfgWidthMax
+} PCI_CFG_WIDTH;
+
+/**
+ Assert the validity of a PCI Segment address.
+ A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
+
+ @param[in] A The address to validate.
+ @param[in] M Additional bits to assert to be zero.
+
+**/
+#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
+ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
+
+
+#define EXTRACT_PCIE_ADDRESS(Address, Bus, Device, Function) \
+{ \
+ (Bus) = (((Address) >> 20) & 0xff); \
+ (Device) = (((Address) >> 15) & 0x1f); \
+ (Function) = (((Address) >> 12) & 0x07); \
+}
+
+
+/**
+ This function geted the config base of PCI device.
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The value of the config base of PCI device.
+
+**/
+STATIC
+UINT64
+PciSegmentLibGetConfigBase (
+ IN UINT64 Address
+ )
+{
+ UINT8 Bus;
+ UINT8 Device;
+ UINT8 Function;
+ UINT8 RootPortCount;
+ UINT8 Peu0RootPortCount;
+ UINT8 Peu1RootPortCount;
+ UINT32 BifMode;
+ UINT32 Peu0BifMode;
+ UINT32 Peu1BifMode;
+
+ EXTRACT_PCIE_ADDRESS (Address, Bus, Device, Function);
+ BifMode = MmioRead32 (PCIE_BIF_MODE);
+ Peu0BifMode = BifMode & 0x3;
+ Peu1BifMode = (BifMode >> 2) & 0x3;
+
+ if ((Peu0BifMode == 1)) {
+ Peu0RootPortCount = 3;
+ } else {
+ Peu0RootPortCount = 2;
+ }
+
+ if ((Peu1BifMode == 1)) {
+ Peu1RootPortCount = 3;
+ } else {
+ Peu1RootPortCount = 2;
+ }
+ RootPortCount = Peu0RootPortCount + Peu1RootPortCount;
+ //ignore device > 0 or function > 0 on root port
+ if (RootPortCount == 4) {
+ if ((Bus == 1) || (Bus == 2) || (Bus == 3) || (Bus == 4)) {
+ if (Device != 0 || Function != 0) {
+ return 0xFFFFFFFF;
+ }
+ return PCI_SEG_CONFIG_BASE;
+ }
+ } else if (RootPortCount == 5) {
+ if ((Bus == 1) || (Bus == 2) || (Bus == 3) || (Bus == 4) || (Bus == 5)) {
+ if (Device != 0 || Function != 0) {
+ return 0xFFFFFFFF;
+ }
+ return PCI_SEG_CONFIG_BASE;
+ }
+ } else if (RootPortCount == 6) {
+ if ((Bus == 1) || (Bus == 2) || (Bus == 3) || (Bus == 4) || (Bus == 5) || (Bus == 6)) {
+ if (Device != 0 || Function != 0) {
+ return 0xFFFFFFFF;
+ }
+ return PCI_SEG_CONFIG_BASE;
+ }
+ }
+
+ return PCI_SEG_CONFIG_BASE;
+}
+
+/**
+ Internal worker function to read a PCI configuration register.
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param[in] Width The width of data to read
+
+ @return The value read from the PCI configuration register.
+
+**/
+STATIC
+UINT32
+PciSegmentLibReadWorker (
+ IN UINT64 Address,
+ IN PCI_CFG_WIDTH Width
+ )
+{
+ UINT64 Base;
+
+ Base = PciSegmentLibGetConfigBase (Address);
+ if (Base == 0xFFFFFFFF) {
+ return 0xFFFFFFFF;
+ }
+
+ switch (Width) {
+ case PciCfgWidthUint8:
+ return MmioRead8 (Base + (UINT32)Address);
+ case PciCfgWidthUint16:
+ return MmioRead16 (Base + (UINT32)Address);
+ case PciCfgWidthUint32:
+ return MmioRead32 (Base + (UINT32)Address);
+ default:
+ ASSERT (FALSE);
+ }
+
+ return 0;
+}
+
+
+/**
+ Internal worker function to writes a PCI configuration register.
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param[in] Width The width of data to write
+ @param[in] Data The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+STATIC
+UINT32
+PciSegmentLibWriteWorker (
+ IN UINT64 Address,
+ IN PCI_CFG_WIDTH Width,
+ IN UINT32 Data
+ )
+{
+ UINT64 Base;
+
+ Base = PciSegmentLibGetConfigBase (Address);
+ if (Base == 0xFFFFFFFF) {
+ return 0xFFFFFFFF;
+ }
+
+ switch (Width) {
+ case PciCfgWidthUint8:
+ MmioWrite8 (Base + (UINT32)Address, Data);
+ break;
+ case PciCfgWidthUint16:
+ MmioWrite16 (Base + (UINT32)Address, Data);
+ break;
+ case PciCfgWidthUint32:
+ MmioWrite32 (Base + (UINT32)Address, Data);
+ break;
+ default:
+ ASSERT (FALSE);
+ }
+
+ return Data;
+}
+
+/**
+ Register a PCI device so PCI configuration registers may be accessed after
+ SetVirtualAddressMap().
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @retval RETURN_SUCCESS The PCI device was registered for runtime access.
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function
+ after ExitBootServices().
+ @retval RETURN_UNSUPPORTED The resources required to access the PCI device
+ at runtime could not be mapped.
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
+ complete the registration.
+
+**/
+RETURN_STATUS
+EFIAPI
+PciSegmentRegisterForRuntimeAccess (
+ IN UINTN Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+ return RETURN_UNSUPPORTED;
+}
+
+/**
+ Reads an 8-bit PCI configuration register.
+
+ Reads and returns the 8-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function,
+ and Register.
+
+ @return The 8-bit PCI configuration register specified by Address.
+
+**/
+UINT8
+EFIAPI
+PciSegmentRead8 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+ return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8);
+}
+
+/**
+ Writes an 8-bit PCI configuration register.
+
+ Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentWrite8 (
+ IN UINT64 Address,
+ IN UINT8 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+ return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value);
+}
+
+/**
+ Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentOr8 (
+ IN UINT64 Address,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentAnd8 (
+ IN UINT64 Address,
+ IN UINT8 AndData
+ )
+{
+ return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
+ followed a bitwise OR with another 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentAndThenOr8 (
+ IN UINT64 Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to read.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldRead8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 8-bit register is returned.
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldWrite8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ )
+{
+ return PciSegmentWrite8 (
+ Address,
+ BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (
+ Address,
+ BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 8-bit register.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldAnd8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ )
+{
+ return PciSegmentWrite8 (
+ Address,
+ BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldAndThenOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (
+ Address,
+ BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a 16-bit PCI configuration register.
+
+ Reads and returns the 16-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 16-bit PCI configuration register specified by Address.
+
+**/
+UINT16
+EFIAPI
+PciSegmentRead16 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
+
+ return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16);
+}
+
+/**
+ Writes a 16-bit PCI configuration register.
+
+ Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT16
+EFIAPI
+PciSegmentWrite16 (
+ IN UINT64 Address,
+ IN UINT16 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
+
+ return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value);
+}
+
+/**
+ Performs a bitwise OR of a 16-bit PCI configuration register with
+ a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function and
+ Register.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentOr16 (
+ IN UINT64 Address,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentAnd16 (
+ IN UINT64 Address,
+ IN UINT16 AndData
+ )
+{
+ return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
+ followed a bitwise OR with another 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentAndThenOr16 (
+ IN UINT64 Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to read.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldRead16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 16-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param[in] Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldWrite16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ )
+{
+ return PciSegmentWrite16 (
+ Address,
+ BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (
+ Address,
+ BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
+ and writes the result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+ Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ The ordinal of the least significant bit in a byte is bit 0.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ The ordinal of the most significant bit in a byte is bit 7.
+ @param[in] AndData The value to AND with the read value from the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldAnd16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ )
+{
+ return PciSegmentWrite16 (
+ Address,
+ BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldAndThenOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (
+ Address,
+ BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a 32-bit PCI configuration register.
+
+ Reads and returns the 32-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function,
+ and Register.
+
+ @return The 32-bit PCI configuration register specified by Address.
+
+**/
+UINT32
+EFIAPI
+PciSegmentRead32 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
+
+ return PciSegmentLibReadWorker (Address, PciCfgWidthUint32);
+}
+
+/**
+ Writes a 32-bit PCI configuration register.
+
+ Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param[in] Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT32
+EFIAPI
+PciSegmentWrite32 (
+ IN UINT64 Address,
+ IN UINT32 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
+
+ return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value);
+}
+
+/**
+ Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentOr32 (
+ IN UINT64 Address,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function,
+ and Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentAnd32 (
+ IN UINT64 Address,
+ IN UINT32 AndData
+ )
+{
+ return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
+ followed a bitwise OR with another 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function,
+ and Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentAndThenOr32 (
+ IN UINT64 Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to read.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldRead32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 32-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldWrite32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 32-bit register.
+
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
+ AND between the read result and the value specified by AndData, and writes the result
+ to the 32-bit PCI configuration register specified by Address. The value written to
+ the PCI configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in AndData are stripped.
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldAnd32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldAndThenOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a range of PCI configuration registers into a caller supplied buffer.
+
+ Reads the range of PCI configuration registers specified by StartAddress and
+ Size into the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be read. Size is
+ returned. When possible 32-bit PCI configuration read cycles are used to read
+ from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
+ and 16-bit PCI configuration read cycles may be used at the beginning and the
+ end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param[in] StartAddress The starting address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+ @param[in] Size The size in bytes of the transfer.
+ @param[in] Buffer The pointer to a buffer receiving the data read.
+
+ @return Size
+
+**/
+UINTN
+EFIAPI
+PciSegmentReadBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+ if (Size == 0) {
+ return Size;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ //
+ // Save Size for return
+ //
+ ReturnValue = Size;
+
+ if ((StartAddress & BIT0) != 0) {
+ //
+ // Read a byte if StartAddress is byte aligned,
+ // Volatile ensure that the latest values are read every time.
+ //
+ *(UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8 *)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ //
+ // Read a word if StartAddress is word aligned
+ //
+ WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ //
+ // Read as many double words as possible
+ //
+ WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32 *)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ //
+ // Read the last remaining word if exist
+ //
+ WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ //
+ // Read the last remaining byte if exist
+ //
+ *(UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
+ }
+
+ return ReturnValue;
+}
+
+
+/**
+ Copies the data in a caller supplied buffer to a specified range of PCI
+ configuration space.
+
+ Writes the range of PCI configuration registers specified by StartAddress and
+ Size from the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be written. Size is
+ returned. When possible 32-bit PCI configuration write cycles are used to
+ write from StartAdress to StartAddress + Size. Due to alignment restrictions,
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
+ and the end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param[in] StartAddress The starting address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+ @param[in] Size The size in bytes of the transfer.
+ @param[in] Buffer The pointer to a buffer containing the data to write.
+
+ @return The parameter of Size.
+
+**/
+UINTN
+EFIAPI
+PciSegmentWriteBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+ if (Size == 0) {
+ return 0;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ //
+ // Save Size for return
+ //
+ ReturnValue = Size;
+
+ if ((StartAddress & BIT0) != 0) {
+ //
+ // Write a byte if StartAddress is byte aligned
+ //
+ PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8 *)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ //
+ // Write a word if StartAddress is word aligned
+ //
+ PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ //
+ // Write as many double words as possible
+ //
+ PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32 *)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ //
+ // Write the last remaining word if exist
+ //
+ PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ //
+ // Write the last remaining byte if exist
+ //
+ PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer);
+ }
+
+ return ReturnValue;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v5 05/10] Silicon/Phytium: Added PciHostBridgeLib to FT2000/4
2021-09-09 9:47 [PATCH v5 00/10] Added support for FT2000/4 chip Ling Jia
` (3 preceding siblings ...)
2021-09-09 9:47 ` [PATCH v5 04/10] Silicon/Phytium: Added PciSegmentLib " Ling Jia
@ 2021-09-09 9:47 ` Ling Jia
2021-09-09 10:22 ` [PATCH v5 00/10] Added support for FT2000/4 chip Leif Lindholm
5 siblings, 0 replies; 7+ messages in thread
From: Ling Jia @ 2021-09-09 9:47 UTC (permalink / raw)
To: devel; +Cc: Leif Lindholm, Ling Jia
The Pci host bridge library is mainly
to get Pci bridge information.
Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Platform/Phytium/DurianPkg/DurianPkg.dsc | 9 +
Platform/Phytium/DurianPkg/DurianPkg.fdf | 6 +
Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 47 +++++
Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 181 ++++++++++++++++++++
4 files changed, 243 insertions(+)
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/DurianPkg/DurianPkg.dsc
index 093b2cd9db..3a9bc2289c 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.dsc
+++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc
@@ -37,6 +37,7 @@
[LibraryClasses.common.DXE_DRIVER]
# Pci dependencies
PciSegmentLib|Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf
+ PciHostBridgeLib|Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
################################################################################
#
@@ -263,6 +264,14 @@
MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ #
+ # PCI Support
+ #
+ ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+ MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
#
# The following 2 module perform the same work except one operate variable.
# Only one of both should be put into fdf.
diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/DurianPkg/DurianPkg.fdf
index 3106a43fb7..a443d0f3a4 100644
--- a/Platform/Phytium/DurianPkg/DurianPkg.fdf
+++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf
@@ -135,6 +135,12 @@ READ_LOCK_STATUS = TRUE
INF FatPkg/EnhancedFatDxe/Fat.inf
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ #
+ # PCI Support
+ #
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+
#
# SATA Controller
#
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
new file mode 100644
index 0000000000..0e6f0797b0
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
@@ -0,0 +1,47 @@
+#/** @file
+# PCI Host Bridge Library instance for Phytium SOC.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PciHostBridgeLib
+ FILE_GUID = f965de0e-40fe-11eb-8290-3f9d1f895a80
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER
+
+#
+# The following information is for reference only and not required by the build
+# tools.
+#
+# VALID_ARCHITECTURES = ARM AARCH64
+#
+
+[Sources]
+ PciHostBridgeLib.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
+
+[LibraryClasses]
+ DebugLib
+
+[Guids]
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdPciBusMin
+ gArmTokenSpaceGuid.PcdPciBusMax
+ gArmTokenSpaceGuid.PcdPciIoBase
+ gArmTokenSpaceGuid.PcdPciIoSize
+ gArmTokenSpaceGuid.PcdPciMmio32Base
+ gArmTokenSpaceGuid.PcdPciMmio32Size
+ gArmTokenSpaceGuid.PcdPciMmio64Base
+ gArmTokenSpaceGuid.PcdPciMmio64Size
diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
new file mode 100644
index 0000000000..8ed3516749
--- /dev/null
+++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -0,0 +1,181 @@
+/** @file
+ PCI host bridge library instance for Phytium SOC.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/PciHostBridgeLib.h>
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+#include <Protocol/PciRootBridgeIo.h>
+
+#pragma pack(1)
+
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+
+#pragma pack ()
+
+#define END_DEVICE_PATH_DEF { END_DEVICE_PATH_TYPE, \
+ END_ENTIRE_DEVICE_PATH_SUBTYPE, \
+ { END_DEVICE_PATH_LENGTH, 0 } \
+ }
+
+#define ACPI_DEVICE_PATH_DEF(UID) {{ ACPI_DEVICE_PATH, ACPI_DP, \
+ { (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \
+ (UINT8) (sizeof (ACPI_HID_DEVICE_PATH) >> 8)} \
+ }, \
+ EISA_PNP_ID (0x0A03), UID \
+ }
+
+STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
+ {
+ ACPI_DEVICE_PATH_DEF (0),
+ END_DEVICE_PATH_DEF
+ },
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED
+CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
+ L"Mem", L"I/O", L"Bus"
+};
+
+STATIC PCI_ROOT_BRIDGE mRootBridge = {
+ 0, // Segment
+ 0, // Supports
+ 0, // Attributes
+ TRUE, // DmaAbove4G
+ FALSE, // NoExtendedConfigSpace
+ FALSE, // ResourceAssigned
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+ {
+ // Bus
+ FixedPcdGet32 (PcdPciBusMin),
+ FixedPcdGet32 (PcdPciBusMax)
+ }, {
+ // Io
+ FixedPcdGet64 (PcdPciIoBase),
+ FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1
+ }, {
+ // Mem
+ FixedPcdGet32 (PcdPciMmio32Base),
+ FixedPcdGet32 (PcdPciMmio32Base) + (FixedPcdGet32 (PcdPciMmio32Size) - 1)
+ //0x7FFFFFFF
+ }, {
+ // MemAbove4G
+ FixedPcdGet64 (PcdPciMmio64Base),
+ FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1
+ }, {
+ // PMem
+ MAX_UINT64,
+ 0
+ }, {
+ // PMemAbove4G
+ MAX_UINT64,
+ 0
+ },
+ (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath
+};
+
+/**
+ Return all the root bridge instances in an array.
+
+ @param[out] Count Return the count of root bridge instances.
+
+ @return All the root bridge instances in an array.
+ The array should be passed into PciHostBridgeFreeRootBridges()
+ when it's not used.
+
+**/
+PCI_ROOT_BRIDGE *
+EFIAPI
+PciHostBridgeGetRootBridges (
+ OUT UINTN *Count
+ )
+{
+ *Count = 1;
+ return &mRootBridge;
+}
+
+
+/**
+ Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
+
+ @param[in] Bridges The root bridge instances array.
+ @param[in] Count The count of the array.
+
+**/
+VOID
+EFIAPI
+PciHostBridgeFreeRootBridges (
+ IN PCI_ROOT_BRIDGE *Bridges,
+ IN UINTN Count
+ )
+{
+
+}
+
+
+/**
+ Inform the platform that the resource conflict happens.
+
+ @param[in] HostBridgeHandle Handle of the Host Bridge.
+ @param[in] Configuration Pointer to PCI I/O and PCI memory resource
+ descriptors. The Configuration contains the resources
+ for all the root bridges. The resource for each root
+ bridge is terminated with END descriptor and an
+ additional END is appended indicating the end of the
+ entire resources. The resource descriptor field
+ values follow the description in
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ SubmitResources().
+
+**/
+VOID
+EFIAPI
+PciHostBridgeResourceConflict (
+ IN EFI_HANDLE HostBridgeHandle,
+ IN VOID *Configuration
+ )
+{
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ BOOLEAN IsPrefetchable;
+
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
+ while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
+ for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
+ ASSERT (Descriptor->ResType <
+ ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr));
+ DEBUG ((DEBUG_INFO, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
+ mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
+ Descriptor->AddrLen,
+ Descriptor->AddrRangeMax
+ ));
+ if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
+
+ IsPrefetchable = (Descriptor->SpecificFlag &
+ EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0;
+
+ DEBUG ((DEBUG_INFO, " Granularity/SpecificFlag = %ld / %02x%s\n",
+ Descriptor->AddrSpaceGranularity,
+ Descriptor->SpecificFlag,
+ (IsPrefetchable) ? L" (Prefetchable)" : L""
+ ));
+ }
+ }
+ //
+ // Skip the end descriptor for root bridge
+ //
+ ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) (
+ (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
+ );
+ }
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v5 00/10] Added support for FT2000/4 chip
2021-09-09 9:47 [PATCH v5 00/10] Added support for FT2000/4 chip Ling Jia
` (4 preceding siblings ...)
2021-09-09 9:47 ` [PATCH v5 05/10] Silicon/Phytium: Added PciHostBridgeLib " Ling Jia
@ 2021-09-09 10:22 ` Leif Lindholm
5 siblings, 0 replies; 7+ messages in thread
From: Leif Lindholm @ 2021-09-09 10:22 UTC (permalink / raw)
To: Ling Jia; +Cc: devel
Hi Ling,
This set *still* does not contain the changes I included in my replies
to v3 and v4 that let it build against current edk2 master.
Please include those changes, verify the platform builds against
current edk2 master, and resubmit a v6.
Best Regards,
Leif
On Thu, Sep 09, 2021 at 17:47:09 +0800, Ling Jia wrote:
> This series added packages to support FT2000/4 chip.
> Platform/Phytium: Added DurianPkg, include DurianPkg.dsc and DurianPkg.fdf.
> Silicon/Phytium: Added FT2000-4Pkg and PhytiumCommonPkg.
>
> The modules could be runed at the silicon of FT2000/4.
> They supported Acpi parameter configuration, Pci bus scaning,
> flash read-write and erase abd operating system boot function.
> Maintainers.txt: Added maintainers and reviewers for the DurianPkg.
>
> The public git repository is :
> https://github.com/jialing2020/edk2-platforms/tree/Phytium_Opensource_For_FT2000-4_v5
>
> About patch 7:
> This is a set of special communication protocol for
> ft2000/4 chip QSPI controller. It has twoaccess modes:
> direct address access and command port access.
> At present, the read and write operations of flash
> are completed through direct address access
> (address mapping has been done on the hardware,
> and the write access is configured to put the data
> into the buffer first and merge and write multiple times).
> The erase operation is completed through command port access.
> Every time you operate norflash, you need to configure the
> command code, command format and other information through
> the command port register (such as erasing 0xd8), if the
> command requires an address, fill in the address port register;
> if the command requires data, access it in the order of high-
> order data register and low-order data register.
> Once the low-order data register is accessed, trigger
> the controller to send a command to flash.
>
> Ling Jia (10):
> Silicon/Phytium: Added PlatformLib to FT2000/4
> Silicon/Phytium: Added Acpi support to FT2000/4
> Silicon/Phytium: Added SMBIOS support to FT2000/4
> Silicon/Phytium: Added PciSegmentLib to FT2000/4
> Silicon/Phytium: Added PciHostBridgeLib to FT2000/4
> Silicon/Phytium: Added Spi driver support to FT2000/4
> Silicon/Phytium: Added flash driver support to Phytium Silicon
> Silicon/Phytium: Added fvb driver for norflash
> Silicon/Phytium: Added Rtc driver to FT2000/4
> Maintainers.txt: Added maintainers and reviewers for the DurianPkg
>
> Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec | 52 +
> Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc | 345 +++++
> Platform/Phytium/DurianPkg/DurianPkg.dsc | 331 +++++
> Platform/Phytium/DurianPkg/DurianPkg.fdf | 235 ++++
> Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf | 56 +
> Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 47 +
> Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf | 44 +
> Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf | 48 +
> Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 47 +
> Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf | 28 +
> Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.inf | 55 +
> Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.inf | 39 +
> Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 53 +
> Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf | 61 +
> Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h | 59 +
> Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h | 95 ++
> Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.h | 24 +
> Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h | 104 ++
> Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h | 80 ++
> Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol.h | 74 +
> Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiProtocol.h | 51 +
> Silicon/Phytium/PhytiumCommonPkg/Include/SystemServiceInterface.h | 112 ++
> Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 943 +++++++++++++
> Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c | 202 +++
> Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c | 412 ++++++
> Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 181 +++
> Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c | 1434 ++++++++++++++++++++
> Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.c | 137 ++
> Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLibMem.c | 156 +++
> Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.c | 462 +++++++
> Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 250 ++++
> Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c | 1304 ++++++++++++++++++
> Maintainers.txt | 8 +
> Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl | 209 +++
> Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc | 80 ++
> Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl | 85 ++
> Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl | 15 +
> Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl | 65 +
> Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc | 77 ++
> Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc | 83 ++
> Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc | 89 ++
> Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc | 67 +
> Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc | 65 +
> Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc | 219 +++
> Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc | 73 +
> Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/AArch64/PhytiumPlatformHelper.S | 76 ++
> Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc | 119 ++
> 47 files changed, 8851 insertions(+)
> create mode 100644 Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec
> create mode 100644 Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dsc.inc
> create mode 100644 Platform/Phytium/DurianPkg/DurianPkg.dsc
> create mode 100644 Platform/Phytium/DurianPkg/DurianPkg.fdf
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiTables.inf
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.inf
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.inf
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.inf
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.inf
> create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
> create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.inf
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.h
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.h
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.h
> create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.h
> create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Include/Platform.h
> create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiNorFlashProtocol.h
> create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Include/Protocol/SpiProtocol.h
> create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Include/SystemServiceInterface.h
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiDxe/SpiDxe.c
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/SpiNorFlashDxe/SpiNorFlashDxe.c
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLib.c
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/PlatformLibMem.c
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/RealTimeClockLib/RealTimeClockLib.c
> create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Drivers/AcpiPlatformDxe/AcpiPlatform.c
> create mode 100644 Silicon/Phytium/PhytiumCommonPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/AcpiSsdtRootPci.asl
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dbg2.aslc
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Cpu.asl
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Dsdt.asl
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Dsdt/Uart.asl
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Fadt.aslc
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Gtdt.aslc
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Iort.aslc
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Madt.aslc
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Mcfg.aslc
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Pptt.aslc
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Drivers/AcpiTables/Spcr.aslc
> create mode 100644 Silicon/Phytium/FT2000-4Pkg/Library/PlatformLib/AArch64/PhytiumPlatformHelper.S
> create mode 100644 Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.fdf.inc
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-09-09 10:22 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-09-09 9:47 [PATCH v5 00/10] Added support for FT2000/4 chip Ling Jia
2021-09-09 9:47 ` [PATCH v5 01/10] Silicon/Phytium: Added PlatformLib to FT2000/4 Ling Jia
2021-09-09 9:47 ` [PATCH v5 02/10] Silicon/Phytium: Added Acpi support " Ling Jia
2021-09-09 9:47 ` [PATCH v5 03/10] Silicon/Phytium: Added SMBIOS " Ling Jia
2021-09-09 9:47 ` [PATCH v5 04/10] Silicon/Phytium: Added PciSegmentLib " Ling Jia
2021-09-09 9:47 ` [PATCH v5 05/10] Silicon/Phytium: Added PciHostBridgeLib " Ling Jia
2021-09-09 10:22 ` [PATCH v5 00/10] Added support for FT2000/4 chip Leif Lindholm
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