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[82.11.186.48]) by smtp.gmail.com with ESMTPSA id u25sm3704194wmm.5.2021.09.13.05.42.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Sep 2021 05:42:20 -0700 (PDT) Date: Mon, 13 Sep 2021 13:42:18 +0100 From: "Leif Lindholm" To: Ling Jia Cc: devel@edk2.groups.io Subject: Re: [PATCH v6 04/10] Silicon/Phytium: Added PciSegmentLib to FT2000/4 Message-ID: <20210913124218.symintdoeeyejfzq@leviathan> References: <20210910082058.15194-1-jialing@phytium.com.cn> <20210910082058.15194-5-jialing@phytium.com.cn> MIME-Version: 1.0 In-Reply-To: <20210910082058.15194-5-jialing@phytium.com.cn> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Ling, Having had a look at this version, I propose folding in this change: diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c index 273443fd5d68..124909cc015e 100644 --- a/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c +++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c @@ -1286,9 +1286,8 @@ PciSegmentReadBuffer ( if ((StartAddress & BIT0) != 0) { // // Read a byte if StartAddress is byte aligned, - // Volatile ensure that the latest values are read every time. // - *(UINT8 *)Buffer = PciSegmentRead8 (StartAddress); + MmioWrite8 ((UINTN)Buffer, PciSegmentRead8 (StartAddress)); StartAddress += sizeof (UINT8); Size -= sizeof (UINT8); Buffer = (UINT8 *)Buffer + 1; @@ -1328,7 +1327,7 @@ PciSegmentReadBuffer ( // // Read the last remaining byte if exist // - *(UINT8 *)Buffer = PciSegmentRead8 (StartAddress); + MmioWrite8 ((UINTN)Buffer, PciSegmentRead8 (StartAddress)); } return ReturnValue; If you are OK with that, I feel that patches 1-6 and 9-10 are ready to be merged. I would like to discuss 7/10 to see if we can improve the readability of the code, based on the additional information you provided. (And I think there is no point to include 8/10 without 7/10?) Best Regards, Leif On Fri, Sep 10, 2021 at 16:20:57 +0800, Ling Jia wrote: > The PCI Segment Library for Phytium platform. > with multiple RCs. > > Signed-off-by: Ling Jia > Reviewed-by: Leif Lindholm > --- > Platform/Phytium/DurianPkg/DurianPkg.dsc | 9 +- > Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf | 28 + > Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c | 1434 ++++++++++++++++++++ > 3 files changed, 1464 insertions(+), 7 deletions(-) > > diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/DurianPkg/DurianPkg.dsc > index 28e52e15e3..093b2cd9db 100644 > --- a/Platform/Phytium/DurianPkg/DurianPkg.dsc > +++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc > @@ -35,7 +35,8 @@ > PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf > > [LibraryClasses.common.DXE_DRIVER] > - > + # Pci dependencies > + PciSegmentLib|Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf > > ################################################################################ > # > @@ -262,12 +263,6 @@ > MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf > MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf > > - # > - # PCI Support > - # > - ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf > - MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf > - > # > # The following 2 module perform the same work except one operate variable. > # Only one of both should be put into fdf. > diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf > new file mode 100644 > index 0000000000..67360016ef > --- /dev/null > +++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf > @@ -0,0 +1,28 @@ > +#/** @file > +# PCI Segment Library for Phytium platform with multiple RCs. > +# > +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +#**/ > + > +[Defines] > + INF_VERSION = 0x0001001b > + BASE_NAME = PciSegmentLib > + FILE_GUID = fa5173d2-40fe-11eb-9b2f-cb20dc669fd3 > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = PciSegmentLib > + > +[Sources] > + PciSegmentLib.c > + > +[Packages] > + MdePkg/MdePkg.dec > + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec > + > +[LibraryClasses] > + BaseLib > + DebugLib > + IoLib > diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c > new file mode 100644 > index 0000000000..273443fd5d > --- /dev/null > +++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.c > @@ -0,0 +1,1434 @@ > +/** @file > + PCI Segment Library for SoC with multiple RCs. > + > + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > + > +#define PCI_SEG_CONFIG_BASE 0x40000000 > +#define PCIE_BIF_MODE 0x29100800 > + > +typedef enum { > + PciCfgWidthUint8 = 0, > + PciCfgWidthUint16, > + PciCfgWidthUint32, > + PciCfgWidthMax > +} PCI_CFG_WIDTH; > + > +/** > + Assert the validity of a PCI Segment address. > + A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63 > + > + @param[in] A The address to validate. > + @param[in] M Additional bits to assert to be zero. > + > +**/ > +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \ > +ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0) > + > + > +#define EXTRACT_PCIE_ADDRESS(Address, Bus, Device, Function) \ > +{ \ > + (Bus) = (((Address) >> 20) & 0xff); \ > + (Device) = (((Address) >> 15) & 0x1f); \ > + (Function) = (((Address) >> 12) & 0x07); \ > +} > + > + > +/** > + This function geted the config base of PCI device. > + @param[in] Address The address that encodes the PCI Bus, Device, Function and > + Register. > + > + @return The value of the config base of PCI device. > + > +**/ > +STATIC > +UINT64 > +PciSegmentLibGetConfigBase ( > + IN UINT64 Address > + ) > +{ > + UINT8 Bus; > + UINT8 Device; > + UINT8 Function; > + UINT8 RootPortCount; > + UINT8 Peu0RootPortCount; > + UINT8 Peu1RootPortCount; > + UINT32 BifMode; > + UINT32 Peu0BifMode; > + UINT32 Peu1BifMode; > + > + EXTRACT_PCIE_ADDRESS (Address, Bus, Device, Function); > + BifMode = MmioRead32 (PCIE_BIF_MODE); > + Peu0BifMode = BifMode & 0x3; > + Peu1BifMode = (BifMode >> 2) & 0x3; > + > + if ((Peu0BifMode == 1)) { > + Peu0RootPortCount = 3; > + } else { > + Peu0RootPortCount = 2; > + } > + > + if ((Peu1BifMode == 1)) { > + Peu1RootPortCount = 3; > + } else { > + Peu1RootPortCount = 2; > + } > + RootPortCount = Peu0RootPortCount + Peu1RootPortCount; > + //ignore device > 0 or function > 0 on root port > + if (RootPortCount == 4) { > + if ((Bus == 1) || (Bus == 2) || (Bus == 3) || (Bus == 4)) { > + if (Device != 0 || Function != 0) { > + return 0xFFFFFFFF; > + } > + return PCI_SEG_CONFIG_BASE; > + } > + } else if (RootPortCount == 5) { > + if ((Bus == 1) || (Bus == 2) || (Bus == 3) || (Bus == 4) || (Bus == 5)) { > + if (Device != 0 || Function != 0) { > + return 0xFFFFFFFF; > + } > + return PCI_SEG_CONFIG_BASE; > + } > + } else if (RootPortCount == 6) { > + if ((Bus == 1) || (Bus == 2) || (Bus == 3) || (Bus == 4) || (Bus == 5) || (Bus == 6)) { > + if (Device != 0 || Function != 0) { > + return 0xFFFFFFFF; > + } > + return PCI_SEG_CONFIG_BASE; > + } > + } > + > + return PCI_SEG_CONFIG_BASE; > +} > + > +/** > + Internal worker function to read a PCI configuration register. > + > + @param[in] Address The address that encodes the PCI Bus, Device, Function and > + Register. > + @param[in] Width The width of data to read > + > + @return The value read from the PCI configuration register. > + > +**/ > +STATIC > +UINT32 > +PciSegmentLibReadWorker ( > + IN UINT64 Address, > + IN PCI_CFG_WIDTH Width > + ) > +{ > + UINT64 Base; > + > + Base = PciSegmentLibGetConfigBase (Address); > + if (Base == 0xFFFFFFFF) { > + return 0xFFFFFFFF; > + } > + > + switch (Width) { > + case PciCfgWidthUint8: > + return MmioRead8 (Base + (UINT32)Address); > + case PciCfgWidthUint16: > + return MmioRead16 (Base + (UINT32)Address); > + case PciCfgWidthUint32: > + return MmioRead32 (Base + (UINT32)Address); > + default: > + ASSERT (FALSE); > + } > + > + return 0; > +} > + > + > +/** > + Internal worker function to writes a PCI configuration register. > + > + @param[in] Address The address that encodes the PCI Bus, Device, Function and > + Register. > + @param[in] Width The width of data to write > + @param[in] Data The value to write. > + > + @return The value written to the PCI configuration register. > + > +**/ > +STATIC > +UINT32 > +PciSegmentLibWriteWorker ( > + IN UINT64 Address, > + IN PCI_CFG_WIDTH Width, > + IN UINT32 Data > + ) > +{ > + UINT64 Base; > + > + Base = PciSegmentLibGetConfigBase (Address); > + if (Base == 0xFFFFFFFF) { > + return 0xFFFFFFFF; > + } > + > + switch (Width) { > + case PciCfgWidthUint8: > + MmioWrite8 (Base + (UINT32)Address, Data); > + break; > + case PciCfgWidthUint16: > + MmioWrite16 (Base + (UINT32)Address, Data); > + break; > + case PciCfgWidthUint32: > + MmioWrite32 (Base + (UINT32)Address, Data); > + break; > + default: > + ASSERT (FALSE); > + } > + > + return Data; > +} > + > +/** > + Register a PCI device so PCI configuration registers may be accessed after > + SetVirtualAddressMap(). > + > + If any reserved bits in Address are set, then ASSERT(). > + > + @param[in] Address The address that encodes the PCI Bus, Device, Function and > + Register. > + > + @retval RETURN_SUCCESS The PCI device was registered for runtime access. > + @retval RETURN_UNSUPPORTED An attempt was made to call this function > + after ExitBootServices(). > + @retval RETURN_UNSUPPORTED The resources required to access the PCI device > + at runtime could not be mapped. > + @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to > + complete the registration. > + > +**/ > +RETURN_STATUS > +EFIAPI > +PciSegmentRegisterForRuntimeAccess ( > + IN UINTN Address > + ) > +{ > + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); > + > + return RETURN_UNSUPPORTED; > +} > + > +/** > + Reads an 8-bit PCI configuration register. > + > + Reads and returns the 8-bit PCI configuration register specified by Address. > + This function must guarantee that all PCI read and write operations are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + > + @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, > + and Register. > + > + @return The 8-bit PCI configuration register specified by Address. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentRead8 ( > + IN UINT64 Address > + ) > +{ > + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); > + > + return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8); > +} > + > +/** > + Writes an 8-bit PCI configuration register. > + > + Writes the 8-bit PCI configuration register specified by Address with the value specified by Value. > + Value is returned. This function must guarantee that all PCI read and write operations are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + > + @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. > + @param[in] Value The value to write. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentWrite8 ( > + IN UINT64 Address, > + IN UINT8 Value > + ) > +{ > + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); > + > + return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value); > +} > + > +/** > + Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value. > + > + Reads the 8-bit PCI configuration register specified by Address, > + performs a bitwise OR between the read result and the value specified by OrData, > + and writes the result to the 8-bit PCI configuration register specified by Address. > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + > + @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. > + @param[in] OrData The value to OR with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentOr8 ( > + IN UINT64 Address, > + IN UINT8 OrData > + ) > +{ > + return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData)); > +} > + > +/** > + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value. > + > + Reads the 8-bit PCI configuration register specified by Address, > + performs a bitwise AND between the read result and the value specified by AndData, > + and writes the result to the 8-bit PCI configuration register specified by Address. > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are serialized. > + If any reserved bits in Address are set, then ASSERT(). > + > + @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. > + @param[in] AndData The value to AND with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentAnd8 ( > + IN UINT64 Address, > + IN UINT8 AndData > + ) > +{ > + return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData)); > +} > + > +/** > + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, > + followed a bitwise OR with another 8-bit value. > + > + Reads the 8-bit PCI configuration register specified by Address, > + performs a bitwise AND between the read result and the value specified by AndData, > + performs a bitwise OR between the result of the AND operation and the value specified by OrData, > + and writes the result to the 8-bit PCI configuration register specified by Address. > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + > + @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. > + @param[in] AndData The value to AND with the PCI configuration register. > + @param[in] OrData The value to OR with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentAndThenOr8 ( > + IN UINT64 Address, > + IN UINT8 AndData, > + IN UINT8 OrData > + ) > +{ > + return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData)); > +} > + > +/** > + Reads a bit field of a PCI configuration register. > + > + Reads the bit field in an 8-bit PCI configuration register. The bit field is > + specified by the StartBit and the EndBit. The value of the bit field is > + returned. > + > + If any reserved bits in Address are set, then ASSERT(). > + If StartBit is greater than 7, then ASSERT(). > + If EndBit is greater than 7, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + > + @param[in] Address The PCI configuration register to read. > + @param[in] StartBit The ordinal of the least significant bit in the bit field. > + Range 0..7. > + @param[in] EndBit The ordinal of the most significant bit in the bit field. > + Range 0..7. > + > + @return The value of the bit field read from the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentBitFieldRead8 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit > + ) > +{ > + return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit); > +} > + > +/** > + Writes a bit field to a PCI configuration register. > + > + Writes Value to the bit field of the PCI configuration register. The bit > + field is specified by the StartBit and the EndBit. All other bits in the > + destination PCI configuration register are preserved. The new value of the > + 8-bit register is returned. > + > + @param[in] Address The PCI configuration register to write. > + @param[in] StartBit The ordinal of the least significant bit in the bit field. > + Range 0..7. > + @param[in] EndBit The ordinal of the most significant bit in the bit field. > + Range 0..7. > + @param[in] Value The new value of the bit field. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentBitFieldWrite8 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT8 Value > + ) > +{ > + return PciSegmentWrite8 ( > + Address, > + BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value) > + ); > +} > + > +/** > + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and > + writes the result back to the bit field in the 8-bit port. > + > + Reads the 8-bit PCI configuration register specified by Address, performs a > + bitwise OR between the read result and the value specified by > + OrData, and writes the result to the 8-bit PCI configuration register > + specified by Address. The value written to the PCI configuration register is > + returned. This function must guarantee that all PCI read and write operations > + are serialized. Extra left bits in OrData are stripped. > + > + If any reserved bits in Address are set, then ASSERT(). > + If StartBit is greater than 7, then ASSERT(). > + If EndBit is greater than 7, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param[in] Address The PCI configuration register to write. > + @param[in] StartBit The ordinal of the least significant bit in the bit field. > + Range 0..7. > + @param[in] EndBit The ordinal of the most significant bit in the bit field. > + Range 0..7. > + @param[in] OrData The value to OR with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentBitFieldOr8 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT8 OrData > + ) > +{ > + return PciSegmentWrite8 ( > + Address, > + BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData) > + ); > +} > + > +/** > + Reads a bit field in an 8-bit PCI configuration register, performs a bitwise > + AND, and writes the result back to the bit field in the 8-bit register. > + > + Reads the 8-bit PCI configuration register specified by Address, performs a > + bitwise AND between the read result and the value specified by AndData, and > + writes the result to the 8-bit PCI configuration register specified by > + Address. The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are > + serialized. Extra left bits in AndData are stripped. > + > + If any reserved bits in Address are set, then ASSERT(). > + If StartBit is greater than 7, then ASSERT(). > + If EndBit is greater than 7, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param[in] Address The PCI configuration register to write. > + @param[in] StartBit The ordinal of the least significant bit in the bit field. > + Range 0..7. > + @param[in] EndBit The ordinal of the most significant bit in the bit field. > + Range 0..7. > + @param[in] AndData The value to AND with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentBitFieldAnd8 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT8 AndData > + ) > +{ > + return PciSegmentWrite8 ( > + Address, > + BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData) > + ); > +} > + > +/** > + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a > + bitwise OR, and writes the result back to the bit field in the > + 8-bit port. > + > + Reads the 8-bit PCI configuration register specified by Address, performs a > + bitwise AND followed by a bitwise OR between the read result and > + the value specified by AndData, and writes the result to the 8-bit PCI > + configuration register specified by Address. The value written to the PCI > + configuration register is returned. This function must guarantee that all PCI > + read and write operations are serialized. Extra left bits in both AndData and > + OrData are stripped. > + > + @param[in] Address The PCI configuration register to write. > + @param[in] StartBit The ordinal of the least significant bit in the bit field. > + Range 0..7. > + @param[in] EndBit The ordinal of the most significant bit in the bit field. > + Range 0..7. > + @param[in] AndData The value to AND with the PCI configuration register. > + @param[in] OrData The value to OR with the result of the AND operation. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT8 > +EFIAPI > +PciSegmentBitFieldAndThenOr8 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT8 AndData, > + IN UINT8 OrData > + ) > +{ > + return PciSegmentWrite8 ( > + Address, > + BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData) > + ); > +} > + > +/** > + Reads a 16-bit PCI configuration register. > + > + Reads and returns the 16-bit PCI configuration register specified by Address. > + This function must guarantee that all PCI read and write operations are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + > + @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. > + > + @return The 16-bit PCI configuration register specified by Address. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentRead16 ( > + IN UINT64 Address > + ) > +{ > + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); > + > + return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16); > +} > + > +/** > + Writes a 16-bit PCI configuration register. > + > + Writes the 16-bit PCI configuration register specified by Address with the value specified by Value. > + Value is returned. This function must guarantee that all PCI read and write operations are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + > + @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. > + @param[in] Value The value to write. > + > + @return The parameter of Value. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentWrite16 ( > + IN UINT64 Address, > + IN UINT16 Value > + ) > +{ > + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); > + > + return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value); > +} > + > +/** > + Performs a bitwise OR of a 16-bit PCI configuration register with > + a 16-bit value. > + > + Reads the 16-bit PCI configuration register specified by Address, performs a > + bitwise OR between the read result and the value specified by > + OrData, and writes the result to the 16-bit PCI configuration register > + specified by Address. The value written to the PCI configuration register is > + returned. This function must guarantee that all PCI read and write operations > + are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + > + @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function and > + Register. > + @param[in] OrData The value to OR with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentOr16 ( > + IN UINT64 Address, > + IN UINT16 OrData > + ) > +{ > + return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData)); > +} > + > +/** > + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value. > + > + Reads the 16-bit PCI configuration register specified by Address, > + performs a bitwise AND between the read result and the value specified by AndData, > + and writes the result to the 16-bit PCI configuration register specified by Address. > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + > + @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. > + @param[in] AndData The value to AND with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentAnd16 ( > + IN UINT64 Address, > + IN UINT16 AndData > + ) > +{ > + return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData)); > +} > + > +/** > + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, > + followed a bitwise OR with another 16-bit value. > + > + Reads the 16-bit PCI configuration register specified by Address, > + performs a bitwise AND between the read result and the value specified by AndData, > + performs a bitwise OR between the result of the AND operation and the value specified by OrData, > + and writes the result to the 16-bit PCI configuration register specified by Address. > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + > + @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. > + @param[in] AndData The value to AND with the PCI configuration register. > + @param[in] OrData The value to OR with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentAndThenOr16 ( > + IN UINT64 Address, > + IN UINT16 AndData, > + IN UINT16 OrData > + ) > +{ > + return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData)); > +} > + > +/** > + Reads a bit field of a PCI configuration register. > + > + Reads the bit field in a 16-bit PCI configuration register. The bit field is > + specified by the StartBit and the EndBit. The value of the bit field is > + returned. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + If StartBit is greater than 15, then ASSERT(). > + If EndBit is greater than 15, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + > + @param[in] Address The PCI configuration register to read. > + @param[in] StartBit The ordinal of the least significant bit in the bit field. > + Range 0..15. > + @param[in] EndBit The ordinal of the most significant bit in the bit field. > + Range 0..15. > + > + @return The value of the bit field read from the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentBitFieldRead16 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit > + ) > +{ > + return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit); > +} > + > +/** > + Writes a bit field to a PCI configuration register. > + > + Writes Value to the bit field of the PCI configuration register. The bit > + field is specified by the StartBit and the EndBit. All other bits in the > + destination PCI configuration register are preserved. The new value of the > + 16-bit register is returned. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + If StartBit is greater than 15, then ASSERT(). > + If EndBit is greater than 15, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param[in] Address The PCI configuration register to write. > + @param[in] StartBit The ordinal of the least significant bit in the bit field. > + Range 0..15. > + @param[in] EndBit The ordinal of the most significant bit in the bit field. > + Range 0..15. > + @param[in] Value The new value of the bit field. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentBitFieldWrite16 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT16 Value > + ) > +{ > + return PciSegmentWrite16 ( > + Address, > + BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value) > + ); > +} > + > +/** > + Reads the 16-bit PCI configuration register specified by Address, > + performs a bitwise OR between the read result and the value specified by OrData, > + and writes the result to the 16-bit PCI configuration register specified by Address. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + If StartBit is greater than 15, then ASSERT(). > + If EndBit is greater than 15, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param[in] Address The PCI configuration register to write. > + @param[in] StartBit The ordinal of the least significant bit in the bit field. > + Range 0..15. > + @param[in] EndBit The ordinal of the most significant bit in the bit field. > + Range 0..15. > + @param[in] OrData The value to OR with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentBitFieldOr16 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT16 OrData > + ) > +{ > + return PciSegmentWrite16 ( > + Address, > + BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData) > + ); > +} > + > +/** > + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, > + and writes the result back to the bit field in the 16-bit port. > + > + Reads the 16-bit PCI configuration register specified by Address, > + performs a bitwise OR between the read result and the value specified by OrData, > + and writes the result to the 16-bit PCI configuration register specified by Address. > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are serialized. > + Extra left bits in OrData are stripped. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 16-bit boundary, then ASSERT(). > + If StartBit is greater than 7, then ASSERT(). > + If EndBit is greater than 7, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. > + @param[in] StartBit The ordinal of the least significant bit in the bit field. > + The ordinal of the least significant bit in a byte is bit 0. > + @param[in] EndBit The ordinal of the most significant bit in the bit field. > + The ordinal of the most significant bit in a byte is bit 7. > + @param[in] AndData The value to AND with the read value from the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentBitFieldAnd16 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT16 AndData > + ) > +{ > + return PciSegmentWrite16 ( > + Address, > + BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData) > + ); > +} > + > +/** > + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a > + bitwise OR, and writes the result back to the bit field in the > + 16-bit port. > + > + Reads the 16-bit PCI configuration register specified by Address, performs a > + bitwise AND followed by a bitwise OR between the read result and > + the value specified by AndData, and writes the result to the 16-bit PCI > + configuration register specified by Address. The value written to the PCI > + configuration register is returned. This function must guarantee that all PCI > + read and write operations are serialized. Extra left bits in both AndData and > + OrData are stripped. > + > + If any reserved bits in Address are set, then ASSERT(). > + If StartBit is greater than 15, then ASSERT(). > + If EndBit is greater than 15, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param[in] Address The PCI configuration register to write. > + @param[in] StartBit The ordinal of the least significant bit in the bit field. > + Range 0..15. > + @param[in] EndBit The ordinal of the most significant bit in the bit field. > + Range 0..15. > + @param[in] AndData The value to AND with the PCI configuration register. > + @param[in] OrData The value to OR with the result of the AND operation. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT16 > +EFIAPI > +PciSegmentBitFieldAndThenOr16 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT16 AndData, > + IN UINT16 OrData > + ) > +{ > + return PciSegmentWrite16 ( > + Address, > + BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData) > + ); > +} > + > +/** > + Reads a 32-bit PCI configuration register. > + > + Reads and returns the 32-bit PCI configuration register specified by Address. > + This function must guarantee that all PCI read and write operations are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + > + @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, > + and Register. > + > + @return The 32-bit PCI configuration register specified by Address. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentRead32 ( > + IN UINT64 Address > + ) > +{ > + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); > + > + return PciSegmentLibReadWorker (Address, PciCfgWidthUint32); > +} > + > +/** > + Writes a 32-bit PCI configuration register. > + > + Writes the 32-bit PCI configuration register specified by Address with the value specified by Value. > + Value is returned. This function must guarantee that all PCI read and write operations are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + > + @param[in] Address The address that encodes the PCI Segment, Bus, Device, > + Function, and Register. > + @param[in] Value The value to write. > + > + @return The parameter of Value. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentWrite32 ( > + IN UINT64 Address, > + IN UINT32 Value > + ) > +{ > + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); > + > + return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value); > +} > + > +/** > + Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value. > + > + Reads the 32-bit PCI configuration register specified by Address, > + performs a bitwise OR between the read result and the value specified by OrData, > + and writes the result to the 32-bit PCI configuration register specified by Address. > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + > + @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. > + @param[in] OrData The value to OR with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentOr32 ( > + IN UINT64 Address, > + IN UINT32 OrData > + ) > +{ > + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData); > +} > + > +/** > + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value. > + > + Reads the 32-bit PCI configuration register specified by Address, > + performs a bitwise AND between the read result and the value specified by AndData, > + and writes the result to the 32-bit PCI configuration register specified by Address. > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + > + @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, > + and Register. > + @param[in] AndData The value to AND with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentAnd32 ( > + IN UINT64 Address, > + IN UINT32 AndData > + ) > +{ > + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData); > +} > + > +/** > + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, > + followed a bitwise OR with another 32-bit value. > + > + Reads the 32-bit PCI configuration register specified by Address, > + performs a bitwise AND between the read result and the value specified by AndData, > + performs a bitwise OR between the result of the AND operation and the value specified by OrData, > + and writes the result to the 32-bit PCI configuration register specified by Address. > + The value written to the PCI configuration register is returned. > + This function must guarantee that all PCI read and write operations are serialized. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + > + @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, > + and Register. > + @param[in] AndData The value to AND with the PCI configuration register. > + @param[in] OrData The value to OR with the PCI configuration register. > + > + @return The value written to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentAndThenOr32 ( > + IN UINT64 Address, > + IN UINT32 AndData, > + IN UINT32 OrData > + ) > +{ > + return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData); > +} > + > +/** > + Reads a bit field of a PCI configuration register. > + > + Reads the bit field in a 32-bit PCI configuration register. The bit field is > + specified by the StartBit and the EndBit. The value of the bit field is returned. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + If StartBit is greater than 31, then ASSERT(). > + If EndBit is greater than 31, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + > + @param[in] Address The PCI configuration register to read. > + @param[in] StartBit The ordinal of the least significant bit in the bit field. > + Range 0..31. > + @param[in] EndBit The ordinal of the most significant bit in the bit field. > + Range 0..31. > + > + @return The value of the bit field read from the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentBitFieldRead32 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit > + ) > +{ > + return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit); > +} > + > +/** > + Writes a bit field to a PCI configuration register. > + > + Writes Value to the bit field of the PCI configuration register. The bit > + field is specified by the StartBit and the EndBit. All other bits in the > + destination PCI configuration register are preserved. The new value of the > + 32-bit register is returned. > + > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + If StartBit is greater than 31, then ASSERT(). > + If EndBit is greater than 31, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param[in] Address The PCI configuration register to write. > + @param[in] StartBit The ordinal of the least significant bit in the bit field. > + Range 0..31. > + @param[in] EndBit The ordinal of the most significant bit in the bit field. > + Range 0..31. > + @param[in] Value The new value of the bit field. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentBitFieldWrite32 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT32 Value > + ) > +{ > + return PciSegmentWrite32 ( > + Address, > + BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value) > + ); > +} > + > +/** > + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and > + writes the result back to the bit field in the 32-bit port. > + > + Reads the 32-bit PCI configuration register specified by Address, performs a > + bitwise OR between the read result and the value specified by > + OrData, and writes the result to the 32-bit PCI configuration register > + specified by Address. The value written to the PCI configuration register is > + returned. This function must guarantee that all PCI read and write operations > + are serialized. Extra left bits in OrData are stripped. > + > + If any reserved bits in Address are set, then ASSERT(). > + If StartBit is greater than 31, then ASSERT(). > + If EndBit is greater than 31, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param[in] Address The PCI configuration register to write. > + @param[in] StartBit The ordinal of the least significant bit in the bit field. > + Range 0..31. > + @param[in] EndBit The ordinal of the most significant bit in the bit field. > + Range 0..31. > + @param[in] OrData The value to OR with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentBitFieldOr32 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT32 OrData > + ) > +{ > + return PciSegmentWrite32 ( > + Address, > + BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData) > + ); > +} > + > +/** > + Reads a bit field in a 32-bit PCI configuration register, performs a bitwise > + AND, and writes the result back to the bit field in the 32-bit register. > + > + > + Reads the 32-bit PCI configuration register specified by Address, performs a bitwise > + AND between the read result and the value specified by AndData, and writes the result > + to the 32-bit PCI configuration register specified by Address. The value written to > + the PCI configuration register is returned. This function must guarantee that all PCI > + read and write operations are serialized. Extra left bits in AndData are stripped. > + If any reserved bits in Address are set, then ASSERT(). > + If Address is not aligned on a 32-bit boundary, then ASSERT(). > + If StartBit is greater than 31, then ASSERT(). > + If EndBit is greater than 31, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param[in] Address The PCI configuration register to write. > + @param[in] StartBit The ordinal of the least significant bit in the bit field. > + Range 0..31. > + @param[in] EndBit The ordinal of the most significant bit in the bit field. > + Range 0..31. > + @param[in] AndData The value to AND with the PCI configuration register. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentBitFieldAnd32 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT32 AndData > + ) > +{ > + return PciSegmentWrite32 ( > + Address, > + BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData) > + ); > +} > + > +/** > + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a > + bitwise OR, and writes the result back to the bit field in the > + 32-bit port. > + > + Reads the 32-bit PCI configuration register specified by Address, performs a > + bitwise AND followed by a bitwise OR between the read result and > + the value specified by AndData, and writes the result to the 32-bit PCI > + configuration register specified by Address. The value written to the PCI > + configuration register is returned. This function must guarantee that all PCI > + read and write operations are serialized. Extra left bits in both AndData and > + OrData are stripped. > + > + If any reserved bits in Address are set, then ASSERT(). > + If StartBit is greater than 31, then ASSERT(). > + If EndBit is greater than 31, then ASSERT(). > + If EndBit is less than StartBit, then ASSERT(). > + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). > + > + @param[in] Address The PCI configuration register to write. > + @param[in] StartBit The ordinal of the least significant bit in the bit field. > + Range 0..31. > + @param[in] EndBit The ordinal of the most significant bit in the bit field. > + Range 0..31. > + @param[in] AndData The value to AND with the PCI configuration register. > + @param[in] OrData The value to OR with the result of the AND operation. > + > + @return The value written back to the PCI configuration register. > + > +**/ > +UINT32 > +EFIAPI > +PciSegmentBitFieldAndThenOr32 ( > + IN UINT64 Address, > + IN UINTN StartBit, > + IN UINTN EndBit, > + IN UINT32 AndData, > + IN UINT32 OrData > + ) > +{ > + return PciSegmentWrite32 ( > + Address, > + BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData) > + ); > +} > + > +/** > + Reads a range of PCI configuration registers into a caller supplied buffer. > + > + Reads the range of PCI configuration registers specified by StartAddress and > + Size into the buffer specified by Buffer. This function only allows the PCI > + configuration registers from a single PCI function to be read. Size is > + returned. When possible 32-bit PCI configuration read cycles are used to read > + from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit > + and 16-bit PCI configuration read cycles may be used at the beginning and the > + end of the range. > + > + If any reserved bits in StartAddress are set, then ASSERT(). > + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). > + If Size > 0 and Buffer is NULL, then ASSERT(). > + > + @param[in] StartAddress The starting address that encodes the PCI Segment, Bus, > + Device, Function and Register. > + @param[in] Size The size in bytes of the transfer. > + @param[in] Buffer The pointer to a buffer receiving the data read. > + > + @return Size > + > +**/ > +UINTN > +EFIAPI > +PciSegmentReadBuffer ( > + IN UINT64 StartAddress, > + IN UINTN Size, > + OUT VOID *Buffer > + ) > +{ > + UINTN ReturnValue; > + > + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); > + ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); > + > + if (Size == 0) { > + return Size; > + } > + > + ASSERT (Buffer != NULL); > + > + // > + // Save Size for return > + // > + ReturnValue = Size; > + > + if ((StartAddress & BIT0) != 0) { > + // > + // Read a byte if StartAddress is byte aligned, > + // Volatile ensure that the latest values are read every time. > + // > + *(UINT8 *)Buffer = PciSegmentRead8 (StartAddress); > + StartAddress += sizeof (UINT8); > + Size -= sizeof (UINT8); > + Buffer = (UINT8 *)Buffer + 1; > + } > + > + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) { > + // > + // Read a word if StartAddress is word aligned > + // > + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); > + StartAddress += sizeof (UINT16); > + Size -= sizeof (UINT16); > + Buffer = (UINT16 *)Buffer + 1; > + } > + > + while (Size >= sizeof (UINT32)) { > + // > + // Read as many double words as possible > + // > + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress)); > + StartAddress += sizeof (UINT32); > + Size -= sizeof (UINT32); > + Buffer = (UINT32 *)Buffer + 1; > + } > + > + if (Size >= sizeof (UINT16)) { > + // > + // Read the last remaining word if exist > + // > + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); > + StartAddress += sizeof (UINT16); > + Size -= sizeof (UINT16); > + Buffer = (UINT16 *)Buffer + 1; > + } > + > + if (Size >= sizeof (UINT8)) { > + // > + // Read the last remaining byte if exist > + // > + *(UINT8 *)Buffer = PciSegmentRead8 (StartAddress); > + } > + > + return ReturnValue; > +} > + > + > +/** > + Copies the data in a caller supplied buffer to a specified range of PCI > + configuration space. > + > + Writes the range of PCI configuration registers specified by StartAddress and > + Size from the buffer specified by Buffer. This function only allows the PCI > + configuration registers from a single PCI function to be written. Size is > + returned. When possible 32-bit PCI configuration write cycles are used to > + write from StartAdress to StartAddress + Size. Due to alignment restrictions, > + 8-bit and 16-bit PCI configuration write cycles may be used at the beginning > + and the end of the range. > + > + If any reserved bits in StartAddress are set, then ASSERT(). > + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). > + If Size > 0 and Buffer is NULL, then ASSERT(). > + > + @param[in] StartAddress The starting address that encodes the PCI Segment, Bus, > + Device, Function and Register. > + @param[in] Size The size in bytes of the transfer. > + @param[in] Buffer The pointer to a buffer containing the data to write. > + > + @return The parameter of Size. > + > +**/ > +UINTN > +EFIAPI > +PciSegmentWriteBuffer ( > + IN UINT64 StartAddress, > + IN UINTN Size, > + IN VOID *Buffer > + ) > +{ > + UINTN ReturnValue; > + > + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); > + ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); > + > + if (Size == 0) { > + return 0; > + } > + > + ASSERT (Buffer != NULL); > + > + // > + // Save Size for return > + // > + ReturnValue = Size; > + > + if ((StartAddress & BIT0) != 0) { > + // > + // Write a byte if StartAddress is byte aligned > + // > + PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer); > + StartAddress += sizeof (UINT8); > + Size -= sizeof (UINT8); > + Buffer = (UINT8 *)Buffer + 1; > + } > + > + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) { > + // > + // Write a word if StartAddress is word aligned > + // > + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); > + StartAddress += sizeof (UINT16); > + Size -= sizeof (UINT16); > + Buffer = (UINT16 *)Buffer + 1; > + } > + > + while (Size >= sizeof (UINT32)) { > + // > + // Write as many double words as possible > + // > + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer)); > + StartAddress += sizeof (UINT32); > + Size -= sizeof (UINT32); > + Buffer = (UINT32 *)Buffer + 1; > + } > + > + if (Size >= sizeof (UINT16)) { > + // > + // Write the last remaining word if exist > + // > + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); > + StartAddress += sizeof (UINT16); > + Size -= sizeof (UINT16); > + Buffer = (UINT16 *)Buffer + 1; > + } > + > + if (Size >= sizeof (UINT8)) { > + // > + // Write the last remaining byte if exist > + // > + PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer); > + } > + > + return ReturnValue; > +} > -- > 2.25.1 >