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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?Fy7OsZR9Drv1w1m0VVteRatIGDvRjfukiuR6EQrSMH4HaisK6tGEh8VfvClM?= =?us-ascii?Q?wmhSNN777W0ZS9tWl99R7F3XU2BDvTSMloufnSfcwIdXcTI0iu6whNkQDIS3?= =?us-ascii?Q?hWvxcaNZ0puA1ThFM6G8I1i2Oez04QSAlVxoIUIUYCWl5cxQe/HMKdyEN6+3?= =?us-ascii?Q?ve3IJF0YYE9UzS9AQA28RDU/B3YnaoR/mDgAPWEzapPvMAhP1Kb2YFJpkvqV?= =?us-ascii?Q?lxLzcmn7UL9c/94kU1HIxsNZxnIKWZ8+HYGfBY2pd6jM7aPV6TQw6a2bHu3o?= =?us-ascii?Q?VS98NFFxaQ9P5eC7ScP3W0imvZWBKIgiOagj0S2LusO6DtY4rujTxbtKjoaA?= =?us-ascii?Q?tKeGgFFARnOWVetyngQ87gVZZiXP3w/s0XiBStDrMyQwL/U0v8cjSjminPPf?= =?us-ascii?Q?G72gFgXC+WZHxhRZQaiyq2qybt5vJ+FSlXyTXZfDv+Mfrl48jUQ3aNYf6pDl?= =?us-ascii?Q?6+xV0upMtFoCZdGm6+AcTbEg+q+ljn+g9dCGiKfCElAuj/VmHzdp+CTCYUVI?= =?us-ascii?Q?/W98WF0OvcADQ72R7/KL5bcl3u839AuKA33r+B/TJaBkhyifpiJRzMawy4dP?= =?us-ascii?Q?hzIunrZqmB3LmiXC2/VEx5bh6ahMCsDin5Aru639Ml52btKOCa9K1Hlxvded?= =?us-ascii?Q?uhsedCQ/E+yEtahGANc99TyLuNMAxFEaJXkR1xvpuSZZ8Xt9gOwPrENP5pLx?= =?us-ascii?Q?VYedQBoz+JOg4P1FCLBxQCwdClW8yzI08NK5qTNwn1gNzEa+ceFpy0bTD2lU?= =?us-ascii?Q?Hv57Xyod6rW4H3jCsNHp0W2tEoeFTzzHMTAdQzwEZJE5e1Qp9SM1ju7Behgn?= =?us-ascii?Q?B5XwIsui4C8IwR5EhfkpilsMV97yuj6S25muIw3WO9PcqUrWTIP4KbWb6JO3?= =?us-ascii?Q?Kozh4z42v5mBrJRnmX7qryoH/YxUK8H9f4vyQGkIHJX46vjDACJmeCO2GFhq?= =?us-ascii?Q?WnZiZkwhMfVbtvd8xGh6qxVqWsk5Vcv1xqnaTqT78FrfnWsFBfO2oHZQWqbd?= =?us-ascii?Q?j+b0jE+ADCqgUNUGV9g/1mkttJz+3K5BkuZtYrgj91dU+XHeUcQUF64JhvBp?= =?us-ascii?Q?uw2f91zLXJ+czYhvnfuzHKvcDcuWy7RuW3KRRgyBkrhxoEA+1RzDfsR6XdO6?= =?us-ascii?Q?bvdjx2U7q78od7kfufrMfuUC3Va0Z3Hb+rBX7zun/li3fh4zR5Y5c0w/AfGn?= =?us-ascii?Q?UfUd5FmxYsYk6FWI8Rgu1E2xnHB1ZCjzXwMtQ+nD/gaANqGXwagCJwcjlV/H?= =?us-ascii?Q?uNvFRv6pxUuI4smgEJH4miiHO2a2eOkbeQYJTQUw2RH7DvB6Vziq8H9mtIsk?= =?us-ascii?Q?gVDVoGF5YoaZkEh89UhaXk4l?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 74fd3f44-c8ef-4ffa-5cfe-08d976e31b4b X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2021 18:20:03.8622 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: oXr1ke03WOVISq08MGUsdMS1+xI/cJi2TL52WxZYnh3IbtI/9v3KolzzqvvgAic2JU4UCfjRA6b7/CNZM9ylMw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR12MB2512 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Michael Roth CPUID instructions are issued during early boot to do things like probe for SEV support. Currently these are handled by a minimal #VC handler that uses the MSR-based GHCB protocol to fetch the CPUID values from the hypervisor. When SEV-SNP is enabled, use the firmware-validated CPUID values from the CPUID page instead [1]. [1]: SEV SNP Firmware ABI Specification, Rev. 0.8, 8.13.2.6 Cc: Michael Roth Cc: James Bottomley Cc: Min Xu Cc: Jiewen Yao Cc: Tom Lendacky Cc: Jordan Justen Cc: Ard Biesheuvel Cc: Erdem Aktas Cc: Gerd Hoffmann Acked-by: Jiewen Yao Signed-off-by: Michael Roth Signed-off-by: Brijesh Singh --- OvmfPkg/ResetVector/Ia32/AmdSev.asm | 80 +++++++++++++++++++++++++++-- 1 file changed, 75 insertions(+), 5 deletions(-) diff --git a/OvmfPkg/ResetVector/Ia32/AmdSev.asm b/OvmfPkg/ResetVector/Ia32= /AmdSev.asm index 48d9178168b0..1f827da3b929 100644 --- a/OvmfPkg/ResetVector/Ia32/AmdSev.asm +++ b/OvmfPkg/ResetVector/Ia32/AmdSev.asm @@ -34,6 +34,18 @@ BITS 32 %define GHCB_CPUID_REGISTER_SHIFT 30 %define CPUID_INSN_LEN 2 =20 +; #VC handler offsets/sizes for accessing SNP CPUID page +; +%define SNP_CPUID_ENTRY_SZ 48 +%define SNP_CPUID_COUNT 0 +%define SNP_CPUID_ENTRY 16 +%define SNP_CPUID_ENTRY_EAX_IN 0 +%define SNP_CPUID_ENTRY_ECX_IN 4 +%define SNP_CPUID_ENTRY_EAX 24 +%define SNP_CPUID_ENTRY_EBX 28 +%define SNP_CPUID_ENTRY_ECX 32 +%define SNP_CPUID_ENTRY_EDX 36 + =20 %define SEV_GHCB_MSR 0xc0010130 %define SEV_STATUS_MSR 0xc0010131 @@ -335,11 +347,61 @@ SevEsIdtNotCpuid: TerminateVmgExit TERM_VC_NOT_CPUID iret =20 - ; - ; Total stack usage for the #VC handler is 44 bytes: - ; - 12 bytes for the exception IRET (after popping error code) - ; - 32 bytes for the local variables. - ; +; Use the SNP CPUID page to handle the cpuid lookup +; +; Modified: EAX, EBX, ECX, EDX +; +; Relies on the stack setup/usage in #VC handler: +; +; On entry, +; [esp + VC_CPUID_FUNCTION] contains EAX input to cpuid instruction +; +; On return, stores corresponding results of CPUID lookup in: +; [esp + VC_CPUID_RESULT_EAX] +; [esp + VC_CPUID_RESULT_EBX] +; [esp + VC_CPUID_RESULT_ECX] +; [esp + VC_CPUID_RESULT_EDX] +; +SnpCpuidLookup: + mov eax, [esp + VC_CPUID_FUNCTION] + mov ebx, [CPUID_BASE + SNP_CPUID_COUNT] + mov ecx, CPUID_BASE + SNP_CPUID_ENTRY + ; Zero these out now so we can simply return if lookup fails + mov dword[esp + VC_CPUID_RESULT_EAX], 0 + mov dword[esp + VC_CPUID_RESULT_EBX], 0 + mov dword[esp + VC_CPUID_RESULT_ECX], 0 + mov dword[esp + VC_CPUID_RESULT_EDX], 0 + +SnpCpuidCheckEntry: + cmp ebx, 0 + je VmmDoneSnpCpuid + cmp dword[ecx + SNP_CPUID_ENTRY_EAX_IN], eax + jne SnpCpuidCheckEntryNext + ; As with SEV-ES handler we assume requested CPUID sub-leaf/index is 0 + cmp dword[ecx + SNP_CPUID_ENTRY_ECX_IN], 0 + je SnpCpuidEntryFound + +SnpCpuidCheckEntryNext: + dec ebx + add ecx, SNP_CPUID_ENTRY_SZ + jmp SnpCpuidCheckEntry + +SnpCpuidEntryFound: + mov eax, [ecx + SNP_CPUID_ENTRY_EAX] + mov [esp + VC_CPUID_RESULT_EAX], eax + mov eax, [ecx + SNP_CPUID_ENTRY_EBX] + mov [esp + VC_CPUID_RESULT_EBX], eax + mov eax, [ecx + SNP_CPUID_ENTRY_EDX] + mov [esp + VC_CPUID_RESULT_ECX], eax + mov eax, [ecx + SNP_CPUID_ENTRY_ECX] + mov [esp + VC_CPUID_RESULT_EDX], eax + jmp VmmDoneSnpCpuid + +; +; Total stack usage for the #VC handler is 44 bytes: +; - 12 bytes for the exception IRET (after popping error code) +; - 32 bytes for the local variables. +; SevEsIdtVmmComm: ; ; If we're here, then we are an SEV-ES guest and this @@ -367,6 +429,13 @@ SevEsIdtVmmComm: ; Save the CPUID function being requested mov [esp + VC_CPUID_FUNCTION], eax =20 + ; If SEV-SNP is enabled, use the CPUID page to handle the CPUID + ; instruction. + mov ecx, SEV_STATUS_MSR + rdmsr + bt eax, 2 + jc SnpCpuidLookup + ; The GHCB CPUID protocol uses the following mapping to request ; a specific register: ; 0 =3D> EAX, 1 =3D> EBX, 2 =3D> ECX, 3 =3D> EDX @@ -424,6 +493,7 @@ VmmDone: mov ecx, SEV_GHCB_MSR wrmsr =20 +VmmDoneSnpCpuid: mov eax, [esp + VC_CPUID_RESULT_EAX] mov ebx, [esp + VC_CPUID_RESULT_EBX] mov ecx, [esp + VC_CPUID_RESULT_ECX] --=20 2.17.1