From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.ispras.ru (mail.ispras.ru [83.149.199.84]) by mx.groups.io with SMTP id smtpd.web08.12253.1632147250866427540 for ; Mon, 20 Sep 2021 07:14:11 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: ispras.ru, ip: 83.149.199.84, mailfrom: cheptsov@ispras.ru) Received: from localhost.localdomain (unknown [77.232.9.83]) by mail.ispras.ru (Postfix) with ESMTPSA id 9934640755D7; Mon, 20 Sep 2021 14:14:06 +0000 (UTC) From: "Vitaly Cheptsov" To: devel@edk2.groups.io Cc: Jiewen Yao , Eric Dong , Michael Kinney , Jian J Wang , Jeff Fan , Mikhail Krichanov , =?UTF-8?q?Marvin=20H=C3=A4user?= Subject: [PATCH] UefiCpuPkg: Fix CPU stack guard support by aligning GDT buffer Date: Mon, 20 Sep 2021 17:13:47 +0300 Message-Id: <20210920141347.25161-1-cheptsov@ispras.ru> X-Mailer: git-send-email 2.30.1 (Apple Git-130) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3639=0D =0D Cc: Jiewen Yao =0D Cc: Eric Dong =0D Cc: Michael Kinney =0D Cc: Jian J Wang =0D Cc: Jeff Fan =0D Cc: Mikhail Krichanov =0D Cc: Marvin H=C3=A4user =0D Signed-off-by: Vitaly Cheptsov =0D ---=0D .../Library/CpuExceptionHandlerLib/DxeException.c | 12 +++++++-----=0D 1 file changed, 7 insertions(+), 5 deletions(-)=0D =0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c b/Uef= iCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c=0D index fd59f09ecd..12874811e1 100644=0D --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c=0D +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c=0D @@ -22,7 +22,7 @@ EXCEPTION_HANDLER_DATA mExceptionHandlerData;=0D =0D UINT8 mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *= =0D CPU_KNOWN_GOOD_STACK_SIZE];=0D -UINT8 mNewGdt[CPU_TSS_GDT_SIZE];=0D +UINT8 mNewGdt[CPU_TSS_GDT_SIZE + IA32_GDT_ALIGNMENT]= ;=0D =0D /**=0D Common exception handler.=0D @@ -238,6 +238,7 @@ InitializeCpuExceptionHandlersEx (=0D CPU_EXCEPTION_INIT_DATA EssData;=0D IA32_DESCRIPTOR Idtr;=0D IA32_DESCRIPTOR Gdtr;=0D + UINT8 *Gdt;=0D =0D //=0D // To avoid repeat initialization of default handlers, the caller should= pass=0D @@ -259,6 +260,7 @@ InitializeCpuExceptionHandlersEx (=0D if (PcdGetBool (PcdCpuStackGuard)) {=0D if (InitData =3D=3D NULL) {=0D SetMem (mNewGdt, sizeof (mNewGdt), 0);=0D + Gdt =3D ALIGN_POINTER (mNewGdt, IA32_GDT_ALIGNMENT);=0D =0D AsmReadIdtr (&Idtr);=0D AsmReadGdtr (&Gdtr);=0D @@ -270,11 +272,11 @@ InitializeCpuExceptionHandlersEx (=0D EssData.X64.StackSwitchExceptionNumber =3D CPU_STACK_SWITCH_EXCEPT= ION_NUMBER;=0D EssData.X64.IdtTable =3D (VOID *)Idtr.Base;=0D EssData.X64.IdtTableSize =3D Idtr.Limit + 1;=0D - EssData.X64.GdtTable =3D mNewGdt;=0D - EssData.X64.GdtTableSize =3D sizeof (mNewGdt);=0D - EssData.X64.ExceptionTssDesc =3D mNewGdt + Gdtr.Limit + 1;=0D + EssData.X64.GdtTable =3D Gdt;=0D + EssData.X64.GdtTableSize =3D CPU_TSS_GDT_SIZE;=0D + EssData.X64.ExceptionTssDesc =3D Gdt + Gdtr.Limit + 1;=0D EssData.X64.ExceptionTssDescSize =3D CPU_TSS_DESC_SIZE;=0D - EssData.X64.ExceptionTss =3D mNewGdt + Gdtr.Limit + 1 + CPU_TSS_DE= SC_SIZE;=0D + EssData.X64.ExceptionTss =3D Gdt + Gdtr.Limit + 1 + CPU_TSS_DESC_S= IZE;=0D EssData.X64.ExceptionTssSize =3D CPU_TSS_SIZE;=0D =0D InitData =3D &EssData;=0D -- =0D 2.30.1 (Apple Git-130)=0D =0D