From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) by mx.groups.io with SMTP id smtpd.web10.5965.1632222136088775351 for ; Tue, 21 Sep 2021 04:02:16 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20210112.gappssmtp.com header.s=20210112 header.b=r/7IjiPG; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.167.41, mailfrom: mw@semihalf.com) Received: by mail-lf1-f41.google.com with SMTP id b20so21135121lfv.3 for ; Tue, 21 Sep 2021 04:02:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+JkPBAB5HHQIkcqDRaryhmNB6JI2s7+uUmIJ1vw9TNw=; b=r/7IjiPGh88HPm0uBDipFay1C9nh7ApO8DpcjSzCmkw9NVtHadSGCk7J0HQT2pPwTy pTwJsuBOW9OulGuX9pXw93iNBiZKpkxdJCOy+0JAUH/qst2/tPRoVltm9rvOrfN3YCRT IsAv3+J3ZYTq7rh8jVYboPvMiseJQ8NRCkDryoGY5onf1Vb4IOt0MVw2S/5kSBV/gK3r j0Cq5JFe0OghlbQiGc4SJTAWBMoc3qmKui2ZtZxklfD9JK3Ie9IlWk6ZvaIkV7KTkgPP zNxs4egKVzcYRonuC0BlsrgpLv1oYX5wTLBaivjG/Bd+PUqONycEhSUHPgMN7eFImqQ2 /1GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+JkPBAB5HHQIkcqDRaryhmNB6JI2s7+uUmIJ1vw9TNw=; b=KdUU67Neh3B3Kw7zy0Suojs9sLWT8Fra4JMIAKKzPPz0pE4nT73p6DGzDKV6KjwGs/ V8QR5FacpTey7tjyfA2D4v8xaZBsO2AVmb2A3axtSexzhDa8rdiAcBaqtp+UzHD2bVN7 xZhRgeNdOQDmU8WqP7uH2khgjSbBZe+j4LP0CzZdwwR3izt5kDwVwTMkHqSymdWf/UdB zSAFWFr4MiPAsibgF23VOHmMXlKnurhHFU3Me7lpOF7QRhpAOimTJucilAkzAaKWBits EZUMKp/JRD/JUm7zqI9A39mnMpn1foEDLeiK5bNpedvNO2OTdOBE9ncVY6AU5qk37bCY EAiQ== X-Gm-Message-State: AOAM533/VIT2/RGsc8f1vfwzzElrv37CORYgJhT3yxbqB10bFSUFFN4N 30d4tZ+bVo3lMj2YOJkcvL/InObH0r5KjQ== X-Google-Smtp-Source: ABdhPJwAQo0tVghMTsrWVbUBXkkFlMIkuZ576qeHI2bVd0tUmuSxCNziL3+rDDvWNW9YvNkyXGDm3A== X-Received: by 2002:a05:6512:2307:: with SMTP id o7mr21942160lfu.183.1632222132647; Tue, 21 Sep 2021 04:02:12 -0700 (PDT) Return-Path: Received: from gilgamesh.lab.semihalf.net ([83.142.187.85]) by smtp.gmail.com with ESMTPSA id 131sm2101246ljj.52.2021.09.21.04.02.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Sep 2021 04:02:12 -0700 (PDT) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ardb+tianocore@kernel.org, jaz@semihalf.com, gjb@semihalf.com, Samer.El-Haj-Mahmoud@arm.com, alon.rotman@solid-run.com, Marcin Wojtas Subject: [edk2-platforms PATCH 1/4] SolidRun/Cn913xCEx7Eval: Add Readme.md Date: Tue, 21 Sep 2021 13:00:53 +0200 Message-Id: <20210921110056.659697-2-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20210921110056.659697-1-mw@semihalf.com> References: <20210921110056.659697-1-mw@semihalf.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Add the complete build instruction for CN913x CEx7 Evaluation Board. Signed-off-by: Marcin Wojtas --- Platform/SolidRun/Cn913xCEx7Eval/Readme.md | 98 ++++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Readme.md diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Readme.md b/Platform/SolidRun= /Cn913xCEx7Eval/Readme.md new file mode 100644 index 0000000000..813e723b65 --- /dev/null +++ b/Platform/SolidRun/Cn913xCEx7Eval/Readme.md @@ -0,0 +1,98 @@ +=EF=BB=BFSolidRun CN913x CEx7 Evaluation Board=0D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0D +=0D +# Summary=0D +=0D +This is a port of 64-bit TianoCore EDK II firmware for the SolidRun CN913x= CEx7 Evaluation Board.=0D +=0D +# Building the firmware=0D +=0D +## Prepare toolchain (for cross-compilation only):=0D +=0D +1. Download the toolchain:=0D +=0D + ```=0D + wget https://releases.linaro.org/components/toolchain/binaries/7.5-2019= .12/aarch64-linux-gnu/gcc-linaro-7.5.0-2019.12-x86_64_aarch64-linux-gnu.tar= .xz=0D + ```=0D +=0D +1. After extracting, setup the path and compiler prefix to GCC5\_AARCH64\_= PREFIX variable:=0D +=0D + ```=0D + export GCC5_AARCH64_PREFIX=3D/gcc-linaro-7.5.0-2019.12-= x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-=0D + ```=0D +=0D +## Prepare prerequisites=0D +=0D +1. Create a new folder (directory) on your local development machine=0D + for use as your workspace. This example uses `/work/git/tianocore`, mod= ify as=0D + appropriate for your needs.=0D +=0D + ```=0D + $ export WORKSPACE=3D/work/git/tianocore=0D + $ mkdir -p $WORKSPACE=0D + $ cd $WORKSPACE=0D + ```=0D +=0D +1. Clone the Trusted Firmware repository:=0D +=0D + ```=0D + $ cd ${WORKSPACE}=0D + $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git= =0D + ```=0D +1. Clone repository for auxiliary firmware on the SoC co-processors and ch= eckout to binaries-marvell-armada-SDK10.0.1.0:=0D +=0D + ```=0D + $ cd ${WORKSPACE}=0D + $ git clone https://github.com/MarvellEmbeddedProcessors/binaries-marve= ll.git=0D + $ cd binaries-marvell/=0D + $ git checkout -b binaries-marvell-armada-SDK10.0.1.0 origin/binaries-m= arvell-armada-SDK10.0.1.0=0D + ```=0D +1. Clone the DDR training code from:=0D +=0D + ```=0D + $ cd ${WORKSPACE}=0D + $ git clone https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell= .git=0D + ```=0D +## Prepare EDKII environment:=0D +=0D +Please follow instructions from "Obtaining source code" and "Manual buildi= ng" from the top level edk2-platforms [Readme.md](https://github.com/tianoc= ore/edk2-platforms#readme).=0D +=0D +## Build EDKII:=0D +=0D +1. Use below build command:=0D +=0D + ```=0D + $ cd ${WORKSPACE}=0D + $ build -a AARCH64 -t GCC5 -b RELEASE -D INCLUDE_TFTP_COMMAND -D CAPSUL= E_ENABLE -D X64EMU_ENABLE -p Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eva= l.dsc=0D + ```=0D +=0D +## Build the final firmware image:=0D +=0D +1. Set BL33 variable to path to EDK II output binary:=0D +=0D + ```=0D + $ export BL33=3D${WORKSPACE}/Build/Cn913xCEx7Eval-AARCH64/RELEASE_GCC5/= FV/ARMADA_EFI.fd=0D + ```=0D +1. Export SCP_BL2 variable:=0D +=0D + ```=0D + $ export SCP_BL2=3D${WORKSKPACE}/binaries-marvell/mrvl_scp_bl2.img=0D + ```=0D +1. Export compiler variables (for cross-compilation only):=0D +=0D + ```=0D + $ export ARCH=3Darm64=0D + $ export CROSS_COMPILE=3D/gcc-linaro-7.5.0-2019.12-x86_= 64_aarch64-linux-gnu/bin/aarch64-linux-gnu-=0D + ```=0D +1. Build the image:=0D +=0D + ```=0D + $ cd ${WORKSPACE}/trusted-firmware-a/=0D + $ make LOG_LEVEL=3D20 MV_DDR_PATH=3D${WORKSPACE}/mv-ddr-marvell CP_NUM= =3D3 PLAT=3Dt9130_cex7_eval all fip mrvl_flash=0D +=0D + ```=0D +The firmware image `flash-image.bin` can be found in `build/t9130_cex7_eva= l/release/` directory.=0D +=0D +# ARM System Ready certification.=0D +=0D +CN913x CEx7 Evaluation Board is [System Ready ES](https://developer.arm.co= m/architectures/system-architectures/arm-systemready/es) certified. Release= binary and the firmware components' baselines list are available in a dedi= cated [wiki page](https://github.com/semihalf/edk2-platforms/wiki).=0D --=20 2.29.0