From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) by mx.groups.io with SMTP id smtpd.web09.7797.1632488349224534394 for ; Fri, 24 Sep 2021 05:59:09 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20210112.gappssmtp.com header.s=20210112 header.b=mAouoCF0; spf=pass (domain: nuviainc.com, ip: 209.85.221.52, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f52.google.com with SMTP id w17so27170211wrv.10 for ; Fri, 24 Sep 2021 05:59:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20210112.gappssmtp.com; s=20210112; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=2adCNOmDtk1n19liZfR/DM1dKTPMEahTotpOnG12swU=; b=mAouoCF0dKy8peumNgAqIVz8RphO5kPO1L92KFWBVmAF87n8S02zhcnRbAcsWrZTd0 eyGqauTyasIvm2D3sggjCXEzVaoCbptJke/GF8ZH7+HCaMxCuMmZpKbPaXO5iE5GmqBD 2b8cY/b81v6Tt5peBZ7T1NGO4GDYwaScipX39ABxT2pJFhmHSS4K7/GfzSZDvkfbPGYW 8C9eO/B6RhRoz9NmbfShIkhyUekGu/oeTr6VoMiH4v3yjwzM9I7088XXobpbl4mQldeS /BHnJH+Rib1Oah1+gmpOoST5oOewezPgHnFHLQOjXzEfFTDCb0MAEXNJbb+yypyBrRyD J7gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=2adCNOmDtk1n19liZfR/DM1dKTPMEahTotpOnG12swU=; b=M0/Eg98asW/fz6Es5DWn777K8q/71FhK6a+fOnddJb64Erw65gglIOjLtiphlsEzkz t4vRxeDpBPdsGA/EEORJihysca8kLLFjFdqD5/hBPbCqUhiLxwDqt3+cnfsLSZbLUDzv ihIIKX6aSsCpVWGKT1WTVkg2T4AoDisoSiCqoynq3OsKxQSpc2Epcpuw2sxu5rdPKmjG HYstbidqyUrH8aaeI16984u5E6ED1PW0tO0YnGjCTD5n4x2DJF5/kobwfIZJNZYYkJ92 pjF2V0KMuL8y/YVyxQh5df9CuW5ltngVS2/38+A8V65gFu9ZoWidI9Zij7hdfkEX1gry gjKg== X-Gm-Message-State: AOAM530/QqJmft/KIuhpWWNWc3fpqQ047yNK1J7UcnktvwLUV5DYlktG azX8jMCChD6JJ47LnoL9Xo+pqQ== X-Google-Smtp-Source: ABdhPJzJAfmzrGRb6OjJQPS0gqpfQozCkEXvMZcMpyCxoZ5pGzb1vcRqd7uVqpgHU1YYc+LNlq0FXg== X-Received: by 2002:adf:f188:: with SMTP id h8mr11055283wro.269.1632488347855; Fri, 24 Sep 2021 05:59:07 -0700 (PDT) Return-Path: Received: from leviathan (cpc92314-cmbg19-2-0-cust559.5-4.cable.virginm.net. [82.11.186.48]) by smtp.gmail.com with ESMTPSA id v8sm8055668wrt.12.2021.09.24.05.59.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Sep 2021 05:59:07 -0700 (PDT) Date: Fri, 24 Sep 2021 13:59:05 +0100 From: "Leif Lindholm" To: Nhi Pham Cc: devel@edk2.groups.io, patches@amperecomputing.com, vunguyen@os.amperecomputing.com, Thang Nguyen , Chuong Tran , Phong Vo , Michael D Kinney , Ard Biesheuvel , Nate DeSimone Subject: Re: [PATCH v3 18/28] Ampere: PCIe: Add PciPlatformDxe driver Message-ID: <20210924125905.avfitdgueqcfg76r@leviathan> References: <20210915155527.8176-1-nhi@os.amperecomputing.com> <20210915155527.8176-19-nhi@os.amperecomputing.com> MIME-Version: 1.0 In-Reply-To: <20210915155527.8176-19-nhi@os.amperecomputing.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Sep 15, 2021 at 22:55:17 +0700, Nhi Pham wrote: > From: Vu Nguyen > > Registers the Platform NotifyPhase() to prevent unexpected issues > caused by the enabled PCIe controllers which have unstable link. > > Cc: Thang Nguyen > Cc: Chuong Tran > Cc: Phong Vo > Cc: Leif Lindholm > Cc: Michael D Kinney > Cc: Ard Biesheuvel > Cc: Nate DeSimone > > Signed-off-by: Vu Nguyen Reviewed-by: Leif Lindholm > --- > Platform/Ampere/JadePkg/Jade.dsc | 5 + > Platform/Ampere/JadePkg/Jade.fdf | 1 + > Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.inf | 37 ++++ > Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.c | 212 ++++++++++++++++++++ > 4 files changed, 255 insertions(+) > > diff --git a/Platform/Ampere/JadePkg/Jade.dsc b/Platform/Ampere/JadePkg/Jade.dsc > index b733f8430806..ce5f2c0dc4e1 100644 > --- a/Platform/Ampere/JadePkg/Jade.dsc > +++ b/Platform/Ampere/JadePkg/Jade.dsc > @@ -148,6 +148,11 @@ [Components.common] > Silicon/Ampere/AmpereAltraPkg/AcpiCommonTables/AcpiCommonTables.inf > Platform/Ampere/JadePkg/AcpiTables/AcpiTables.inf > > + # > + # PCIe > + # > + Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.inf > + > # > # VGA Aspeed > # > diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jade.fdf > index 195da2d63a7a..8ddfabcdd9a8 100644 > --- a/Platform/Ampere/JadePkg/Jade.fdf > +++ b/Platform/Ampere/JadePkg/Jade.fdf > @@ -298,6 +298,7 @@ [FV.FvMain] > # > INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf > + INF Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.inf > > # > # VGA Aspeed > diff --git a/Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.inf b/Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.inf > new file mode 100644 > index 000000000000..5f5316055217 > --- /dev/null > +++ b/Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.inf > @@ -0,0 +1,37 @@ > +## @file > +# > +# Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[defines] > + INF_VERSION = 0x0001001B > + BASE_NAME = PciPlatformDxe > + FILE_GUID = 73276F3D-DCBC-49B2-9890-7564F917501D > + MODULE_TYPE = DXE_DRIVER > + VERSION_STRING = 1.0 > + ENTRY_POINT = PciPlatformDriverEntry > + > +[Sources] > + PciPlatformDxe.c > + > +[Packages] > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec > + > +[LibraryClasses] > + Ac01PcieLib > + DebugLib > + UefiBootServicesTableLib > + UefiDriverEntryPoint > + > +[Protocols] > + gEfiDevicePathProtocolGuid > + gEfiPciHostBridgeResourceAllocationProtocolGuid > + gEfiPciPlatformProtocolGuid > + > +[Depex] > + TRUE > diff --git a/Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.c b/Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.c > new file mode 100644 > index 000000000000..196f857175e9 > --- /dev/null > +++ b/Platform/Ampere/JadePkg/Drivers/PciPlatformDxe/PciPlatformDxe.c > @@ -0,0 +1,212 @@ > +/** @file > + > + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#pragma pack(1) > +typedef struct { > + ACPI_HID_DEVICE_PATH AcpiDevicePath; > + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; > +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; > +#pragma pack () > + > +/** > + > + Perform initialization by the phase indicated. > + > + @param This Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance. > + @param HostBridge The associated PCI host bridge handle. > + @param Phase The phase of the PCI controller enumeration. > + @param ChipsetPhase Defines the execution phase of the PCI chipset driver. > + > + @retval EFI_SUCCESS Must return with success. > + > +**/ > +EFI_STATUS > +EFIAPI > +PhaseNotify ( > + IN EFI_PCI_PLATFORM_PROTOCOL *This, > + IN EFI_HANDLE HostBridge, > + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, > + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase > + ) > +{ > + EFI_PCI_ROOT_BRIDGE_DEVICE_PATH *RootBridgeDevPath; > + EFI_HANDLE RootBridgeHandle = NULL; > + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAlloc = NULL; > + EFI_STATUS Status; > + > + if (ChipsetPhase != ChipsetExit) { > + return EFI_SUCCESS; > + } > + > + // > + // Get HostBridgeInstance from HostBridge handle. > + // > + Status = gBS->HandleProtocol ( > + HostBridge, > + &gEfiPciHostBridgeResourceAllocationProtocolGuid, > + (VOID **)&ResAlloc > + ); > + > + while (TRUE) { > + Status = ResAlloc->GetNextRootBridge (ResAlloc, &RootBridgeHandle); > + if (EFI_ERROR (Status)) { > + break; > + } > + > + Status = gBS->HandleProtocol ( > + RootBridgeHandle, > + &gEfiDevicePathProtocolGuid, > + (VOID **)&RootBridgeDevPath > + ); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "%a %d: Failed to locate RootBridge DevicePath\n", __FUNCTION__, __LINE__)); > + break; > + } > + > + Ac01PcieHostBridgeNotifyPhase (RootBridgeDevPath->AcpiDevicePath.UID, 0, Phase); > + } > + > + return EFI_SUCCESS; > +} > + > +/** > + > + The PlatformPrepController() function can be used to notify the platform driver so that > + it can perform platform-specific actions. No specific actions are required. > + Several notification points are defined at this time. More synchronization points may be > + added as required in the future. The PCI bus driver calls the platform driver twice for > + every PCI controller-once before the PCI Host Bridge Resource Allocation Protocol driver > + is notified, and once after the PCI Host Bridge Resource Allocation Protocol driver has > + been notified. > + This member function may not perform any error checking on the input parameters. It also > + does not return any error codes. If this member function detects any error condition, it > + needs to handle those errors on its own because there is no way to surface any errors to > + the caller. > + > + @param This Pointer to the EFI_PCI_PLATFORM_PROTOCOL instance. > + @param HostBridge The associated PCI host bridge handle. > + @param RootBridge The associated PCI root bridge handle. > + @param PciAddress The address of the PCI device on the PCI bus. > + @param Phase The phase of the PCI controller enumeration. > + @param ChipsetPhase Defines the execution phase of the PCI chipset driver. > + > + @retval EFI_SUCCESS The function completed successfully. > + @retval EFI_UNSUPPORTED Not supported. > + > +**/ > +EFI_STATUS > +EFIAPI > +PlatformPrepController ( > + IN EFI_PCI_PLATFORM_PROTOCOL *This, > + IN EFI_HANDLE HostBridge, > + IN EFI_HANDLE RootBridge, > + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, > + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, > + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase > + ) > +{ > + return EFI_UNSUPPORTED; > +} > + > +/** > + Set the PciPolicy as EFI_RESERVE_ISA_IO_NO_ALIAS | EFI_RESERVE_VGA_IO_NO_ALIAS. > + > + @param This The pointer to the Protocol itself. > + @param PciPolicy The returned Policy. > + > + @retval EFI_UNSUPPORTED Function not supported. > + @retval EFI_INVALID_PARAMETER Invalid PciPolicy value. > + > +**/ > +EFI_STATUS > +EFIAPI > +GetPlatformPolicy ( > + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, > + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy > + ) > +{ > + return EFI_UNSUPPORTED; > +} > + > +/** > + > + Return a PCI ROM image for the onboard device represented by PciHandle. > + > + @param This Protocol instance pointer. > + @param PciHandle PCI device to return the ROM image for. > + @param RomImage PCI Rom Image for onboard device. > + @param RomSize Size of RomImage in bytes. > + > + @retval EFI_SUCCESS RomImage is valid. > + @retval EFI_NOT_FOUND No RomImage. > + > +**/ > +EFI_STATUS > +EFIAPI > +GetPciRom ( > + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, > + IN EFI_HANDLE PciHandle, > + OUT VOID **RomImage, > + OUT UINTN *RomSize > + ) > +{ > + return EFI_NOT_FOUND; > +} > + > +// > +// Interface defintion of PCI Platform protocol. > +// > +EFI_PCI_PLATFORM_PROTOCOL mPciPlatformProtocol = { > + .PlatformNotify = PhaseNotify, > + .PlatformPrepController = PlatformPrepController, > + .GetPlatformPolicy = GetPlatformPolicy, > + .GetPciRom = GetPciRom > +}; > + > +/** > + > + The Entry point of the Pci Platform Driver. > + > + @param ImageHandle Handle to the image. > + @param SystemTable Handle to System Table. > + > + @retval EFI_STATUS Status of the function calling. > + > +**/ > +EFI_STATUS > +PciPlatformDriverEntry ( > + IN EFI_HANDLE ImageHandle, > + IN EFI_SYSTEM_TABLE *SystemTable > + ) > +{ > + EFI_STATUS Status; > + EFI_HANDLE PciPlatformHandle; > + > + // > + // Install on a new handle > + // > + PciPlatformHandle = NULL; > + Status = gBS->InstallMultipleProtocolInterfaces ( > + &PciPlatformHandle, > + &gEfiPciPlatformProtocolGuid, > + &mPciPlatformProtocol, > + NULL > + ); > + > + return Status; > +} > -- > 2.17.1 >