From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web09.12625.1632611151977186302 for ; Sat, 25 Sep 2021 16:05:52 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: guo.dong@intel.com) X-IronPort-AV: E=McAfee;i="6200,9189,10118"; a="285311481" X-IronPort-AV: E=Sophos;i="5.85,322,1624345200"; d="scan'208";a="285311481" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Sep 2021 16:05:51 -0700 X-IronPort-AV: E=Sophos;i="5.85,322,1624345200"; d="scan'208";a="586418283" Received: from gdong1-mobl1.amr.corp.intel.com ([10.255.67.241]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Sep 2021 16:05:50 -0700 From: "Guo Dong" To: devel@edk2.groups.io Cc: ray.ni@intel.com, maurice.ma@intel.com, benjamin.you@intel.com, Guo Dong Subject: [`edk2-devel][PATCH 4/8] UefiPayloadPkg: Add SpiFlashLib Date: Sat, 25 Sep 2021 16:05:26 -0700 Message-Id: <20210925230530.861-5-guo.dong@intel.com> X-Mailer: git-send-email 2.32.0.windows.2 In-Reply-To: <20210925230530.861-1-guo.dong@intel.com> References: <20210925230530.861-1-guo.dong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Guo Dong This is a common SPI Flash library used for the Intel platform that supports SPI hardware sequence. This library provides actual SPI flash operation via Intel PCH SPI controller. Signed-off-by: Guo Dong --- .../Include/Guid/SpiFlashInfoGuid.h | 38 + UefiPayloadPkg/Include/Library/SpiFlashLib.h | 215 +++++ UefiPayloadPkg/Library/SpiFlashLib/PchSpi.c | 180 ++++ UefiPayloadPkg/Library/SpiFlashLib/RegsSpi.h | 129 +++ .../Library/SpiFlashLib/SpiCommon.h | 208 +++++ .../Library/SpiFlashLib/SpiFlashLib.c | 857 ++++++++++++++++++ .../Library/SpiFlashLib/SpiFlashLib.inf | 47 + UefiPayloadPkg/UefiPayloadPkg.dec | 1 + 8 files changed, 1675 insertions(+) create mode 100644 UefiPayloadPkg/Include/Guid/SpiFlashInfoGuid.h create mode 100644 UefiPayloadPkg/Include/Library/SpiFlashLib.h create mode 100644 UefiPayloadPkg/Library/SpiFlashLib/PchSpi.c create mode 100644 UefiPayloadPkg/Library/SpiFlashLib/RegsSpi.h create mode 100644 UefiPayloadPkg/Library/SpiFlashLib/SpiCommon.h create mode 100644 UefiPayloadPkg/Library/SpiFlashLib/SpiFlashLib.c create mode 100644 UefiPayloadPkg/Library/SpiFlashLib/SpiFlashLib.inf diff --git a/UefiPayloadPkg/Include/Guid/SpiFlashInfoGuid.h b/UefiPayloadPk= g/Include/Guid/SpiFlashInfoGuid.h new file mode 100644 index 0000000000..d073e8aaa8 --- /dev/null +++ b/UefiPayloadPkg/Include/Guid/SpiFlashInfoGuid.h @@ -0,0 +1,38 @@ +/** @file=0D + This file defines the hob structure for the SPI flash variable info.=0D +=0D + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef __SPI_FLASH_INFO_GUID_H__=0D +#define __SPI_FLASH_INFO_GUID_H__=0D +=0D +#include =0D +//=0D +// SPI Flash infor hob GUID=0D +//=0D +extern EFI_GUID gSpiFlashInfoGuid;=0D +=0D +//=0D +// Set this bit if platform need disable SMM write protection when writing= flash=0D +// in SMM mode using this method: -- AsmWriteMsr32 (0x1FE, MmioRead32 (0x= FED30880) | BIT0);=0D +//=0D +#define FLAGS_SPI_DISABLE_SMM_WRITE_PROTECT BIT0=0D +=0D +//=0D +// Reuse ACPI definition=0D +//=0D +typedef EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE PLD_GENERIC_ADDRESS;=0D +#define SPACE_ID_PCI_CONFIGURATION EFI_ACPI_3_0_PCI_CONFIGURA= TION_SPACE=0D +#define REGISTER_BIT_WIDTH_DWORD EFI_ACPI_3_0_DWORD=0D +=0D +typedef struct {=0D + UINT8 Revision;=0D + UINT8 Reserved;=0D + UINT16 Flags;=0D + PLD_GENERIC_ADDRESS SpiAddress;=0D +} SPI_FLASH_INFO;=0D +=0D +#endif=0D diff --git a/UefiPayloadPkg/Include/Library/SpiFlashLib.h b/UefiPayloadPkg/= Include/Library/SpiFlashLib.h new file mode 100644 index 0000000000..7c334bf4cb --- /dev/null +++ b/UefiPayloadPkg/Include/Library/SpiFlashLib.h @@ -0,0 +1,215 @@ +/** @file=0D + PCH SPI Common Driver implements the SPI Host Controller Compatibility I= nterface.=0D +=0D + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef __SPI_FLASH_LIB_H__=0D +#define __SPI_FLASH_LIB_H__=0D +=0D +/**=0D + Flash Region Type=0D +**/=0D +typedef enum {=0D + FlashRegionDescriptor,=0D + FlashRegionBios,=0D + FlashRegionMe,=0D + FlashRegionGbE,=0D + FlashRegionPlatformData,=0D + FlashRegionDer,=0D + FlashRegionAll,=0D + FlashRegionMax=0D +} FLASH_REGION_TYPE;=0D +=0D +/**=0D + Read SFDP data from the flash part.=0D +=0D + @param[in] ComponentNumber The Component Number for chip select=0D + @param[in] ByteCount Number of bytes in SFDP data portion of = the SPI cycle, the max number is 64=0D + @param[out] SfdpData The Pointer to caller-allocated buffer c= ontaining the SFDP data received=0D + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read.=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiFlashReadSfdp (=0D + IN UINT8 ComponentNumber,=0D + IN UINT32 ByteCount,=0D + OUT UINT8 *SfdpData=0D + );=0D +=0D +/**=0D + Read Jedec Id from the flash part.=0D +=0D + @param[in] ComponentNumber The Component Number for chip select=0D + @param[in] ByteCount Number of bytes in JedecId data portion = of the SPI cycle, the data size is 3 typically=0D + @param[out] JedecId The Pointer to caller-allocated buffer c= ontaining JEDEC ID received=0D + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read.=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiFlashReadJedecId (=0D + IN UINT8 ComponentNumber,=0D + IN UINT32 ByteCount,=0D + OUT UINT8 *JedecId=0D + );=0D +=0D +/**=0D + Write the status register in the flash part.=0D +=0D + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically=0D + @param[in] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register writing=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiFlashWriteStatus (=0D + IN UINT32 ByteCount,=0D + IN UINT8 *StatusValue=0D + );=0D +=0D +/**=0D + Read status register in the flash part.=0D +=0D + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically=0D + @param[out] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register received.=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiFlashReadStatus (=0D + IN UINT32 ByteCount,=0D + OUT UINT8 *StatusValue=0D + );=0D +=0D +/**=0D + Read SC Soft Strap Values=0D +=0D + @param[in] SoftStrapAddr SC Soft Strap address offset from FPSBA.= =0D + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle=0D + @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining SC Soft Strap Value.=0D + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read.=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiReadPchSoftStrap (=0D + IN UINT32 SoftStrapAddr,=0D + IN UINT32 ByteCount,=0D + OUT UINT8 *SoftStrapValue=0D + );=0D +=0D +=0D +/**=0D + Read data from the flash part.=0D +=0D + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor.=0D + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions.=0D + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle.=0D + @param[out] Buffer The Pointer to caller-allocated buffer c= ontaining the dada received.=0D + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read.=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiFlashRead (=0D + IN FLASH_REGION_TYPE FlashRegionType,=0D + IN UINT32 Address,=0D + IN UINT32 ByteCount,=0D + OUT UINT8 *Buffer=0D + );=0D +=0D +/**=0D + Erase some area on the flash part.=0D +=0D + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor.=0D + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions.=0D + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle.=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiFlashErase (=0D + IN FLASH_REGION_TYPE FlashRegionType,=0D + IN UINT32 Address,=0D + IN UINT32 ByteCount=0D + );=0D +=0D +/**=0D + Write data to the flash part.=0D +=0D + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor.=0D + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions.=0D + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle.=0D + @param[in] Buffer Pointer to caller-allocated buffer conta= ining the data sent during the SPI cycle.=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiFlashWrite (=0D + IN FLASH_REGION_TYPE FlashRegionType,=0D + IN UINT32 Address,=0D + IN UINT32 ByteCount,=0D + IN UINT8 *Buffer=0D + );=0D +=0D +/**=0D + Initialize an SPI library.=0D +=0D + @retval EFI_SUCCESS The protocol instance was properly initi= alized=0D + @exception EFI_UNSUPPORTED The SC is not supported by this module=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiConstructor (=0D + VOID=0D + );=0D +=0D +/**=0D + Get the SPI region base and size, based on the enum type=0D +=0D + @param[in] FlashRegionType The Flash Region type for for the base a= ddress which is listed in the Descriptor.=0D + @param[out] BaseAddress The Flash Linear Address for the Region = 'n' Base=0D + @param[out] RegionSize The size for the Region 'n'=0D +=0D + @retval EFI_SUCCESS Read success=0D + @retval EFI_INVALID_PARAMETER Invalid region type given=0D + @retval EFI_DEVICE_ERROR The region is not used=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiGetRegionAddress (=0D + IN FLASH_REGION_TYPE FlashRegionType,=0D + OUT UINT32 *BaseAddress, OPTIONAL=0D + OUT UINT32 *RegionSize OPTIONAL=0D + );=0D +=0D +#endif=0D +=0D diff --git a/UefiPayloadPkg/Library/SpiFlashLib/PchSpi.c b/UefiPayloadPkg/L= ibrary/SpiFlashLib/PchSpi.c new file mode 100644 index 0000000000..58fb0010d6 --- /dev/null +++ b/UefiPayloadPkg/Library/SpiFlashLib/PchSpi.c @@ -0,0 +1,180 @@ +/** @file=0D +=0D + Copyright (c) 2017-2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +#include "SpiCommon.h"=0D +=0D +/**=0D + Acquire SPI MMIO BAR=0D +=0D + @param[in] PchSpiBase PCH SPI PCI Base Address=0D +=0D + @retval Return SPI BAR Address=0D +=0D +**/=0D +UINT32=0D +AcquireSpiBar0 (=0D + IN UINTN PchSpiBase=0D + )=0D +{=0D + return MmioRead32 (PchSpiBase + R_SPI_BASE) & ~(B_SPI_BAR0_MASK);=0D +}=0D +=0D +/**=0D + Release SPI MMIO BAR. Do nothing.=0D +=0D + @param[in] PchSpiBase PCH SPI PCI Base Address=0D +=0D + @retval None=0D +=0D +**/=0D +VOID=0D +ReleaseSpiBar0 (=0D + IN UINTN PchSpiBase=0D + )=0D +{=0D +}=0D +=0D +=0D +=0D +/**=0D + This function is to enable/disable BIOS Write Protect in SMM phase.=0D +=0D + @param[in] EnableSmmSts Flag to Enable/disable Bios write protect= =0D +=0D + @retval None=0D +**/=0D +VOID=0D +CpuSmmDisableBiosWriteProtect (=0D + IN BOOLEAN EnableSmmSts=0D + )=0D +{=0D + UINT32 Data32;=0D +=0D + if(EnableSmmSts){=0D + //=0D + // Disable BIOS Write Protect in SMM phase.=0D + //=0D + Data32 =3D MmioRead32 ((UINTN) (0xFED30880)) | (UINT32) (BIT0);=0D + AsmWriteMsr32 (0x000001FE, Data32);=0D + } else {=0D + //=0D + // Enable BIOS Write Protect in SMM phase=0D + //=0D + Data32 =3D MmioRead32 ((UINTN) (0xFED30880)) & (UINT32) (~BIT0);=0D + AsmWriteMsr32 (0x000001FE, Data32);=0D + }=0D +=0D + //=0D + // Read FED30880h back to ensure the setting went through.=0D + //=0D + Data32 =3D MmioRead32 (0xFED30880);=0D +}=0D +=0D +=0D +/**=0D + This function is a hook for Spi to disable BIOS Write Protect=0D +=0D + @param[in] PchSpiBase PCH SPI PCI Base Address=0D + @param[in] CpuSmmBwp Need to disable CPU SMM Bios write prote= ction or not=0D +=0D + @retval EFI_SUCCESS The protocol instance was properly initi= alized=0D + @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in S= MM phase=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +DisableBiosWriteProtect (=0D + IN UINTN PchSpiBase,=0D + IN UINT8 CpuSmmBwp=0D + )=0D +{=0D +=0D + //=0D + // Write clear BC_SYNC_SS prior to change WPD from 0 to 1.=0D + //=0D + MmioOr8 (PchSpiBase + R_SPI_BCR + 1, (B_SPI_BCR_SYNC_SS >> 8));=0D +=0D + //=0D + // Enable the access to the BIOS space for both read and write cycles=0D + //=0D + MmioOr8 (PchSpiBase + R_SPI_BCR, B_SPI_BCR_BIOSWE);=0D +=0D + if (CpuSmmBwp !=3D 0) {=0D + CpuSmmDisableBiosWriteProtect (TRUE);=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + This function is a hook for Spi to enable BIOS Write Protect=0D +=0D + @param[in] PchSpiBase PCH SPI PCI Base Address=0D + @param[in] CpuSmmBwp Need to disable CPU SMM Bios write prote= ction or not=0D +=0D + @retval None=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +EnableBiosWriteProtect (=0D + IN UINTN PchSpiBase,=0D + IN UINT8 CpuSmmBwp=0D + )=0D +{=0D +=0D + //=0D + // Disable the access to the BIOS space for write cycles=0D + //=0D + MmioAnd8 (PchSpiBase + R_SPI_BCR, (UINT8) (~B_SPI_BCR_BIOSWE));=0D +=0D + if (CpuSmmBwp !=3D 0) {=0D + CpuSmmDisableBiosWriteProtect (FALSE);=0D + }=0D +}=0D +=0D +/**=0D + This function disables SPI Prefetching and caching,=0D + and returns previous BIOS Control Register value before disabling.=0D +=0D + @param[in] PchSpiBase PCH SPI PCI Base Address=0D +=0D + @retval Previous BIOS Control Register value=0D +=0D +**/=0D +UINT8=0D +SaveAndDisableSpiPrefetchCache (=0D + IN UINTN PchSpiBase=0D + )=0D +{=0D + UINT8 BiosCtlSave;=0D +=0D + BiosCtlSave =3D MmioRead8 (PchSpiBase + R_SPI_BCR) & B_SPI_BCR_SRC;=0D +=0D + MmioAndThenOr32 (PchSpiBase + R_SPI_BCR, \=0D + (UINT32) (~B_SPI_BCR_SRC), \=0D + (UINT32) (V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS << B_SPI_BCR_SRC));=0D +=0D + return BiosCtlSave;=0D +}=0D +=0D +/**=0D + This function updates BIOS Control Register with the given value.=0D +=0D + @param[in] PchSpiBase PCH SPI PCI Base Address=0D + @param[in] BiosCtlValue BIOS Control Register Value to be update= d=0D +=0D + @retval None=0D +=0D +**/=0D +VOID=0D +SetSpiBiosControlRegister (=0D + IN UINTN PchSpiBase,=0D + IN UINT8 BiosCtlValue=0D + )=0D +{=0D + MmioAndThenOr8 (PchSpiBase + R_SPI_BCR, (UINT8) ~B_SPI_BCR_SRC, BiosCtlV= alue);=0D +}=0D diff --git a/UefiPayloadPkg/Library/SpiFlashLib/RegsSpi.h b/UefiPayloadPkg/= Library/SpiFlashLib/RegsSpi.h new file mode 100644 index 0000000000..c80c9017e7 --- /dev/null +++ b/UefiPayloadPkg/Library/SpiFlashLib/RegsSpi.h @@ -0,0 +1,129 @@ +/** @file=0D + Register names for SPI device.=0D +=0D + Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef _REGS_SPI_H_=0D +#define _REGS_SPI_H_=0D +=0D +#define R_SPI_BASE 0x10 ///< 32-bit Memory = Base Address Register=0D +#define B_SPI_BAR0_MASK 0x0FFF=0D +#define R_SPI_BCR 0xDC ///< BIOS Control = Register=0D +#define B_SPI_BCR_SRC (BIT3 | BIT2) ///< SPI Read Confi= guration (SRC)=0D +#define V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS 0x04 ///< Prefetch Disab= le, Cache Disable=0D +#define B_SPI_BCR_SYNC_SS BIT8=0D +#define B_SPI_BCR_BIOSWE BIT0 ///< Write Protect = Disable (WPD)=0D +=0D +///=0D +/// SPI Host Interface Registers=0D +#define R_SPI_HSFS 0x04 ///< Hardware Seque= ncing Flash Status and Control Register(32bits)=0D +#define B_SPI_HSFS_FDBC_MASK 0x3F000000 ///< Flash Data Byt= e Count ( <=3D 64), Count =3D (Value in this field) + 1.=0D +#define N_SPI_HSFS_FDBC 24=0D +#define B_SPI_HSFS_CYCLE_MASK 0x001E0000 ///< Flash Cycle.=0D +#define N_SPI_HSFS_CYCLE 17=0D +#define V_SPI_HSFS_CYCLE_READ 0 ///< Flash Cycle Re= ad=0D +#define V_SPI_HSFS_CYCLE_WRITE 2 ///< Flash Cycle Wr= ite=0D +#define V_SPI_HSFS_CYCLE_4K_ERASE 3 ///< Flash Cycle 4K= Block Erase=0D +#define V_SPI_HSFS_CYCLE_64K_ERASE 4 ///< Flash Cycle 64= K Sector Erase=0D +#define V_SPI_HSFS_CYCLE_READ_SFDP 5 ///< Flash Cycle Re= ad SFDP=0D +#define V_SPI_HSFS_CYCLE_READ_JEDEC_ID 6 ///< Flash Cycle Re= ad JEDEC ID=0D +#define V_SPI_HSFS_CYCLE_WRITE_STATUS 7 ///< Flash Cycle Wr= ite Status=0D +#define V_SPI_HSFS_CYCLE_READ_STATUS 8 ///< Flash Cycle Re= ad Status=0D +#define B_SPI_HSFS_CYCLE_FGO BIT16 ///< Flash Cycle Go= .=0D +#define B_SPI_HSFS_FDV BIT14 ///< Flash Descript= or Valid=0D +#define B_SPI_HSFS_SCIP BIT5 ///< SPI Cycle in P= rogress=0D +#define B_SPI_HSFS_FCERR BIT1 ///< Flash Cycle Er= ror=0D +#define B_SPI_HSFS_FDONE BIT0 ///< Flash Cycle Do= ne=0D +=0D +=0D +#define R_SPI_FADDR 0x08 ///< SPI Flash Address=0D +#define B_SPI_FADDR_MASK 0x07FFFFFF ///< SPI Flash Address= Mask (0~26bit)=0D +=0D +=0D +#define R_SPI_FDATA00 0x10 ///< SPI Data 00 (32 bits)= =0D +=0D +#define R_SPI_FRAP 0x50 ///< SPI Flash Regions Acce= ss Permissions Register=0D +#define B_SPI_FRAP_BRWA_PLATFORM BIT12 //< Region write access for= Region4 PlatformData=0D +#define B_SPI_FRAP_BRWA_GBE BIT11 //< Region write access for= Region3 GbE=0D +#define B_SPI_FRAP_BRWA_SEC BIT10 ///< Region Write Access fo= r Region2 SEC=0D +#define B_SPI_FRAP_BRWA_BIOS BIT9 ///< Region Write Access fo= r Region1 BIOS=0D +#define B_SPI_FRAP_BRWA_FLASHD BIT8 ///< Region Write Access fo= r Region0 Flash Descriptor=0D +#define B_SPI_FRAP_BRRA_PLATFORM BIT4 ///< Region read acces= s for Region4 PlatformData=0D +#define B_SPI_FRAP_BRRA_GBE BIT3 ///< Region read acces= s for Region3 GbE=0D +#define B_SPI_FRAP_BRRA_SEC BIT2 ///< Region Read Acces= s for Region2 SEC=0D +#define B_SPI_FRAP_BRRA_BIOS BIT1 ///< Region Read Acces= s for Region1 BIOS=0D +#define B_SPI_FRAP_BRRA_FLASHD BIT0 ///< Region Read Acces= s for Region0 Flash Descriptor=0D +=0D +=0D +#define R_SPI_FREG0_FLASHD 0x54 ///< Flash Region 0 (F= lash Descriptor) (32bits)=0D +#define B_SPI_FREG0_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] her= e represents limit[26:12]=0D +#define N_SPI_FREG0_LIMIT 4 ///< Bit 30:16 identif= ies address bits [26:12]=0D +#define B_SPI_FREG0_BASE_MASK 0x00007FFF ///< Base, [14:0] her= e represents base [26:12]=0D +#define N_SPI_FREG0_BASE 12 ///< Bit 14:0 identifi= es address bits [26:2]=0D +=0D +#define R_SPI_FREG1_BIOS 0x58 ///< Flash Region 1 (B= IOS) (32bits)=0D +#define B_SPI_FREG1_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] her= e represents limit[26:12]=0D +#define N_SPI_FREG1_LIMIT 4 ///< Bit 30:16 identif= ies address bits [26:12]=0D +#define B_SPI_FREG1_BASE_MASK 0x00007FFF ///< Base, [14:0] her= e represents base [26:12]=0D +#define N_SPI_FREG1_BASE 12 ///< Bit 14:0 identifi= es address bits [26:2]=0D +=0D +#define R_SPI_FREG2_SEC 0x5C ///< Flash Region 2 (S= EC) (32bits)=0D +#define B_SPI_FREG2_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] her= e represents limit[26:12]=0D +#define N_SPI_FREG2_LIMIT 4 //< Bit 30:16 identifi= es address bits [26:12]=0D +#define B_SPI_FREG2_BASE_MASK 0x00007FFF ///< Base, [14:0] her= e represents base [26:12]=0D +#define N_SPI_FREG2_BASE 12 //< Bit 14:0 identifie= s address bits [26:2]=0D +=0D +#define R_SPI_FREG3_GBE 0x60 //< Flash Region 3(GbE= )(32bits)=0D +#define B_SPI_FREG3_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] her= e represents limit[26:12]=0D +#define N_SPI_FREG3_LIMIT 4 //< Bit 30:16 identifi= es address bits [26:12]=0D +#define B_SPI_FREG3_BASE_MASK 0x00007FFF ///< Base, [14:0] her= e represents base [26:12]=0D +#define N_SPI_FREG3_BASE 12 //< Bit 14:0 identifie= s address bits [26:2]=0D +=0D +#define R_SPI_FREG4_PLATFORM_DATA 0x64 ///< Flash Region 4 (P= latform Data) (32bits)=0D +#define B_SPI_FREG4_LIMIT_MASK 0x7FFF0000 ///< Size, [30:16] her= e represents limit[26:12]=0D +#define N_SPI_FREG4_LIMIT 4 ///< Bit 30:16 identif= ies address bits [26:12]=0D +#define B_SPI_FREG4_BASE_MASK 0x00007FFF ///< Base, [14:0] her= e represents base [26:12]=0D +#define N_SPI_FREG4_BASE 12 ///< Bit 14:0 identifi= es address bits [26:2]=0D +=0D +=0D +#define S_SPI_FREGX 4 ///< Size of Flash Reg= ion register=0D +#define B_SPI_FREGX_LIMIT_MASK 0x7FFF0000 ///< Flash Region Limi= t [30:16] represents [26:12], [11:0] are assumed to be FFFh=0D +#define N_SPI_FREGX_LIMIT 16 ///< Region limit bit = position=0D +#define N_SPI_FREGX_LIMIT_REPR 12 ///< Region limit bit = represents position=0D +#define B_SPI_FREGX_BASE_MASK 0x00007FFF ///< Flash Region Base= , [14:0] represents [26:12]=0D +=0D +=0D +#define R_SPI_FDOC 0xB4 ///< Flash Descriptor Obser= vability Control Register (32 bits)=0D +#define B_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) ///< Flas= h Descriptor Section Select=0D +#define V_SPI_FDOC_FDSS_FSDM 0x0000 ///< Flash Signature and D= escriptor Map=0D +#define V_SPI_FDOC_FDSS_COMP 0x1000 ///< Component=0D +#define B_SPI_FDOC_FDSI_MASK 0x0FFC ///< Flash Descriptor Sect= ion Index=0D +=0D +#define R_SPI_FDOD 0xB8 ///< Flash Descriptor Obser= vability Data Register (32 bits)=0D +=0D +=0D +#define R_SPI_LVSCC 0xC4 ///=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef _SPI_COMMON_LIB_H_=0D +#define _SPI_COMMON_LIB_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include "RegsSpi.h"=0D +=0D +///=0D +/// Maximum time allowed while waiting the SPI cycle to complete=0D +/// Wait Time =3D 6 seconds =3D 6000000 microseconds=0D +/// Wait Period =3D 10 microseconds=0D +///=0D +#define WAIT_TIME 6000000 ///< Wait Time =3D 6 seconds =3D 6000000 m= icroseconds=0D +#define WAIT_PERIOD 10 ///< Wait Period =3D 10 microseconds=0D +=0D +///=0D +/// Flash cycle Type=0D +///=0D +typedef enum {=0D + FlashCycleRead,=0D + FlashCycleWrite,=0D + FlashCycleErase,=0D + FlashCycleReadSfdp,=0D + FlashCycleReadJedecId,=0D + FlashCycleWriteStatus,=0D + FlashCycleReadStatus,=0D + FlashCycleMax=0D +} FLASH_CYCLE_TYPE;=0D +=0D +///=0D +/// Flash Component Number=0D +///=0D +typedef enum {=0D + FlashComponent0,=0D + FlashComponent1,=0D + FlashComponentMax=0D +} FLASH_COMPONENT_NUM;=0D +=0D +///=0D +/// Private data structure definitions for the driver=0D +///=0D +#define SC_SPI_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('P', 'S', 'P', 'I')=0D +=0D +typedef struct {=0D + UINTN Signature;=0D + EFI_HANDLE Handle;=0D + UINT32 AcpiTmrReg;=0D + UINTN PchSpiBase;=0D + UINT16 RegionPermission;=0D + UINT32 SfdpVscc0Value;=0D + UINT32 SfdpVscc1Value;=0D + UINT32 StrapBaseAddress;=0D + UINT8 NumberOfComponents;=0D + UINT16 Flags;=0D + UINT32 Component1StartAddr;=0D +} SPI_INSTANCE;=0D +=0D +=0D +/**=0D + Acquire SPI MMIO BAR=0D +=0D + @param[in] PchSpiBase PCH SPI PCI Base Address=0D +=0D + @retval Return SPI BAR Address=0D +=0D +**/=0D +UINT32=0D +AcquireSpiBar0 (=0D + IN UINTN PchSpiBase=0D + );=0D +=0D +=0D +/**=0D + Release SPI MMIO BAR. Do nothing.=0D +=0D + @param[in] PchSpiBase PCH SPI PCI Base Address=0D +=0D + @retval None=0D +=0D +**/=0D +VOID=0D +ReleaseSpiBar0 (=0D + IN UINTN PchSpiBase=0D + );=0D +=0D +=0D +/**=0D + This function is a hook for Spi to disable BIOS Write Protect=0D +=0D + @param[in] PchSpiBase PCH SPI PCI Base Address=0D + @param[in] CpuSmmBwp Need to disable CPU SMM Bios write prote= ction or not=0D +=0D + @retval EFI_SUCCESS The protocol instance was properly initi= alized=0D + @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in S= MM phase=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +DisableBiosWriteProtect (=0D + IN UINTN PchSpiBase,=0D + IN UINT8 CpuSmmBwp=0D + );=0D +=0D +/**=0D + This function is a hook for Spi to enable BIOS Write Protect=0D +=0D + @param[in] PchSpiBase PCH SPI PCI Base Address=0D + @param[in] CpuSmmBwp Need to disable CPU SMM Bios write prote= ction or not=0D +=0D + @retval None=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +EnableBiosWriteProtect (=0D + IN UINTN PchSpiBase,=0D + IN UINT8 CpuSmmBwp=0D + );=0D +=0D +=0D +/**=0D + This function disables SPI Prefetching and caching,=0D + and returns previous BIOS Control Register value before disabling.=0D +=0D + @param[in] PchSpiBase PCH SPI PCI Base Address=0D +=0D + @retval Previous BIOS Control Register value=0D +=0D +**/=0D +UINT8=0D +SaveAndDisableSpiPrefetchCache (=0D + IN UINTN PchSpiBase=0D + );=0D +=0D +/**=0D + This function updates BIOS Control Register with the given value.=0D +=0D + @param[in] PchSpiBase PCH SPI PCI Base Address=0D + @param[in] BiosCtlValue BIOS Control Register Value to be update= d=0D +=0D + @retval None=0D +=0D +**/=0D +VOID=0D +SetSpiBiosControlRegister (=0D + IN UINTN PchSpiBase,=0D + IN UINT8 BiosCtlValue=0D + );=0D +=0D +=0D +/**=0D + This function sends the programmed SPI command to the slave device.=0D +=0D + @param[in] SpiRegionType The SPI Region type for flash cycle whic= h is listed in the Descriptor=0D + @param[in] FlashCycleType The Flash SPI cycle type list in HSFC (H= ardware Sequencing Flash Control Register) register=0D + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions.=0D + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle.=0D + @param[in,out] Buffer Pointer to caller-allocated buffer conta= ining the data received or sent during the SPI cycle.=0D +=0D + @retval EFI_SUCCESS SPI command completes successfully.=0D + @retval EFI_DEVICE_ERROR Device error, the command aborts abnorma= lly.=0D + @retval EFI_ACCESS_DENIED Some unrecognized command encountered in= hardware sequencing mode=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D +**/=0D +EFI_STATUS=0D +SendSpiCmd (=0D + IN FLASH_REGION_TYPE FlashRegionType,=0D + IN FLASH_CYCLE_TYPE FlashCycleType,=0D + IN UINT32 Address,=0D + IN UINT32 ByteCount,=0D + IN OUT UINT8 *Buffer=0D + );=0D +=0D +/**=0D + Wait execution cycle to complete on the SPI interface.=0D +=0D + @param[in] PchSpiBar0 Spi MMIO base address=0D + @param[in] ErrorCheck TRUE if the SpiCycle needs to do the err= or check=0D +=0D + @retval TRUE SPI cycle completed on the interface.=0D + @retval FALSE Time out while waiting the SPI cycle to = complete.=0D + It's not safe to program the next comman= d on the SPI interface.=0D +**/=0D +BOOLEAN=0D +WaitForSpiCycleComplete (=0D + IN UINT32 PchSpiBar0,=0D + IN BOOLEAN ErrorCheck=0D + );=0D +=0D +#endif=0D diff --git a/UefiPayloadPkg/Library/SpiFlashLib/SpiFlashLib.c b/UefiPayload= Pkg/Library/SpiFlashLib/SpiFlashLib.c new file mode 100644 index 0000000000..11e4d0ea00 --- /dev/null +++ b/UefiPayloadPkg/Library/SpiFlashLib/SpiFlashLib.c @@ -0,0 +1,857 @@ +/** @file=0D + Generic driver using Hardware Sequencing registers.=0D +=0D + Copyright (c) 2017-2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +#include "SpiCommon.h"=0D +=0D +SPI_INSTANCE *mSpiInstance =3D NULL;=0D +=0D +/**=0D + Get SPI Instance from library global data..=0D +=0D + @retval SpiInstance Return SPI instance=0D +**/=0D +SPI_INSTANCE *=0D +GetSpiInstance (=0D + VOID=0D +)=0D +{=0D + if (mSpiInstance =3D=3D NULL) {=0D + mSpiInstance =3D AllocatePool (sizeof(SPI_INSTANCE));=0D + if (mSpiInstance =3D=3D NULL) {=0D + return NULL;=0D + }=0D + ZeroMem (mSpiInstance, sizeof(SPI_INSTANCE));=0D + }=0D +=0D + return mSpiInstance;=0D +}=0D +=0D +=0D +/**=0D + Initialize an SPI library.=0D +=0D + @retval EFI_SUCCESS The protocol instance was properly initi= alized=0D + @exception EFI_UNSUPPORTED The SC is not supported by this module=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiConstructor (=0D + VOID=0D + )=0D +{=0D + UINT32 ScSpiBar0;=0D + UINT8 Comp0Density;=0D + SPI_INSTANCE *SpiInstance;=0D + EFI_HOB_GUID_TYPE *GuidHob;=0D + SPI_FLASH_INFO *SpiFlashInfo;=0D +=0D + //=0D + // Find SPI flash hob=0D + //=0D + GuidHob =3D GetFirstGuidHob (&gSpiFlashInfoGuid);=0D + if (GuidHob =3D=3D NULL) {=0D + ASSERT (FALSE);=0D + return EFI_NOT_FOUND;=0D + }=0D + SpiFlashInfo =3D (SPI_FLASH_INFO *) GET_GUID_HOB_DATA (GuidHob);=0D +=0D + //=0D + // Initialize the SPI instance=0D + //=0D + SpiInstance =3D GetSpiInstance ();=0D + if (SpiInstance =3D=3D NULL) {=0D + return EFI_NOT_FOUND;=0D + }=0D + DEBUG ((DEBUG_INFO, "SpiInstance =3D %08X\n", SpiInstance));=0D +=0D + SpiInstance->Signature =3D SC_SPI_PRIVATE_DATA_SIGNATURE;=0D + SpiInstance->Handle =3D NULL;=0D +=0D + //=0D + // Check the SPI address=0D + //=0D + if ((SpiFlashInfo->SpiAddress.AddressSpaceId !=3D EFI_ACPI_3_0_PCI_CONF= IGURATION_SPACE) ||=0D + (SpiFlashInfo->SpiAddress.RegisterBitWidth !=3D 32) ||=0D + (SpiFlashInfo->SpiAddress.RegisterBitOffset !=3D 0) ||=0D + (SpiFlashInfo->SpiAddress.AccessSize !=3D EFI_ACPI_3_0_DWORD)){=0D + DEBUG ((DEBUG_ERROR, "SPI FLASH HOB is not expected. need check the ho= b or enhance SPI flash driver.\n"));=0D + }=0D + SpiInstance->PchSpiBase =3D (UINT32)(UINTN)SpiFlashInfo->SpiAddress.Addr= ess;=0D + SpiInstance->Flags =3D SpiFlashInfo->Flags;=0D + DEBUG ((DEBUG_INFO, "PchSpiBase at 0x%x\n", SpiInstance->PchSpiBase));=0D +=0D + ScSpiBar0 =3D AcquireSpiBar0 (SpiInstance->PchSpiBase);=0D + DEBUG ((DEBUG_INFO, "ScSpiBar0 at 0x%08X\n", ScSpiBar0));=0D +=0D + if (ScSpiBar0 =3D=3D 0) {=0D + ASSERT (FALSE);=0D + }=0D +=0D + if ((MmioRead32 (ScSpiBar0 + R_SPI_HSFS) & B_SPI_HSFS_FDV) =3D=3D 0) {=0D + DEBUG ((DEBUG_ERROR, "SPI Flash descriptor invalid, cannot use Hardwar= e Sequencing registers!\n"));=0D + ASSERT (FALSE);=0D + }=0D +=0D + MmioOr32 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_= MEMORY_SPACE);=0D + SpiInstance->RegionPermission =3D MmioRead16 (ScSpiBar0 + R_SPI_FRAP);=0D + SpiInstance->SfdpVscc0Value =3D MmioRead32 (ScSpiBar0 + R_SPI_LVSCC);= =0D + SpiInstance->SfdpVscc1Value =3D MmioRead32 (ScSpiBar0 + R_SPI_UVSCC);= =0D +=0D + //=0D + // Select to Flash Map 0 Register to get the number of flash Component=0D + //=0D + MmioAndThenOr32 (=0D + ScSpiBar0 + R_SPI_FDOC,=0D + (UINT32) (~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)),=0D + (UINT32) (V_SPI_FDOC_FDSS_FSDM | R_SPI_FDBAR_FLASH_MAP0)=0D + );=0D +=0D + //=0D + // Copy Zero based Number Of Components=0D + //=0D + SpiInstance->NumberOfComponents =3D (UINT8) ((MmioRead16 (ScSpiBar0 + R_= SPI_FDOD) & B_SPI_FDBAR_NC) >> N_SPI_FDBAR_NC);=0D +=0D + MmioAndThenOr32 (=0D + ScSpiBar0 + R_SPI_FDOC,=0D + (UINT32) (~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)),=0D + (UINT32) (V_SPI_FDOC_FDSS_COMP | R_SPI_FCBA_FLCOMP)=0D + );=0D +=0D + //=0D + // Copy Component 0 Density=0D + //=0D + Comp0Density =3D (UINT8) MmioRead32 (ScSpiBar0 + R_SPI_FDOD) & B_SPI_FLC= OMP_COMP1_MASK;=0D + SpiInstance->Component1StartAddr =3D (UINT32) (SIZE_512KB << Comp0Densit= y);=0D +=0D + //=0D + // Select FLASH_MAP1 to get Flash SC Strap Base Address=0D + //=0D + MmioAndThenOr32 (=0D + (ScSpiBar0 + R_SPI_FDOC),=0D + (UINT32) (~(B_SPI_FDOC_FDSS_MASK | B_SPI_FDOC_FDSI_MASK)),=0D + (UINT32) (V_SPI_FDOC_FDSS_FSDM | R_SPI_FDBAR_FLASH_MAP1)=0D + );=0D +=0D + SpiInstance->StrapBaseAddress =3D MmioRead32 (ScSpiBar0 + R_SPI_FDOD) & = B_SPI_FDBAR_FPSBA;=0D +=0D + //=0D + // Align FPSBA with address bits for the SC Strap portion of flash descr= iptor=0D + //=0D + SpiInstance->StrapBaseAddress &=3D B_SPI_FDBAR_FPSBA;=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + Read data from the flash part.=0D +=0D + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor.=0D + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions.=0D + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle.=0D + @param[out] Buffer The Pointer to caller-allocated buffer c= ontaining the data received.=0D + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read.=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiFlashRead (=0D + IN FLASH_REGION_TYPE FlashRegionType,=0D + IN UINT32 Address,=0D + IN UINT32 ByteCount,=0D + OUT UINT8 *Buffer=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + Status =3D SendSpiCmd (FlashRegionType, FlashCycleRead, Address, ByteCou= nt, Buffer);=0D + return Status;=0D +}=0D +=0D +/**=0D + Write data to the flash part.=0D +=0D + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor.=0D + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions.=0D + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle.=0D + @param[in] Buffer Pointer to caller-allocated buffer conta= ining the data sent during the SPI cycle.=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiFlashWrite (=0D + IN FLASH_REGION_TYPE FlashRegionType,=0D + IN UINT32 Address,=0D + IN UINT32 ByteCount,=0D + IN UINT8 *Buffer=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + Status =3D SendSpiCmd (FlashRegionType, FlashCycleWrite, Address, ByteCo= unt, Buffer);=0D + return Status;=0D +}=0D +=0D +/**=0D + Erase some area on the flash part.=0D +=0D + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor.=0D + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions.=0D + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle.=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiFlashErase (=0D + IN FLASH_REGION_TYPE FlashRegionType,=0D + IN UINT32 Address,=0D + IN UINT32 ByteCount=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + Status =3D SendSpiCmd (FlashRegionType, FlashCycleErase, Address, ByteCo= unt, NULL);=0D + return Status;=0D +}=0D +=0D +/**=0D + Read SFDP data from the flash part.=0D +=0D + @param[in] ComponentNumber The Component Number for chip select=0D + @param[in] ByteCount Number of bytes in SFDP data portion of = the SPI cycle, the max number is 64=0D + @param[out] SfdpData The Pointer to caller-allocated buffer c= ontaining the SFDP data received=0D + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read.=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiFlashReadSfdp (=0D + IN UINT8 ComponentNumber,=0D + IN UINT32 ByteCount,=0D + OUT UINT8 *SfdpData=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINT32 Address;=0D + SPI_INSTANCE *SpiInstance;=0D +=0D + SpiInstance =3D GetSpiInstance ();=0D + if (SpiInstance =3D=3D NULL) {=0D + return EFI_DEVICE_ERROR;=0D + }=0D +=0D + if ((ByteCount > 64) || (ComponentNumber > SpiInstance->NumberOfComponen= ts)) {=0D + ASSERT (FALSE);=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + Address =3D 0;=0D + if (ComponentNumber =3D=3D FlashComponent1) {=0D + Address =3D SpiInstance->Component1StartAddr;=0D + }=0D +=0D + Status =3D SendSpiCmd (0, FlashCycleReadSfdp, Address, ByteCount, SfdpDa= ta);=0D + return Status;=0D +}=0D +=0D +/**=0D + Read Jedec Id from the flash part.=0D +=0D + @param[in] ComponentNumber The Component Number for chip select=0D + @param[in] ByteCount Number of bytes in JedecId data portion = of the SPI cycle, the data size is 3 typically=0D + @param[out] JedecId The Pointer to caller-allocated buffer c= ontaining JEDEC ID received=0D + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read.=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiFlashReadJedecId (=0D + IN UINT8 ComponentNumber,=0D + IN UINT32 ByteCount,=0D + OUT UINT8 *JedecId=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINT32 Address;=0D + SPI_INSTANCE *SpiInstance;=0D +=0D + SpiInstance =3D GetSpiInstance ();=0D + if (SpiInstance =3D=3D NULL) {=0D + return EFI_DEVICE_ERROR;=0D + }=0D +=0D + if (ComponentNumber > SpiInstance->NumberOfComponents) {=0D + ASSERT (FALSE);=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + Address =3D 0;=0D + if (ComponentNumber =3D=3D FlashComponent1) {=0D + Address =3D SpiInstance->Component1StartAddr;=0D + }=0D +=0D + Status =3D SendSpiCmd (0, FlashCycleReadJedecId, Address, ByteCount, Jed= ecId);=0D + return Status;=0D +}=0D +=0D +/**=0D + Write the status register in the flash part.=0D +=0D + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically=0D + @param[in] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register writing=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiFlashWriteStatus (=0D + IN UINT32 ByteCount,=0D + IN UINT8 *StatusValue=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + Status =3D SendSpiCmd (0, FlashCycleWriteStatus, 0, ByteCount, StatusVal= ue);=0D + return Status;=0D +}=0D +=0D +/**=0D + Read status register in the flash part.=0D +=0D + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically=0D + @param[out] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register received.=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiFlashReadStatus (=0D + IN UINT32 ByteCount,=0D + OUT UINT8 *StatusValue=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + Status =3D SendSpiCmd (0, FlashCycleReadStatus, 0, ByteCount, StatusValu= e);=0D + return Status;=0D +}=0D +=0D +/**=0D + Read SC Soft Strap Values=0D +=0D + @param[in] SoftStrapAddr SC Soft Strap address offset from FPSBA.= =0D + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle=0D + @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining SC Soft Strap Value.=0D + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read.=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiReadPchSoftStrap (=0D + IN UINT32 SoftStrapAddr,=0D + IN UINT32 ByteCount,=0D + OUT UINT8 *SoftStrapValue=0D + )=0D +{=0D + UINT32 StrapFlashAddr;=0D + EFI_STATUS Status;=0D + SPI_INSTANCE *SpiInstance;=0D +=0D + SpiInstance =3D GetSpiInstance ();=0D + if (SpiInstance =3D=3D NULL) {=0D + return EFI_DEVICE_ERROR;=0D + }=0D +=0D + ASSERT (SpiInstance->StrapBaseAddress !=3D 0);=0D + //=0D + // SC Strap Flash Address =3D FPSBA + RamAddr=0D + //=0D + StrapFlashAddr =3D SpiInstance->StrapBaseAddress + SoftStrapAddr;=0D +=0D + Status =3D SendSpiCmd (FlashRegionDescriptor, FlashCycleRead, StrapFlash= Addr, ByteCount, SoftStrapValue);=0D + return Status;=0D +}=0D +=0D +/**=0D + This function sends the programmed SPI command to the slave device.=0D +=0D + @param[in] SpiRegionType The SPI Region type for flash cycle whic= h is listed in the Descriptor=0D + @param[in] FlashCycleType The Flash SPI cycle type list in HSFC (H= ardware Sequencing Flash Control Register) register=0D + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions.=0D + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle.=0D + @param[in,out] Buffer Pointer to caller-allocated buffer conta= ining the data received or sent during the SPI cycle.=0D +=0D + @retval EFI_SUCCESS SPI command completes successfully.=0D + @retval EFI_DEVICE_ERROR Device error, the command aborts abnorma= lly.=0D + @retval EFI_ACCESS_DENIED Some unrecognized command encountered in= hardware sequencing mode=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D +**/=0D +EFI_STATUS=0D +SendSpiCmd (=0D + IN FLASH_REGION_TYPE FlashRegionType,=0D + IN FLASH_CYCLE_TYPE FlashCycleType,=0D + IN UINT32 Address,=0D + IN UINT32 ByteCount,=0D + IN OUT UINT8 *Buffer=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINT32 Index;=0D + UINTN SpiBaseAddress;=0D + UINT32 ScSpiBar0;=0D + UINT32 LimitAddress;=0D + UINT32 HardwareSpiAddr;=0D + UINT16 PermissionBit;=0D + UINT32 SpiDataCount;=0D + UINT32 FlashCycle;=0D + UINT8 BiosCtlSave;=0D + SPI_INSTANCE *SpiInstance;=0D + UINT32 Data32;=0D +=0D + SpiInstance =3D GetSpiInstance ();=0D + if (SpiInstance =3D=3D NULL) {=0D + return EFI_DEVICE_ERROR;=0D + }=0D +=0D + Status =3D EFI_SUCCESS;=0D + SpiBaseAddress =3D SpiInstance->PchSpiBase;=0D + ScSpiBar0 =3D AcquireSpiBar0 (SpiBaseAddress);=0D + BiosCtlSave =3D 0;=0D + SpiInstance->RegionPermission =3D MmioRead16 (ScSpiBar0 + R_SPI_FRAP);=0D +=0D + //=0D + // If it's write cycle, disable Prefetching, Caching and disable BIOS Wr= ite Protect=0D + //=0D + if ((FlashCycleType =3D=3D FlashCycleWrite) || (FlashCycleType =3D=3D Fl= ashCycleErase)) {=0D + Status =3D DisableBiosWriteProtect (SpiBaseAddress, mSpiInstance->Flag= s & FLAGS_SPI_DISABLE_SMM_WRITE_PROTECT);=0D + if (EFI_ERROR (Status)) {=0D + goto SendSpiCmdEnd;=0D + }=0D + BiosCtlSave =3D SaveAndDisableSpiPrefetchCache (SpiBaseAddress);=0D + }=0D +=0D + //=0D + // Make sure it's safe to program the command.=0D + //=0D + if (!WaitForSpiCycleComplete (ScSpiBar0, FALSE)) {=0D + Status =3D EFI_DEVICE_ERROR;=0D + goto SendSpiCmdEnd;=0D + }=0D +=0D + HardwareSpiAddr =3D Address;=0D + if ((FlashCycleType =3D=3D FlashCycleRead) ||=0D + (FlashCycleType =3D=3D FlashCycleWrite) ||=0D + (FlashCycleType =3D=3D FlashCycleErase)) {=0D +=0D + switch (FlashRegionType) {=0D + case FlashRegionDescriptor:=0D + if (FlashCycleType =3D=3D FlashCycleRead) {=0D + PermissionBit =3D B_SPI_FRAP_BRRA_FLASHD;=0D + } else {=0D + PermissionBit =3D B_SPI_FRAP_BRWA_FLASHD;=0D + }=0D + Data32 =3D MmioRead32 (ScSpiBar0 + R_SPI_FREG0_FLASHD);=0D + HardwareSpiAddr +=3D (Data32 & B_SPI_FREG0_BASE_MASK) << N_SPI_FREG0= _BASE;=0D + LimitAddress =3D (Data32 & B_SPI_FREG0_LIMIT_MASK) >> N_SPI_FREG= 0_LIMIT;=0D + break;=0D +=0D + case FlashRegionBios:=0D + if (FlashCycleType =3D=3D FlashCycleRead) {=0D + PermissionBit =3D B_SPI_FRAP_BRRA_BIOS;=0D + } else {=0D + PermissionBit =3D B_SPI_FRAP_BRWA_BIOS;=0D + }=0D + Data32 =3D MmioRead32 (ScSpiBar0 + R_SPI_FREG1_BIOS);=0D + HardwareSpiAddr +=3D (Data32 & B_SPI_FREG1_BASE_MASK) << N_SPI_FREG1= _BASE;=0D + LimitAddress =3D (Data32 & B_SPI_FREG1_LIMIT_MASK) >> N_SPI_FREG= 1_LIMIT;=0D + break;=0D +=0D + case FlashRegionMe:=0D + if (FlashCycleType =3D=3D FlashCycleRead) {=0D + PermissionBit =3D B_SPI_FRAP_BRRA_SEC;=0D + } else {=0D + PermissionBit =3D B_SPI_FRAP_BRWA_SEC;=0D + }=0D + Data32 =3D MmioRead32 (ScSpiBar0 + R_SPI_FREG2_SEC);=0D + HardwareSpiAddr +=3D (Data32 & B_SPI_FREG2_BASE_MASK) << N_SPI_FREG2= _BASE;=0D + LimitAddress =3D (Data32 & B_SPI_FREG2_LIMIT_MASK) >> N_SPI_FREG= 2_LIMIT;=0D + break;=0D +=0D + case FlashRegionGbE:=0D + if (FlashCycleType =3D=3D FlashCycleRead) {=0D + PermissionBit =3D B_SPI_FRAP_BRRA_GBE;=0D + } else {=0D + PermissionBit =3D B_SPI_FRAP_BRWA_GBE;=0D + }=0D + Data32 =3D MmioRead32 (ScSpiBar0 + R_SPI_FREG3_GBE);=0D + HardwareSpiAddr +=3D (Data32 & B_SPI_FREG3_BASE_MASK) << N_SPI_FREG3= _BASE;=0D + LimitAddress =3D (Data32 & B_SPI_FREG3_LIMIT_MASK) >> N_SPI_FREG= 3_LIMIT;=0D + break;=0D +=0D + case FlashRegionPlatformData:=0D + if (FlashCycleType =3D=3D FlashCycleRead) {=0D + PermissionBit =3D B_SPI_FRAP_BRRA_PLATFORM;=0D + } else {=0D + PermissionBit =3D B_SPI_FRAP_BRWA_PLATFORM;=0D + }=0D + Data32 =3D MmioRead32 (ScSpiBar0 + R_SPI_FREG4_PLATFORM_DATA);=0D + HardwareSpiAddr +=3D (Data32 & B_SPI_FREG4_BASE_MASK) << N_SPI_FREG4= _BASE;=0D + LimitAddress =3D (Data32 & B_SPI_FREG4_LIMIT_MASK) >> N_SPI_FREG= 4_LIMIT;=0D + break;=0D +=0D + case FlashRegionAll:=0D + //=0D + // FlashRegionAll indicates address is relative to flash device=0D + // No error checking for this case=0D + //=0D + LimitAddress =3D 0;=0D + PermissionBit =3D 0;=0D + break;=0D +=0D + default:=0D + Status =3D EFI_UNSUPPORTED;=0D + goto SendSpiCmdEnd;=0D + }=0D +=0D + if ((LimitAddress !=3D 0) && (Address > LimitAddress)) {=0D + Status =3D EFI_INVALID_PARAMETER;=0D + goto SendSpiCmdEnd;=0D + }=0D +=0D + //=0D + // If the operation is read, but the region attribute is not read allo= wed, return error.=0D + // If the operation is write, but the region attribute is not write al= lowed, return error.=0D + //=0D + if ((PermissionBit !=3D 0) && ((SpiInstance->RegionPermission & Permis= sionBit) =3D=3D 0)) {=0D + Status =3D EFI_ACCESS_DENIED;=0D + goto SendSpiCmdEnd;=0D + }=0D + }=0D +=0D + //=0D + // Check for SC SPI hardware sequencing required commands=0D + //=0D + FlashCycle =3D 0;=0D + switch (FlashCycleType) {=0D + case FlashCycleRead:=0D + FlashCycle =3D (UINT32) (V_SPI_HSFS_CYCLE_READ << N_SPI_HSFS_CYCLE);=0D + break;=0D +=0D + case FlashCycleWrite:=0D + FlashCycle =3D (UINT32) (V_SPI_HSFS_CYCLE_WRITE << N_SPI_HSFS_CYCLE);= =0D + break;=0D +=0D + case FlashCycleErase:=0D + if (((ByteCount % SIZE_4KB) !=3D 0) || ((HardwareSpiAddr % SIZE_4KB) != =3D 0)) {=0D + DEBUG ((DEBUG_ERROR, "Erase and erase size must be 4KB aligned. \n")= );=0D + ASSERT (FALSE);=0D + Status =3D EFI_INVALID_PARAMETER;=0D + goto SendSpiCmdEnd;=0D + }=0D + break;=0D +=0D + case FlashCycleReadSfdp:=0D + FlashCycle =3D (UINT32) (V_SPI_HSFS_CYCLE_READ_SFDP << N_SPI_HSFS_CYCL= E);=0D + break;=0D +=0D + case FlashCycleReadJedecId:=0D + FlashCycle =3D (UINT32) (V_SPI_HSFS_CYCLE_READ_JEDEC_ID << N_SPI_HSFS_= CYCLE);=0D + break;=0D +=0D + case FlashCycleWriteStatus:=0D + FlashCycle =3D (UINT32) (V_SPI_HSFS_CYCLE_WRITE_STATUS << N_SPI_HSFS_C= YCLE);=0D + break;=0D +=0D + case FlashCycleReadStatus:=0D + FlashCycle =3D (UINT32) (V_SPI_HSFS_CYCLE_READ_STATUS << N_SPI_HSFS_CY= CLE);=0D + break;=0D +=0D + default:=0D + //=0D + // Unrecognized Operation=0D + //=0D + ASSERT (FALSE);=0D + Status =3D EFI_INVALID_PARAMETER;=0D + goto SendSpiCmdEnd;=0D + break;=0D + }=0D +=0D + do {=0D + SpiDataCount =3D ByteCount;=0D + if ((FlashCycleType =3D=3D FlashCycleRead) || (FlashCycleType =3D=3D F= lashCycleWrite)) {=0D + //=0D + // Trim at 256 byte boundary per operation,=0D + // - SC SPI controller requires trimming at 4KB boundary=0D + // - Some SPI chips require trimming at 256 byte boundary for write = operation=0D + // - Trimming has limited performance impact as we can read / write = at most 64 byte=0D + // per operation=0D + //=0D + if (HardwareSpiAddr + ByteCount > ((HardwareSpiAddr + BIT8) &~(BIT8 = - 1))) {=0D + SpiDataCount =3D (((UINT32) (HardwareSpiAddr) + BIT8) &~(BIT8 - 1)= ) - (UINT32) (HardwareSpiAddr);=0D + }=0D + //=0D + // Calculate the number of bytes to shift in/out during the SPI data= cycle.=0D + // Valid settings for the number of bytes during each data portion o= f the=0D + // SC SPI cycles are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32, 40, 48,= 56, 64=0D + //=0D + if (SpiDataCount >=3D 64) {=0D + SpiDataCount =3D 64;=0D + } else if ((SpiDataCount &~0x07) !=3D 0) {=0D + SpiDataCount =3D SpiDataCount &~0x07;=0D + }=0D + }=0D +=0D + if (FlashCycleType =3D=3D FlashCycleErase) {=0D + if (((ByteCount / SIZE_64KB) !=3D 0) &&=0D + ((ByteCount % SIZE_64KB) =3D=3D 0) &&=0D + ((HardwareSpiAddr % SIZE_64KB) =3D=3D 0)) {=0D + if (HardwareSpiAddr < SpiInstance->Component1StartAddr) {=0D + //=0D + // Check whether Component0 support 64k Erase=0D + //=0D + if ((SpiInstance->SfdpVscc0Value & B_SPI_LVSCC_EO_64K) !=3D 0) {= =0D + SpiDataCount =3D SIZE_64KB;=0D + } else {=0D + SpiDataCount =3D SIZE_4KB;=0D + }=0D + } else {=0D + //=0D + // Check whether Component1 support 64k Erase=0D + //=0D + if ((SpiInstance->SfdpVscc1Value & B_SPI_LVSCC_EO_64K) !=3D 0) {= =0D + SpiDataCount =3D SIZE_64KB;=0D + } else {=0D + SpiDataCount =3D SIZE_4KB;=0D + }=0D + }=0D + } else {=0D + SpiDataCount =3D SIZE_4KB;=0D + }=0D + if (SpiDataCount =3D=3D SIZE_4KB) {=0D + FlashCycle =3D (UINT32) (V_SPI_HSFS_CYCLE_4K_ERASE << N_SPI_HSFS_C= YCLE);=0D + } else {=0D + FlashCycle =3D (UINT32) (V_SPI_HSFS_CYCLE_64K_ERASE << N_SPI_HSFS_= CYCLE);=0D + }=0D + }=0D +=0D + //=0D + // If it's write cycle, load data into the SPI data buffer.=0D + //=0D + if ((FlashCycleType =3D=3D FlashCycleWrite) || (FlashCycleType =3D=3D = FlashCycleWriteStatus)) {=0D + if ((SpiDataCount & 0x07) !=3D 0) {=0D + //=0D + // Use Byte write if Data Count is 0, 1, 2, 3, 4, 5, 6, 7=0D + //=0D + for (Index =3D 0; Index < SpiDataCount; Index++) {=0D + MmioWrite8 (ScSpiBar0 + R_SPI_FDATA00 + Index, Buffer[Index]);=0D + }=0D + } else {=0D + //=0D + // Use Dword write if Data Count is 8, 16, 24, 32, 40, 48, 56, 64= =0D + //=0D + for (Index =3D 0; Index < SpiDataCount; Index +=3D sizeof (UINT32)= ) {=0D + MmioWrite32 (ScSpiBar0 + R_SPI_FDATA00 + Index, *(UINT32 *) (Buf= fer + Index));=0D + }=0D + }=0D + }=0D +=0D + //=0D + // Set the Flash Address=0D + //=0D + MmioWrite32 (ScSpiBar0 + R_SPI_FADDR, (UINT32) (HardwareSpiAddr & B_SP= I_FADDR_MASK));=0D +=0D + //=0D + // Set Data count, Flash cycle, and Set Go bit to start a cycle=0D + //=0D + MmioAndThenOr32 (=0D + ScSpiBar0 + R_SPI_HSFS,=0D + (UINT32) (~(B_SPI_HSFS_FDBC_MASK | B_SPI_HSFS_CYCLE_MASK)),=0D + (UINT32) (((SpiDataCount - 1) << N_SPI_HSFS_FDBC) | FlashCycle | B_S= PI_HSFS_CYCLE_FGO)=0D + );=0D +=0D + //=0D + // Wait for command execution complete.=0D + //=0D + if (!WaitForSpiCycleComplete (ScSpiBar0, TRUE)) {=0D + Status =3D EFI_DEVICE_ERROR;=0D + goto SendSpiCmdEnd;=0D + }=0D +=0D + //=0D + // If it's read cycle, load data into the caller's buffer.=0D + //=0D + if ((FlashCycleType =3D=3D FlashCycleRead) ||=0D + (FlashCycleType =3D=3D FlashCycleReadSfdp) ||=0D + (FlashCycleType =3D=3D FlashCycleReadJedecId) ||=0D + (FlashCycleType =3D=3D FlashCycleReadStatus)) {=0D + if ((SpiDataCount & 0x07) !=3D 0) {=0D + //=0D + // Use Byte read if Data Count is 0, 1, 2, 3, 4, 5, 6, 7=0D + //=0D + for (Index =3D 0; Index < SpiDataCount; Index++) {=0D + Buffer[Index] =3D MmioRead8 (ScSpiBar0 + R_SPI_FDATA00 + Index);= =0D + }=0D + } else {=0D + //=0D + // Use Dword read if Data Count is 8, 16, 24, 32, 40, 48, 56, 64=0D + //=0D + for (Index =3D 0; Index < SpiDataCount; Index +=3D sizeof (UINT32)= ) {=0D + *(UINT32 *) (Buffer + Index) =3D MmioRead32 (ScSpiBar0 + R_SPI_F= DATA00 + Index);=0D + }=0D + }=0D + }=0D +=0D + HardwareSpiAddr +=3D SpiDataCount;=0D + Buffer +=3D SpiDataCount;=0D + ByteCount -=3D SpiDataCount;=0D + } while (ByteCount > 0);=0D +=0D +SendSpiCmdEnd:=0D + ///=0D + /// Restore the settings for SPI Prefetching and Caching and enable BIOS= Write Protect=0D + ///=0D + if ((FlashCycleType =3D=3D FlashCycleWrite) || (FlashCycleType =3D=3D Fl= ashCycleErase)) {=0D + EnableBiosWriteProtect (SpiBaseAddress, mSpiInstance->Flags & FLAGS_S= PI_DISABLE_SMM_WRITE_PROTECT);=0D + SetSpiBiosControlRegister (SpiBaseAddress, BiosCtlSave);=0D + }=0D +=0D + ReleaseSpiBar0 (SpiBaseAddress);=0D +=0D + return Status;=0D +}=0D +=0D +/**=0D + Wait execution cycle to complete on the SPI interface.=0D +=0D + @param[in] ScSpiBar0 Spi MMIO base address=0D + @param[in] ErrorCheck TRUE if the SpiCycle needs to do the err= or check=0D +=0D + @retval TRUE SPI cycle completed on the interface.=0D + @retval FALSE Time out while waiting the SPI cycle to = complete.=0D + It's not safe to program the next comman= d on the SPI interface.=0D +**/=0D +BOOLEAN=0D +WaitForSpiCycleComplete (=0D + IN UINT32 ScSpiBar0,=0D + IN BOOLEAN ErrorCheck=0D + )=0D +{=0D + UINT64 WaitTicks;=0D + UINT64 WaitCount;=0D + UINT32 Data32;=0D +=0D + //=0D + // Convert the wait period allowed into to tick count=0D + //=0D + WaitCount =3D WAIT_TIME / WAIT_PERIOD;=0D + //=0D + // Wait for the SPI cycle to complete.=0D + //=0D + for (WaitTicks =3D 0; WaitTicks < WaitCount; WaitTicks++) {=0D + Data32 =3D MmioRead32 (ScSpiBar0 + R_SPI_HSFS);=0D + if ((Data32 & B_SPI_HSFS_SCIP) =3D=3D 0) {=0D + MmioWrite32 (ScSpiBar0 + R_SPI_HSFS, B_SPI_HSFS_FCERR | B_SPI_HSFS_F= DONE);=0D + if (((Data32 & B_SPI_HSFS_FCERR) !=3D 0) && ErrorCheck) {=0D + return FALSE;=0D + } else {=0D + return TRUE;=0D + }=0D + }=0D + MicroSecondDelay ( WAIT_PERIOD);=0D + }=0D + return FALSE;=0D +}=0D +=0D +/**=0D + Get the SPI region base and size, based on the enum type=0D +=0D + @param[in] FlashRegionType The Flash Region type for for the base a= ddress which is listed in the Descriptor.=0D + @param[out] BaseAddress The Flash Linear Address for the Region = 'n' Base=0D + @param[out] RegionSize The size for the Region 'n'=0D +=0D + @retval EFI_SUCCESS Read success=0D + @retval EFI_INVALID_PARAMETER Invalid region type given=0D + @retval EFI_DEVICE_ERROR The region is not used=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiGetRegionAddress (=0D + IN FLASH_REGION_TYPE FlashRegionType,=0D + OUT UINT32 *BaseAddress, OPTIONAL=0D + OUT UINT32 *RegionSize OPTIONAL=0D + )=0D +{=0D + UINT32 ScSpiBar0;=0D + UINT32 ReadValue;=0D + UINT32 Base;=0D + SPI_INSTANCE *SpiInstance;=0D +=0D + if (FlashRegionType >=3D FlashRegionMax) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + SpiInstance =3D GetSpiInstance();=0D + if (SpiInstance =3D=3D NULL) {=0D + return EFI_DEVICE_ERROR;=0D + }=0D +=0D + if (FlashRegionType =3D=3D FlashRegionAll) {=0D + if (BaseAddress !=3D NULL) {=0D + *BaseAddress =3D 0;=0D + }=0D + if (RegionSize !=3D NULL) {=0D + *RegionSize =3D SpiInstance->Component1StartAddr;=0D + }=0D + return EFI_SUCCESS;=0D + }=0D +=0D + ScSpiBar0 =3D AcquireSpiBar0 (SpiInstance->PchSpiBase);=0D + ReadValue =3D MmioRead32 (ScSpiBar0 + R_SPI_FREG0_FLASHD + S_SPI_FREGX *= (UINT32) FlashRegionType);=0D + ReleaseSpiBar0 (SpiInstance->PchSpiBase);=0D +=0D + //=0D + // If the region is not used, the Region Base is 7FFFh and Region Limit = is 0000h=0D + //=0D + if (ReadValue =3D=3D B_SPI_FREGX_BASE_MASK) {=0D + return EFI_DEVICE_ERROR;=0D + }=0D +=0D + Base =3D (ReadValue & B_SPI_FREG1_BASE_MASK) << N_SPI_FREG1_BASE;=0D + if (BaseAddress !=3D NULL) {=0D + *BaseAddress =3D Base;=0D + }=0D +=0D + if (RegionSize !=3D NULL) {=0D + *RegionSize =3D ((((ReadValue & B_SPI_FREGX_LIMIT_MASK) >> N_SPI_FREG= X_LIMIT) + 1) <<=0D + N_SPI_FREGX_LIMIT_REPR) - Base;=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/UefiPayloadPkg/Library/SpiFlashLib/SpiFlashLib.inf b/UefiPaylo= adPkg/Library/SpiFlashLib/SpiFlashLib.inf new file mode 100644 index 0000000000..7e8ecfda41 --- /dev/null +++ b/UefiPayloadPkg/Library/SpiFlashLib/SpiFlashLib.inf @@ -0,0 +1,47 @@ +## @file=0D +#=0D +# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
= =0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D SpiFlashLib=0D + FILE_GUID =3D 6F96AFCB-DE89-4ca1-A63F-8703EE8FDE50= =0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D SpiFlashLib=0D + CONSTRUCTOR =3D SpiConstructor=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64=0D +#=0D +=0D +[Sources]=0D + RegsSpi.h=0D + SpiCommon.h=0D + PchSpi.c=0D + SpiFlashLib.c=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + UefiPayloadPkg/UefiPayloadPkg.dec=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + PcdLib=0D + IoLib=0D + PciLib=0D + HobLib=0D + TimerLib=0D + BaseLib=0D +=0D +[Guids]=0D + gSpiFlashInfoGuid=0D +=0D +[Pcd]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress=0D diff --git a/UefiPayloadPkg/UefiPayloadPkg.dec b/UefiPayloadPkg/UefiPayload= Pkg.dec index 417a70f4e8..2467dc76d6 100644 --- a/UefiPayloadPkg/UefiPayloadPkg.dec +++ b/UefiPayloadPkg/UefiPayloadPkg.dec @@ -37,6 +37,7 @@ gUefiSerialPortInfoGuid =3D { 0x6c6872fe, 0x56a9, 0x4403, { 0xbb, 0x98,= 0x95, 0x8d, 0x62, 0xde, 0x87, 0xf1 } }=0D gLoaderMemoryMapInfoGuid =3D { 0xa1ff7424, 0x7a1a, 0x478e, { 0xa9, 0xe4,= 0x92, 0xf3, 0x57, 0xd1, 0x28, 0x32 } }=0D =0D + gSpiFlashInfoGuid =3D { 0x2d4aac1b, 0x91a5, 0x4cd5, { 0x9b, 0x5c,= 0xb4, 0x0f, 0x5d, 0x28, 0x51, 0xa1 } }=0D gSmmRegisterInfoGuid =3D { 0xaa9bd7a7, 0xcafb, 0x4499, { 0xa4, 0xa9,= 0xb, 0x34, 0x6b, 0x40, 0xa6, 0x22 } }=0D gS3CommunicationGuid =3D { 0x88e31ba1, 0x1856, 0x4b8b, { 0xbb, 0xdf,= 0xf8, 0x16, 0xdd, 0x94, 0xa, 0xef } }=0D =0D --=20 2.32.0.windows.2