* [edk2-platforms][PATCH v2 01/14] U5SeriesPkg: Deduplicate PlatformPei
2021-10-06 11:56 [edk2-platforms][PATCH v2 00/14] Use generic OpenSBI platform Daniel Schaefer
@ 2021-10-06 11:56 ` Daniel Schaefer
2021-10-06 11:56 ` [edk2-platforms][PATCH v2 02/14] RISC-V: Split SMBIOS out of PlatformPei Daniel Schaefer
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Daniel Schaefer @ 2021-10-06 11:56 UTC (permalink / raw)
To: devel; +Cc: Abner Chang, Sunil V L
The current (and future) RISC-V platforms share a lot of PlatformPei
code that does not need to be duplicated. If we see that they need to
have different behavior in the future, we can add platform specific
libraires for that specific code.
The upcoming RiscvVirt is only 1205 lines with this patch.
Still way too much. Hopefully MinPlatform will help.
26 ./RiscvVirt.dec
13 ./RiscvVirt.uni
12 ./RiscvVirtPkgExtra.uni
78 ./VarStore.fdf.inc
66 ./RiscvVirt.fdf.inc
654 ./RiscvVirt.dsc
356 ./RiscvVirt.fdf
1205 total
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
Platform/{SiFive/U5SeriesPkg/FreedomU500VC707Board => RISC-V/PlatformPkg}/Universal/Pei/PlatformPei/Fv.c | 0
Platform/{SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard => RISC-V/PlatformPkg}/Universal/Pei/PlatformPei/MemDetect.c | 11 +-
Platform/{SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard => RISC-V/PlatformPkg}/Universal/Pei/PlatformPei/Platform.c | 6 +-
Platform/{SiFive/U5SeriesPkg/FreedomU500VC707Board => RISC-V/PlatformPkg}/Universal/Pei/PlatformPei/Platform.h | 0
Platform/{SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard => RISC-V/PlatformPkg}/Universal/Pei/PlatformPei/PlatformPei.inf | 4 +-
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc | 2 +-
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf | 2 +-
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/MemDetect.c | 74 -----
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Platform.c | 310 --------------------
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/PlatformPei.inf | 73 -----
Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc | 2 +-
Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf | 2 +-
Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Fv.c | 51 ----
Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.h | 86 ------
14 files changed, 21 insertions(+), 602 deletions(-)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Fv.c b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Fv.c
similarity index 100%
rename from Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Fv.c
rename to Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Fv.c
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/MemDetect.c b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetect.c
similarity index 79%
rename from Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/MemDetect.c
rename to Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetect.c
index 755eae9318..c15d6bb5d4 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/MemDetect.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/MemDetect.c
@@ -1,7 +1,7 @@
/**@file
Memory Detection for Virtual Machines.
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -46,6 +46,10 @@ PublishPeiMemory (
EFI_PHYSICAL_ADDRESS MemoryBase;
UINT64 MemorySize;
+ //
+ // TODO: This value should come from platform
+ // configuration or the memory sizing code.
+ //
MemoryBase = 0x80000000UL + 0x1000000UL;
MemorySize = 0x40000000UL - 0x1000000UL; //1GB - 16MB
@@ -69,6 +73,9 @@ InitializeRamRegions (
VOID
)
{
+ //
+ // TODO: This value should come from platform
+ // configuration or the memory sizing code.
+ //
AddMemoryRangeHob(0x81000000UL, 0x81000000UL + 0x3F000000UL);
-
}
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.c b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
similarity index 93%
rename from Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.c
rename to Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
index 9a2cb9413c..24192c692b 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
@@ -199,11 +199,14 @@ MiscInitialization (
// of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
// S3 resume as well, so we build it unconditionally.)
//
+ // TODO: Determine this dynamically from the platform
+ // setting or the HART configuration.
+ //
BuildCpuHob (48, 32);
}
/**
- Check if system retunrs from S3.
+ Check if system returns from S3.
@return BOOLEAN TRUE, system returned from S3
FALSE, system is not returned from S3
@@ -254,6 +257,7 @@ BuildCoreInformationHob (
EFI_STATUS Status;
RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosHobPtr;
+ // TODO: Create SMBIOS libs for non-U540 platforms
Status = CreateU5MCCoreplexProcessorSpecificDataHob (0);
if (EFI_ERROR (Status)) {
ASSERT(FALSE);
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Platform.h b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.h
similarity index 100%
rename from Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Platform.h
rename to Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.h
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/PlatformPei.inf b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
similarity index 88%
rename from Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/PlatformPei.inf
rename to Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
index 59ada93056..e7f5eef630 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/PlatformPei.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
@@ -3,7 +3,7 @@
#
# This module provides platform specific function to detect boot mode.
#
-# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -62,6 +62,8 @@
gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize
gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdNumberofU5Cores
gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdE5MCSupported
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
index 9f0a25f8a6..fce1c50578 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
@@ -395,7 +395,7 @@
NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
}
- Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/PlatformPei.inf {
+ Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf {
<LibraryClasses>
PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
}
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf
index 5f3ac8e0b7..7db3a02bcb 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf
@@ -99,7 +99,7 @@ INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
# RISC-V Platform PEI Driver
-INF Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/PlatformPei.inf
+INF Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
################################################################################
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/MemDetect.c b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/MemDetect.c
deleted file mode 100644
index 755eae9318..0000000000
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/MemDetect.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/**@file
- Memory Detection for Virtual Machines.
-
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-Module Name:
-
- MemDetect.c
-
-**/
-
-//
-// The package level header files this module uses
-//
-#include <PiPei.h>
-
-//
-// The Library classes this module consumes
-//
-#include <Library/BaseMemoryLib.h>
-#include <Library/DebugLib.h>
-#include <Library/HobLib.h>
-#include <Library/IoLib.h>
-#include <Library/PcdLib.h>
-#include <Library/PeimEntryPoint.h>
-#include <Library/ResourcePublicationLib.h>
-
-#include "Platform.h"
-
-
-/**
- Publish PEI core memory
-
- @return EFI_SUCCESS The PEIM initialized successfully.
-
-**/
-EFI_STATUS
-PublishPeiMemory (
- VOID
- )
-{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS MemoryBase;
- UINT64 MemorySize;
-
- MemoryBase = 0x80000000UL + 0x1000000UL;
- MemorySize = 0x40000000UL - 0x1000000UL; //1GB - 16MB
-
- DEBUG((DEBUG_INFO, "%a: MemoryBase:0x%x MemorySize:%x\n", __FUNCTION__, MemoryBase, MemorySize));
-
- //
- // Publish this memory to the PEI Core
- //
- Status = PublishSystemMemory(MemoryBase, MemorySize);
- ASSERT_EFI_ERROR (Status);
-
- return Status;
-}
-
-/**
- Publish system RAM and reserve memory regions
-
-**/
-VOID
-InitializeRamRegions (
- VOID
- )
-{
- AddMemoryRangeHob(0x81000000UL, 0x81000000UL + 0x3F000000UL);
-
-}
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Platform.c b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Platform.c
deleted file mode 100644
index 6641e10f2e..0000000000
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/Platform.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/**@file
- Platform PEI driver
-
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
- Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-//
-// The package level header files this module uses
-//
-#include <PiPei.h>
-
-//
-// The Library classes this module consumes
-//
-#include <Library/DebugLib.h>
-#include <Library/HobLib.h>
-#include <Library/IoLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/PcdLib.h>
-#include <Library/PciLib.h>
-#include <Library/PeimEntryPoint.h>
-#include <Library/PeiServicesLib.h>
-#include <Library/ResourcePublicationLib.h>
-#include <Guid/MemoryTypeInformation.h>
-#include <Ppi/MasterBootMode.h>
-#include <IndustryStandard/Pci22.h>
-
-#include <SiFiveU5MCCoreplex.h>
-
-#include "Platform.h"
-
-EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
- { EfiACPIMemoryNVS, 0x004 },
- { EfiACPIReclaimMemory, 0x008 },
- { EfiReservedMemoryType, 0x004 },
- { EfiRuntimeServicesData, 0x024 },
- { EfiRuntimeServicesCode, 0x030 },
- { EfiBootServicesCode, 0x180 },
- { EfiBootServicesData, 0xF00 },
- { EfiMaxMemoryType, 0x000 }
-};
-
-
-EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
- &gEfiPeiMasterBootModePpiGuid,
- NULL
- }
-};
-
-STATIC EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
-
-VOID
-AddIoMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
- )
-{
- BuildResourceDescriptorHob (
- EFI_RESOURCE_MEMORY_MAPPED_IO,
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_TESTED,
- MemoryBase,
- MemorySize
- );
-}
-
-VOID
-AddReservedMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
- )
-{
- BuildResourceDescriptorHob (
- EFI_RESOURCE_MEMORY_RESERVED,
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_TESTED,
- MemoryBase,
- MemorySize
- );
-}
-
-VOID
-AddIoMemoryRangeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- EFI_PHYSICAL_ADDRESS MemoryLimit
- )
-{
- AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
-}
-
-
-VOID
-AddMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
- )
-{
- BuildResourceDescriptorHob (
- EFI_RESOURCE_SYSTEM_MEMORY,
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_TESTED,
- MemoryBase,
- MemorySize
- );
-}
-
-
-VOID
-AddMemoryRangeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- EFI_PHYSICAL_ADDRESS MemoryLimit
- )
-{
- AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
-}
-
-
-VOID
-AddUntestedMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
- )
-{
- BuildResourceDescriptorHob (
- EFI_RESOURCE_SYSTEM_MEMORY,
- EFI_RESOURCE_ATTRIBUTE_PRESENT |
- EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
- EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
- EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,
- MemoryBase,
- MemorySize
- );
-}
-
-VOID
-AddUntestedMemoryRangeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- EFI_PHYSICAL_ADDRESS MemoryLimit
- )
-{
- AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
-}
-
-VOID
-AddPciResource (
- VOID
- )
-{
- //
- // Platform-specific
- //
-}
-
-VOID
-MemMapInitialization (
- VOID
- )
-{
- //
- // Create Memory Type Information HOB
- //
- BuildGuidDataHob (
- &gEfiMemoryTypeInformationGuid,
- mDefaultMemoryTypeInformation,
- sizeof(mDefaultMemoryTypeInformation)
- );
-
- //
- // Add PCI IO Port space available for PCI resource allocations.
- //
- AddPciResource ();
-}
-
-VOID
-MiscInitialization (
- VOID
- )
-{
- //
- // Build the CPU HOB with guest RAM size dependent address width and 16-bits
- // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
- // S3 resume as well, so we build it unconditionally.)
- //
- BuildCpuHob (32, 32);
-}
-
-/**
- Check if system retunrs from S3.
-
- @return BOOLEAN TRUE, system returned from S3
- FALSE, system is not returned from S3
-
-**/
-BOOLEAN
-CheckResumeFromS3 (
- VOID
- )
-{
- //
- //Platform implementation-specific
- //
- return FALSE;
-}
-
-
-VOID
-BootModeInitialization (
- VOID
- )
-{
- EFI_STATUS Status;
-
- if (CheckResumeFromS3 () == TRUE) {
- DEBUG ((DEBUG_INFO, "This is wake from S3\n"));
- } else {
- DEBUG ((DEBUG_INFO, "This is normal boot\n"));
- }
- Status = PeiServicesSetBootMode (mBootMode);
- ASSERT_EFI_ERROR (Status);
-
- Status = PeiServicesInstallPpi (mPpiBootMode);
- ASSERT_EFI_ERROR (Status);
-}
-
-/**
- Build processor information for U54 Coreplex processor.
-
- @return EFI_SUCCESS Status.
-
-**/
-EFI_STATUS
-BuildCoreInformationHob (
- VOID
-)
-{
- EFI_STATUS Status;
- RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosHobPtr;
-
- Status = CreateU5MCCoreplexProcessorSpecificDataHob (0);
- if (EFI_ERROR (Status)) {
- ASSERT(FALSE);
- }
- Status = CreateU5MCProcessorSmbiosDataHob (0, &SmbiosHobPtr);
- if (EFI_ERROR (Status)) {
- ASSERT(FALSE);
- }
-
- DEBUG ((DEBUG_INFO, "U5 MC Coreplex SMBIOS DATA HOB at address 0x%x\n", SmbiosHobPtr));
-
- return EFI_SUCCESS;
-}
-
-/**
- Perform Platform PEI initialization.
-
- @param FileHandle Handle of the file being invoked.
- @param PeiServices Describes the list of possible PEI Services.
-
- @return EFI_SUCCESS The PEIM initialized successfully.
-
-**/
-EFI_STATUS
-EFIAPI
-InitializePlatform (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
- )
-{
- EFI_STATUS Status;
-
- DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));
-
- BootModeInitialization ();
- DEBUG ((DEBUG_INFO, "Platform BOOT mode initiated.\n"));
- PublishPeiMemory ();
- DEBUG ((DEBUG_INFO, "PEI memory published.\n"));
- InitializeRamRegions ();
- DEBUG ((DEBUG_INFO, "Platform RAM regions initiated.\n"));
-
- if (mBootMode != BOOT_ON_S3_RESUME) {
- PeiFvInitialization ();
- MemMapInitialization ();
- }
-
- MiscInitialization ();
- Status = BuildCoreInformationHob ();
- if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "Fail to build processor informstion HOB.\n"));
- ASSERT(FALSE);
- }
- return EFI_SUCCESS;
-}
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/PlatformPei.inf b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/PlatformPei.inf
deleted file mode 100644
index 0e96c33e8f..0000000000
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Universal/Pei/PlatformPei/PlatformPei.inf
+++ /dev/null
@@ -1,73 +0,0 @@
-## @file
-# Platform PEI driver
-#
-# This module provides platform specific function to detect boot mode.
-#
-# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-[Defines]
- INF_VERSION = 0x0001001b
- BASE_NAME = PlatformPei
- FILE_GUID = 222c386d-5abc-4fb4-b124-fbb82488acf4
- MODULE_TYPE = PEIM
- VERSION_STRING = 1.0
- ENTRY_POINT = InitializePlatform
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = RISCV64
-#
-
-[Sources]
- Fv.c
- MemDetect.c
- Platform.c
-
-[Packages]
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
- Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
- Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
- Silicon/SiFive/SiFive.dec
- UefiCpuPkg/UefiCpuPkg.dec
-
-[Guids]
- gEfiMemoryTypeInformationGuid
- gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid
-
-[LibraryClasses]
- DebugLib
- HobLib
- IoLib
- PciLib
- PeiResourcePublicationLib
- PeiServicesLib
- PeiServicesTablePointerLib
- PeimEntryPoint
- PcdLib
- SiliconSiFiveU5MCCoreplexInfoLib
-
-[Pcd]
- gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
- gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration
- gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize
- gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize
- gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdNumberofU5Cores
- gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdE5MCSupported
-
-
-[Ppis]
- gEfiPeiMasterBootModePpiGuid
-
-[Depex]
- TRUE
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
index afe63c80ba..14d83fb25a 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
@@ -394,7 +394,7 @@
NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
}
- Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/PlatformPei.inf {
+ Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf {
<LibraryClasses>
PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
}
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf
index a1a4b342e3..7471737728 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf
@@ -99,7 +99,7 @@ INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
# RISC-V Platform PEI Driver
-INF Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/PlatformPei.inf
+INF Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
################################################################################
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Fv.c b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Fv.c
deleted file mode 100644
index 060d66238d..0000000000
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Fv.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/** @file
- Build FV related hobs for platform.
-
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
- Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include "PiPei.h"
-#include "Platform.h"
-#include <Library/DebugLib.h>
-#include <Library/HobLib.h>
-#include <Library/PcdLib.h>
-#include <Library/PeiServicesLib.h>
-
-/**
- Publish PEI & DXE (Decompressed) Memory based FVs to let PEI
- and DXE know about them.
-
- @retval EFI_SUCCESS Platform PEI FVs were initialized successfully.
-
-**/
-EFI_STATUS
-PeiFvInitialization (
- VOID
- )
-{
- DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n"));
- //
- // Let DXE know about the DXE FV
- //
- BuildFvHob (PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize));
- DEBUG ((DEBUG_INFO, "Platform builds DXE FV at %x, size %x.\n",
- PcdGet32 (PcdRiscVDxeFvBase),
- PcdGet32 (PcdRiscVDxeFvSize)));
-
- //
- // Let PEI know about the DXE FV so it can find the DXE Core
- //
- PeiServicesInstallFvInfoPpi (
- NULL,
- (VOID *)(UINTN) PcdGet32 (PcdRiscVDxeFvBase),
- PcdGet32 (PcdRiscVDxeFvSize),
- NULL,
- NULL
- );
-
- return EFI_SUCCESS;
-}
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.h b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.h
deleted file mode 100644
index c2cdd6d75b..0000000000
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Universal/Pei/PlatformPei/Platform.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/** @file
- Platform PEI module include file.
-
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#ifndef PLATFORM_PEI_H_INCLUDED_
-#define PLATFORM_PEI_H_INCLUDED_
-
-VOID
-AddIoMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
- );
-
-VOID
-AddIoMemoryRangeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- EFI_PHYSICAL_ADDRESS MemoryLimit
- );
-
-VOID
-AddMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
- );
-
-VOID
-AddMemoryRangeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- EFI_PHYSICAL_ADDRESS MemoryLimit
- );
-
-VOID
-AddUntestedMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
- );
-
-VOID
-AddReservedMemoryBaseSizeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- UINT64 MemorySize
- );
-
-VOID
-AddUntestedMemoryRangeHob (
- EFI_PHYSICAL_ADDRESS MemoryBase,
- EFI_PHYSICAL_ADDRESS MemoryLimit
- );
-
-VOID
-AddressWidthInitialization (
- VOID
- );
-
-EFI_STATUS
-PublishPeiMemory (
- VOID
- );
-
-UINT32
-GetSystemMemorySizeBelow4gb (
- VOID
- );
-
-VOID
-InitializeRamRegions (
- VOID
- );
-
-EFI_STATUS
-PeiFvInitialization (
- VOID
- );
-
-EFI_STATUS
-InitializeXen (
- VOID
- );
-
-#endif // _PLATFORM_PEI_H_INCLUDED_
--
2.33.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [edk2-platforms][PATCH v2 02/14] RISC-V: Split SMBIOS out of PlatformPei
2021-10-06 11:56 [edk2-platforms][PATCH v2 00/14] Use generic OpenSBI platform Daniel Schaefer
2021-10-06 11:56 ` [edk2-platforms][PATCH v2 01/14] U5SeriesPkg: Deduplicate PlatformPei Daniel Schaefer
@ 2021-10-06 11:56 ` Daniel Schaefer
2021-10-06 11:56 ` [edk2-platforms][PATCH v2 03/14] RISC-V: Use U5 SMBIOS library only for those platforms Daniel Schaefer
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Daniel Schaefer @ 2021-10-06 11:56 UTC (permalink / raw)
To: devel; +Cc: Abner Chang, Sunil V L
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c | 17 +---------
Platform/SiFive/U5SeriesPkg/Include/SiFiveU5MCCoreplex.h | 33 ++++----------------
Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 32 ++++++++++++++++++-
3 files changed, 38 insertions(+), 44 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
index 24192c692b..8586a94b62 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/Platform.c
@@ -254,22 +254,7 @@ BuildCoreInformationHob (
VOID
)
{
- EFI_STATUS Status;
- RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosHobPtr;
-
- // TODO: Create SMBIOS libs for non-U540 platforms
- Status = CreateU5MCCoreplexProcessorSpecificDataHob (0);
- if (EFI_ERROR (Status)) {
- ASSERT(FALSE);
- }
- Status = CreateU5MCProcessorSmbiosDataHob (0, &SmbiosHobPtr);
- if (EFI_ERROR (Status)) {
- ASSERT(FALSE);
- }
-
- DEBUG ((DEBUG_INFO, "U5 MC Coreplex SMBIOS DATA HOB at address 0x%x\n", SmbiosHobPtr));
-
- return EFI_SUCCESS;
+ return BuildRiscVSmbiosHobs ();
}
/**
diff --git a/Platform/SiFive/U5SeriesPkg/Include/SiFiveU5MCCoreplex.h b/Platform/SiFive/U5SeriesPkg/Include/SiFiveU5MCCoreplex.h
index 5d70e26f83..363b34a8f1 100644
--- a/Platform/SiFive/U5SeriesPkg/Include/SiFiveU5MCCoreplex.h
+++ b/Platform/SiFive/U5SeriesPkg/Include/SiFiveU5MCCoreplex.h
@@ -1,7 +1,7 @@
/** @file
SiFive U54 Coreplex library definitions.
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -17,35 +17,14 @@
#define SIFIVE_U5MC_COREPLEX_MC_HART_ID 0
/**
- Build up U5MC coreplex processor core-specific information.
+ Build processor and platform information for the U5 platform
- @param UniqueId U5MC unique ID.
-
- @return EFI_STATUS
+ @return EFI_SUCCESS Status.
**/
EFI_STATUS
-EFIAPI
-CreateU5MCCoreplexProcessorSpecificDataHob (
- IN UINTN UniqueId
- );
-
-/**
- Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
- this information and build SMBIOS Type4 and Type7 record.
-
- @param ProcessorUid Unique ID of pysical processor which owns this core.
- @param SmbiosDataHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_HOB. The pointers
- maintained in this structure is only valid before memory is discovered.
- Access to those pointers after memory is installed will cause unexpected issues.
+BuildRiscVSmbiosHobs (
+ VOID
+);
- @return EFI_SUCCESS The PEIM initialized successfully.
-
-**/
-EFI_STATUS
-EFIAPI
-CreateU5MCProcessorSmbiosDataHob (
- IN UINTN ProcessorUid,
- OUT RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosDataHobPtr
- );
#endif
diff --git a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
index b2f74c2a74..bc1b252946 100644
--- a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
+++ b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -1,7 +1,7 @@
/**@file
Build up platform processor information.
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -32,6 +32,7 @@
@return EFI_SUCCESS The PEIM initialized successfully.
**/
+STATIC
EFI_STATUS
EFIAPI
CreateU5MCCoreplexProcessorSpecificDataHob (
@@ -96,6 +97,7 @@ CreateU5MCCoreplexProcessorSpecificDataHob (
@return EFI_SUCCESS The SMBIOS Hobs were created successfully.
**/
+STATIC
EFI_STATUS
EFIAPI
CreateU5MCProcessorSmbiosDataHob (
@@ -163,3 +165,31 @@ CreateU5MCProcessorSmbiosDataHob (
return EFI_SUCCESS;
}
+
+/**
+ Build processor and platform information for the U5 platform
+
+ @return EFI_SUCCESS Status.
+
+**/
+EFI_STATUS
+BuildRiscVSmbiosHobs (
+ VOID
+)
+{
+ EFI_STATUS Status;
+ RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosHobPtr;
+
+ Status = CreateU5MCCoreplexProcessorSpecificDataHob (0);
+ if (EFI_ERROR (Status)) {
+ ASSERT(FALSE);
+ }
+ Status = CreateU5MCProcessorSmbiosDataHob (0, &SmbiosHobPtr);
+ if (EFI_ERROR (Status)) {
+ ASSERT(FALSE);
+ }
+
+ DEBUG ((DEBUG_INFO, "U5 MC Coreplex SMBIOS DATA HOB at address 0x%x\n", SmbiosHobPtr));
+
+ return EFI_SUCCESS;
+}
--
2.33.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [edk2-platforms][PATCH v2 03/14] RISC-V: Use U5 SMBIOS library only for those platforms
2021-10-06 11:56 [edk2-platforms][PATCH v2 00/14] Use generic OpenSBI platform Daniel Schaefer
2021-10-06 11:56 ` [edk2-platforms][PATCH v2 01/14] U5SeriesPkg: Deduplicate PlatformPei Daniel Schaefer
2021-10-06 11:56 ` [edk2-platforms][PATCH v2 02/14] RISC-V: Split SMBIOS out of PlatformPei Daniel Schaefer
@ 2021-10-06 11:56 ` Daniel Schaefer
2021-10-06 11:56 ` [edk2-platforms][PATCH v2 04/14] Silicon/RISC-V: Introduce FirmwareContext library Daniel Schaefer
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Daniel Schaefer @ 2021-10-06 11:56 UTC (permalink / raw)
To: devel; +Cc: Abner Chang, Sunil V L
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
Platform/RISC-V/PlatformPkg/Library/PeiCoreInfoHobLibNull/CoreInfoHob.c | 37 +++++++++++++++++
Platform/RISC-V/PlatformPkg/Library/PeiCoreInfoHobLibNull/PeiCoreInfoHobLib.inf | 43 ++++++++++++++++++++
Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf | 2 +-
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc | 2 +-
Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc | 2 +-
Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 4 +-
6 files changed, 85 insertions(+), 5 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreInfoHobLibNull/CoreInfoHob.c b/Platform/RISC-V/PlatformPkg/Library/PeiCoreInfoHobLibNull/CoreInfoHob.c
new file mode 100644
index 0000000000..9aad7991bc
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreInfoHobLibNull/CoreInfoHob.c
@@ -0,0 +1,37 @@
+/**@file
+ Build up platform processor information.
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/BaseMemoryLib.h>
+
+#include <ProcessorSpecificHobData.h>
+
+
+/**
+ Build processor and platform information for a generic RISC-V
+
+ @return EFI_SUCCESS Status.
+
+**/
+EFI_STATUS
+BuildRiscVSmbiosHobs (
+ VOID
+)
+{
+ return EFI_SUCCESS;
+}
diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreInfoHobLibNull/PeiCoreInfoHobLib.inf b/Platform/RISC-V/PlatformPkg/Library/PeiCoreInfoHobLibNull/PeiCoreInfoHobLib.inf
new file mode 100644
index 0000000000..5a8db5071f
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreInfoHobLibNull/PeiCoreInfoHobLib.inf
@@ -0,0 +1,43 @@
+## @file
+# Library instance to create core information HOB
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVCoreplexInfoLibNull
+ FILE_GUID = E5783AF0-B7C5-4FAA-BAB4-D52C06B98BBE
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVCoreplexInfoLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ CoreInfoHob.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ MemoryAllocationLib
+ PrintLib
+
+[Guids]
+
+[Ppis]
+
+[FixedPcd]
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
index e7f5eef630..0db88abba4 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
@@ -51,7 +51,7 @@
PeiServicesTablePointerLib
PeimEntryPoint
PcdLib
- SiliconSiFiveU5MCCoreplexInfoLib
+ RiscVCoreplexInfoLib
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
index fce1c50578..1dc6405a20 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
@@ -212,7 +212,7 @@
# RISC-V core libraries
#
SiliconSiFiveU54CoreInfoLib|Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
- SiliconSiFiveU5MCCoreplexInfoLib|Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
+ RiscVCoreplexInfoLib|Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
[LibraryClasses.common.DXE_CORE]
TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
index 14d83fb25a..18a99b86d8 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
@@ -213,7 +213,7 @@
# RISC-V core libraries
#
SiliconSiFiveU54CoreInfoLib|Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
- SiliconSiFiveU5MCCoreplexInfoLib|Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
+ RiscVCoreplexInfoLib|Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
[LibraryClasses.common.DXE_CORE]
TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
diff --git a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
index b3124a6daf..d741f04747 100644
--- a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
+++ b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
@@ -1,7 +1,7 @@
## @file
# Library instance to create core information HOB
#
-# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -13,7 +13,7 @@
FILE_GUID = 4E397A71-5164-4E69-9884-70CBE2740AAB
MODULE_TYPE = PEIM
VERSION_STRING = 1.0
- LIBRARY_CLASS = SiliconSiFiveU5MCCoreplexInfoLib
+ LIBRARY_CLASS = RiscVCoreplexInfoLib
#
# The following information is for reference only and not required by the build tools.
--
2.33.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [edk2-platforms][PATCH v2 04/14] Silicon/RISC-V: Introduce FirmwareContext library
2021-10-06 11:56 [edk2-platforms][PATCH v2 00/14] Use generic OpenSBI platform Daniel Schaefer
` (2 preceding siblings ...)
2021-10-06 11:56 ` [edk2-platforms][PATCH v2 03/14] RISC-V: Use U5 SMBIOS library only for those platforms Daniel Schaefer
@ 2021-10-06 11:56 ` Daniel Schaefer
2021-10-06 11:56 ` [edk2-platforms][PATCH v2 05/14] Silicon/RISC-V: PeiServiceTableLib uses RiscVFirmwareContextLib Daniel Schaefer
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Daniel Schaefer @ 2021-10-06 11:56 UTC (permalink / raw)
To: devel; +Cc: Sunil V L
From: Abner Chang <abner.chang@hpe.com>
Add RISC-V FirmwareContext library for different FirmwareContext
implementations. This instance uses SBI firmware extension to
get the pointer to FirmwareContext.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h | 3 +-
Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h | 14 +++++-
Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h | 43 ++++++++++++++++
Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S | 34 ++++++++++++-
Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c | 52 ++++++++++++++++++++
Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf | 34 +++++++++++++
Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c | 48 ++++++++++++++++++
Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf | 33 +++++++++++++
Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c | 48 ++++++++++++++++++
Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf | 34 +++++++++++++
Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 1 +
Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 4 +-
12 files changed, 344 insertions(+), 4 deletions(-)
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
index 2a992394ed..f6726bda24 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
@@ -1,7 +1,7 @@
/** @file
RISC-V package definitions.
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -96,6 +96,7 @@
#define SSTATUS_SIE_BIT_POSITION 1
#define SSTATUS_SPP_BIT_POSITION 8
#define RISCV_CSR_SUPERVISOR_SIE 0x104
+#define RISCV_CSR_SUPERVISOR_STVEC 0x105
#define RISCV_CSR_SUPERVISOR_SSCRATCH 0x140
#define RISCV_CSR_SUPERVISOR_SEPC 0x141
#define RISCV_CSR_SUPERVISOR_SCAUSE 0x142
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
index f37d4c20d0..f70723567e 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
@@ -1,7 +1,7 @@
/** @file
RISC-V CPU library definitions.
- Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -68,4 +68,16 @@ RiscVReadMachineImplementId (VOID);
VOID
RiscVSetSupervisorAddressTranslationRegister(UINT64);
+VOID
+RiscVSetSupervisorScratch (UINT64);
+
+UINT64
+RiscVGetSupervisorScratch (VOID);
+
+VOID
+RiscVSetSupervisorStvec (UINT64);
+
+UINT64
+RiscVGetSupervisorStvec (VOID);
+
#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h
new file mode 100644
index 0000000000..f35c4e0c51
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVFirmwareContextLib.h
@@ -0,0 +1,43 @@
+/** @file
+ Library to get/set Firmware Context.
+
+ Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_FIRMWARE_CONTEXT_LIB_H_
+#define RISCV_FIRMWARE_CONTEXT_LIB_H_
+
+#include <Uefi.h>
+#include <IndustryStandard/RiscVOpensbi.h>
+
+/**
+ Get pointer to OpenSBI Firmware Context
+
+ Get the pointer of firmware context.
+
+ @param FirmwareContextPtr Pointer to retrieve pointer to the
+ Firmware Context.
+**/
+VOID
+EFIAPI
+GetFirmwareContextPointer (
+ IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+ );
+
+/**
+ Set pointer to OpenSBI Firmware Context
+
+ Set the pointer of firmware context.
+
+ @param FirmwareContextPtr Pointer to Firmware Context.
+**/
+VOID
+EFIAPI
+SetFirmwareContextPointer (
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+ );
+
+#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
index 06ba80cb5f..e242c9b866 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/Cpu.S
@@ -2,7 +2,7 @@
//
// RISC-V CPU functions.
//
-// Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Copyright (c) 2016 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -101,6 +101,38 @@ ASM_FUNC (RiscVReadMachineImplementId)
csrr a0, RISCV_CSR_MACHINE_MIMPID
ret
+//
+// Set Supervisor mode scratch.
+// @param a0 : Value set to Supervisor mode scratch
+//
+ASM_FUNC (RiscVSetSupervisorScratch)
+ csrrw a1, RISCV_CSR_SUPERVISOR_SSCRATCH, a0
+ ret
+
+//
+// Get Supervisor mode scratch.
+// @retval a0 : Value in Supervisor mode scratch
+//
+ASM_FUNC (RiscVGetSupervisorScratch)
+ csrr a0, RISCV_CSR_SUPERVISOR_SSCRATCH
+ ret
+
+//
+// Set Supervisor mode trap vector.
+// @param a0 : Value set to Supervisor mode trap vector
+//
+ASM_FUNC (RiscVSetSupervisorStvec)
+ csrrw a1, RISCV_CSR_SUPERVISOR_STVEC, a0
+ ret
+
+//
+// Get Supervisor mode scratch.
+// @retval a0 : Value in Supervisor mode trap vector
+//
+ASM_FUNC (RiscVGetSupervisorStvec)
+ csrr a0, RISCV_CSR_SUPERVISOR_STVEC
+ ret
+
//
// Set Supervisor Address Translation and
// Protection Register.
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
new file mode 100644
index 0000000000..6125618eaf
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
@@ -0,0 +1,52 @@
+/** @file
+ This iinstance uses RISC-V OpenSBI Firmware Extension SBI to
+ get the pointer of firmware context.
+
+ Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+#include <Library/RiscVEdk2SbiLib.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_platform.h>
+
+/**
+ Get pointer to OpenSBI Firmware Context
+
+ Get the pointer of firmware context through OpenSBI FW Extension SBI.
+
+ @param FirmwareContextPtr Pointer to retrieve pointer to the
+ Firmware Context.
+**/
+VOID
+EFIAPI
+GetFirmwareContextPointer (
+ IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+ )
+{
+ SbiGetFirmwareContext (FirmwareContextPtr);
+}
+
+/**
+ Set the pointer to OpenSBI Firmware Context
+
+ Set the pointer of firmware context through OpenSBI FW Extension SBI.
+
+ @param FirmwareContextPtr Pointer to Firmware Context.
+**/
+VOID
+EFIAPI
+SetFirmwareContextPointer (
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+ )
+{
+ //
+ // We don't have to set firmware context pointer using
+ // OpenSBI FW Extension SBI.
+ //
+}
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
new file mode 100644
index 0000000000..168b705453
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
@@ -0,0 +1,34 @@
+## @file
+# Instance of OpebSBI Firmware Conext Library
+#
+# This iinstance uses RISC-V OpenSBI Firmware Extension SBI.
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVFirmwareContextSbiLib
+ FILE_GUID = 3709E048-6794-427A-B728-BFE3FFD6D461
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVFirmwareContextLib|PEIM PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+[Sources]
+ RiscVFirmwareContextSbiLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+ RiscVEdk2SbiLib
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c
new file mode 100644
index 0000000000..2504e17132
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.c
@@ -0,0 +1,48 @@
+/** @file
+ This instance uses Supervisor mode SCRATCH CSR to get/set the
+ pointer of firmware context.
+
+ Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+#include <IndustryStandard/RiscVOpensbi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+
+/**
+ Get pointer to OpenSBI Firmware Context
+
+ Get the pointer of firmware context through Supervisor mode SCRATCH CSR.
+
+ @param FirmwareContextPtr Pointer to retrieve pointer to the
+ Firmware Context.
+**/
+VOID
+EFIAPI
+GetFirmwareContextPointer (
+ IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+ )
+{
+ *FirmwareContextPtr = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)RiscVGetSupervisorScratch ();
+}
+
+/**
+ Set the pointer to OpenSBI Firmware Context
+
+ Set the pointer of firmware context through Supervisor mode SCRATCH CSR.
+
+ @param FirmwareContextPtr Pointer to Firmware Context.
+**/
+VOID
+EFIAPI
+SetFirmwareContextPointer (
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+ )
+{
+ RiscVSetSupervisorScratch ((UINT64)FirmwareContextPtr);
+}
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
new file mode 100644
index 0000000000..750c1cf51f
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
@@ -0,0 +1,33 @@
+## @file
+# Instance of OpebSBI Firmware Conext Library
+#
+# This instance uses RISC-V Supervisor mode SCRATCH CSR
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVFirmwareContextSscratchLib
+ FILE_GUID = 3709E048-6794-427A-B728-BFE3FFD6D461
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVFirmwareContextLib|PEIM PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+[Sources]
+ RiscVFirmwareContextSscratchLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
new file mode 100644
index 0000000000..7d1675355a
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
@@ -0,0 +1,48 @@
+/** @file
+ This instance uses This iinstance Supervisor mode STVEC CSR to
+ get/set the pointer of firmware context.
+
+ Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+#include <IndustryStandard/RiscVOpensbi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+
+/**
+ Get pointer to OpenSBI Firmware Context
+
+ Get the pointer of firmware context through Supervisor mode STVEC CSR.
+
+ @param FirmwareContextPtr Pointer to retrieve pointer to the
+ Firmware Context.
+**/
+VOID
+EFIAPI
+GetFirmwareContextPointer (
+ IN OUT EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT **FirmwareContextPtr
+ )
+{
+ *FirmwareContextPtr = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)RiscVGetSupervisorStvec ();
+}
+
+/**
+ Set pointer to OpenSBI Firmware Context
+
+ Set the pointer of firmware context through Supervisor mode STVEC CSR
+
+ @param FirmwareContextPtr Pointer to Firmware Context.
+**/
+VOID
+EFIAPI
+SetFirmwareContextPointer (
+ IN EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContextPtr
+ )
+{
+ RiscVSetSupervisorStvec ((UINT64)FirmwareContextPtr);
+}
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
new file mode 100644
index 0000000000..fa894cda91
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.inf
@@ -0,0 +1,34 @@
+## @file
+# Instance of OpebSBI Firmware Conext Library
+#
+# This iinstance Supervisor mode STVEC CSR
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVFirmwareContextStvecLib
+ FILE_GUID = 42DCFFAC-1DBD-4264-80A3-85CC7167AC82
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVFirmwareContextLib|PEIM PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+[Sources]
+ RiscVFirmwareContextStvecLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+
+
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
index 0b64b33f0f..08279a97b1 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
@@ -24,6 +24,7 @@
RiscVPlatformDxeIplLib|Include/Library/RiscVPlatformDxeIpl.h
RiscVCpuLib|Include/Library/RiscVCpuLib.h
RiscVEdk2SbiLib|Include/Library/RiscVEdk2SbiLib.h
+ RiscVFirmwareContextLib|Include/Library/RiscVFirmwareContextLib.h
[Guids]
gUefiRiscVPkgTokenSpaceGuid = { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}}
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
index 5c5cfcb525..1292ba1bea 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
@@ -65,13 +65,14 @@
UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf
RiscVPlatformTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
- PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
[LibraryClasses.common.PEI_CORE]
PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+ RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
[LibraryClasses.common.PEIM]
PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+ RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
@@ -92,6 +93,7 @@
[Components]
Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
+ Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
Silicon/RISC-V/ProcessorPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
--
2.33.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [edk2-platforms][PATCH v2 05/14] Silicon/RISC-V: PeiServiceTableLib uses RiscVFirmwareContextLib
2021-10-06 11:56 [edk2-platforms][PATCH v2 00/14] Use generic OpenSBI platform Daniel Schaefer
` (3 preceding siblings ...)
2021-10-06 11:56 ` [edk2-platforms][PATCH v2 04/14] Silicon/RISC-V: Introduce FirmwareContext library Daniel Schaefer
@ 2021-10-06 11:56 ` Daniel Schaefer
2021-10-06 11:56 ` [edk2-platforms][PATCH v2 06/14] SiFive/U5SeriesPkg: Use FirmwareContext library Daniel Schaefer
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Daniel Schaefer @ 2021-10-06 11:56 UTC (permalink / raw)
To: devel; +Cc: Sunil V L
From: Abner Chang <abner.chang@hpe.com>
Use RISC-V FirmwareContext library to set and get the
pointer of PeiService.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf | 4 ++--
Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c | 8 ++++----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf b/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
index f23272016b..fa9fe78518 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+++ b/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
@@ -4,7 +4,7 @@
# PEI Services Table Pointer Library implementation that retrieves a pointer to the
# PEI Services Table from a RISC-V OpenSBI sbi_platform firmware context structure.
#
-# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -35,5 +35,5 @@
[LibraryClasses]
DebugLib
RiscVCpuLib
- RiscVEdk2SbiLib
+ RiscVFirmwareContextLib
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c b/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
index 0c1473e932..9aa74b4f9f 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
@@ -1,7 +1,7 @@
/** @file
PEI Services Table Pointer Library.
- Copyright (c) 2019 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2019 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -9,7 +9,7 @@
#include <PiPei.h>
#include <Library/DebugLib.h>
#include <Library/RiscVCpuLib.h>
-#include <Library/RiscVEdk2SbiLib.h>
+#include <Library/RiscVFirmwareContextLib.h>
#include <Library/PeiServicesTablePointerLib.h>
#include <sbi/sbi_scratch.h>
#include <sbi/sbi_platform.h>
@@ -32,8 +32,8 @@ SetPeiServicesTablePointer (
)
{
EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
- SbiGetFirmwareContext (&FirmwareContext);
+ GetFirmwareContextPointer (&FirmwareContext);
FirmwareContext->PeiServiceTable = (VOID *)(UINTN)PeiServicesTablePointer;
DEBUG ((DEBUG_INFO, "Set PEI Service 0x%x at OpenSBI Firmware Context at 0x%x\n",
@@ -61,8 +61,8 @@ GetPeiServicesTablePointer (
)
{
EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
- SbiGetFirmwareContext (&FirmwareContext);
+ GetFirmwareContextPointer (&FirmwareContext);
return (CONST EFI_PEI_SERVICES **)FirmwareContext->PeiServiceTable;
}
--
2.33.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [edk2-platforms][PATCH v2 06/14] SiFive/U5SeriesPkg: Use FirmwareContext library
2021-10-06 11:56 [edk2-platforms][PATCH v2 00/14] Use generic OpenSBI platform Daniel Schaefer
` (4 preceding siblings ...)
2021-10-06 11:56 ` [edk2-platforms][PATCH v2 05/14] Silicon/RISC-V: PeiServiceTableLib uses RiscVFirmwareContextLib Daniel Schaefer
@ 2021-10-06 11:56 ` Daniel Schaefer
2021-10-06 11:56 ` [edk2-platforms][PATCH v2 07/14] U540: Add and build device tree Daniel Schaefer
2021-10-06 11:56 ` [edk2-platforms][PATCH v2 08/14] RISC-V/PlatformPkg: Build DeviceTree and use that in SEC Daniel Schaefer
7 siblings, 0 replies; 9+ messages in thread
From: Daniel Schaefer @ 2021-10-06 11:56 UTC (permalink / raw)
To: devel; +Cc: Sunil V L
From: Abner Chang <abner.chang@hpe.com>
Use RISC-V FirmwareContext library to set and get the
pointer of PeiService on SiFive U5 series platforms.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
index 18a99b86d8..2b00176c27 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
@@ -174,6 +174,7 @@
[LibraryClasses.common.PEI_CORE]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+ RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
@@ -190,6 +191,7 @@
[LibraryClasses.common.PEIM]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+ RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
--
2.33.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [edk2-platforms][PATCH v2 07/14] U540: Add and build device tree
2021-10-06 11:56 [edk2-platforms][PATCH v2 00/14] Use generic OpenSBI platform Daniel Schaefer
` (5 preceding siblings ...)
2021-10-06 11:56 ` [edk2-platforms][PATCH v2 06/14] SiFive/U5SeriesPkg: Use FirmwareContext library Daniel Schaefer
@ 2021-10-06 11:56 ` Daniel Schaefer
2021-10-06 11:56 ` [edk2-platforms][PATCH v2 08/14] RISC-V/PlatformPkg: Build DeviceTree and use that in SEC Daniel Schaefer
7 siblings, 0 replies; 9+ messages in thread
From: Daniel Schaefer @ 2021-10-06 11:56 UTC (permalink / raw)
To: devel; +Cc: daniel.schaefer, Abner Chang, Sunil V L
Device Tree is taken from Uboot.
Cc: Daniel Schaefer <daniel.schaefer>
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree.fdf.inc | 35 +++
Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/U540DeviceTree.inf | 25 ++
Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/fu540-c000.dtsi | 287 ++++++++++++++++++++
Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/gpio.h | 42 +++
Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/hifive-unleashed-a00.dts | 106 ++++++++
Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/sifive-fu540-prci.h | 18 ++
Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc | 2 +
Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf | 6 +
Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc | 8 +-
9 files changed, 526 insertions(+), 3 deletions(-)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree.fdf.inc
new file mode 100644
index 0000000000..fb28be2767
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree.fdf.inc
@@ -0,0 +1,35 @@
+## @file
+# FDF include file with Layout Regions that define an empty variable store.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (C) 2014, Red Hat, Inc.
+# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+$(DTB_OFFSET)|$(DTB_SIZE)
+gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase|gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvSize
+FV = DTBFV
+
+[FV.DTBFV]
+BlockSize = 0x1000
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+INF RuleOverride = DTB Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/U540DeviceTree.inf
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/U540DeviceTree.inf b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/U540DeviceTree.inf
new file mode 100644
index 0000000000..92c4211ccd
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/U540DeviceTree.inf
@@ -0,0 +1,25 @@
+## @file
+#
+# Device tree description of the Hifive Unleashed platform
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = U540DeviceTree
+ FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDefaultDtbFileGuid
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ gpio.h
+ hifive-unleashed-a00.dts
+ fu540-c000.dtsi
+ sifive-fu540-prci.h
+
+[Packages]
+ MdePkg/MdePkg.dec
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/fu540-c000.dtsi b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/fu540-c000.dtsi
new file mode 100644
index 0000000000..e44b6f7c56
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/fu540-c000.dtsi
@@ -0,0 +1,287 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2018-2019 SiFive, Inc */
+
+/dts-v1/;
+
+/*#include <dt-bindings/clock/sifive-fu540-prci.h>*/
+#include "sifive-fu540-prci.h"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,fu540-c000", "sifive,fu540";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ ethernet0 = ð0;
+ };
+
+ chosen {
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu0: cpu@0 {
+ compatible = "sifive,e51", "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu1: cpu@1 {
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ next-level-cache = <&l2cache>;
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu2: cpu@2 {
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <2>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ next-level-cache = <&l2cache>;
+ cpu2_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu3: cpu@3 {
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <3>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ next-level-cache = <&l2cache>;
+ cpu3_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu4: cpu@4 {
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <4>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ next-level-cache = <&l2cache>;
+ cpu4_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
+ ranges;
+ plic0: interrupt-controller@c000000 {
+ #interrupt-cells = <1>;
+ compatible = "sifive,plic-1.0.0";
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ riscv,ndev = <53>;
+ interrupt-controller;
+ interrupts-extended = <
+ &cpu0_intc 0xffffffff
+ &cpu1_intc 0xffffffff &cpu1_intc 9
+ &cpu2_intc 0xffffffff &cpu2_intc 9
+ &cpu3_intc 0xffffffff &cpu3_intc 9
+ &cpu4_intc 0xffffffff &cpu4_intc 9>;
+ };
+ prci: clock-controller@10000000 {
+ compatible = "sifive,fu540-c000-prci";
+ reg = <0x0 0x10000000 0x0 0x1000>;
+ clocks = <&hfclk>, <&rtcclk>;
+ #clock-cells = <1>;
+ };
+ uart0: serial@10010000 {
+ compatible = "sifive,fu540-c000-uart", "sifive,uart0";
+ reg = <0x0 0x10010000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <4>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ status = "disabled";
+ };
+ dma: dma@3000000 {
+ compatible = "sifive,fu540-c000-pdma";
+ reg = <0x0 0x3000000 0x0 0x8000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <23 24 25 26 27 28 29 30>;
+ #dma-cells = <1>;
+ };
+ uart1: serial@10011000 {
+ compatible = "sifive,fu540-c000-uart", "sifive,uart0";
+ reg = <0x0 0x10011000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <5>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ status = "disabled";
+ };
+ i2c0: i2c@10030000 {
+ compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
+ reg = <0x0 0x10030000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <50>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ reg-shift = <2>;
+ reg-io-width = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ qspi0: spi@10040000 {
+ compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10040000 0x0 0x1000
+ 0x0 0x20000000 0x0 0x10000000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <51>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ qspi1: spi@10041000 {
+ compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10041000 0x0 0x1000
+ 0x0 0x30000000 0x0 0x10000000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <52>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ qspi2: spi@10050000 {
+ compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10050000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <6>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ eth0: ethernet@10090000 {
+ compatible = "sifive,fu540-c000-gem";
+ interrupt-parent = <&plic0>;
+ interrupts = <53>;
+ reg = <0x0 0x10090000 0x0 0x2000
+ 0x0 0x100a0000 0x0 0x1000>;
+ local-mac-address = [00 00 00 00 00 00];
+ clock-names = "pclk", "hclk";
+ clocks = <&prci PRCI_CLK_GEMGXLPLL>,
+ <&prci PRCI_CLK_GEMGXLPLL>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ pwm0: pwm@10020000 {
+ compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
+ reg = <0x0 0x10020000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <42 43 44 45>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+ pwm1: pwm@10021000 {
+ compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
+ reg = <0x0 0x10021000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <46 47 48 49>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+ l2cache: cache-controller@2010000 {
+ compatible = "sifive,fu540-c000-ccache", "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <1024>;
+ cache-size = <2097152>;
+ cache-unified;
+ interrupt-parent = <&plic0>;
+ interrupts = <1 2 3>;
+ reg = <0x0 0x2010000 0x0 0x1000>;
+ };
+ gpio: gpio@10060000 {
+ compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
+ interrupt-parent = <&plic0>;
+ interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>,
+ <14>, <15>, <16>, <17>, <18>, <19>, <20>,
+ <21>, <22>;
+ reg = <0x0 0x10060000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/gpio.h b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/gpio.h
new file mode 100644
index 0000000000..c029467e82
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/gpio.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for most GPIO bindings.
+ *
+ * Most GPIO bindings include a flags cell as part of the GPIO specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_GPIO_H
+#define _DT_BINDINGS_GPIO_GPIO_H
+
+/* Bit 0 express polarity */
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
+/* Bit 1 express single-endedness */
+#define GPIO_PUSH_PULL 0
+#define GPIO_SINGLE_ENDED 2
+
+/* Bit 2 express Open drain or open source */
+#define GPIO_LINE_OPEN_SOURCE 0
+#define GPIO_LINE_OPEN_DRAIN 4
+
+/*
+ * Open Drain/Collector is the combination of single-ended open drain interface.
+ * Open Source/Emitter is the combination of single-ended open source interface.
+ */
+#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)
+#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)
+
+/* Bit 3 express GPIO suspend/resume and reset persistence */
+#define GPIO_PERSISTENT 0
+#define GPIO_TRANSITORY 8
+
+/* Bit 4 express pull up */
+#define GPIO_PULL_UP 16
+
+/* Bit 5 express pull down */
+#define GPIO_PULL_DOWN 32
+
+#endif
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/hifive-unleashed-a00.dts b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/hifive-unleashed-a00.dts
new file mode 100644
index 0000000000..df06f1c8c4
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/hifive-unleashed-a00.dts
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2018-2019 SiFive, Inc */
+
+#include "fu540-c000.dtsi"
+/*#include <dt-bindings/gpio/gpio.h>*/
+#include "gpio.h"
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+#define RTCCLK_FREQ 1000000
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "SiFive HiFive Unleashed A00";
+ compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ cpus {
+ timebase-frequency = <RTCCLK_FREQ>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x2 0x00000000>;
+ };
+
+ soc {
+ };
+
+ hfclk: hfclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <33333333>;
+ clock-output-names = "hfclk";
+ };
+
+ rtcclk: rtcclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <RTCCLK_FREQ>;
+ clock-output-names = "rtcclk";
+ };
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&qspi0 {
+ status = "okay";
+ flash@0 {
+ compatible = "issi,is25wp256", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
+&qspi2 {
+ status = "okay";
+ mmc@0 {
+ compatible = "mmc-spi-slot";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ voltage-ranges = <3300 3300>;
+ disable-wp;
+ };
+};
+
+ð0 {
+ status = "okay";
+ phy-mode = "gmii";
+ phy-handle = <&phy0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&gpio {
+ status = "okay";
+};
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/sifive-fu540-prci.h b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/sifive-fu540-prci.h
new file mode 100644
index 0000000000..6a0b70a37d
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/sifive-fu540-prci.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018-2019 SiFive, Inc.
+ * Wesley Terpstra
+ * Paul Walmsley
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H
+#define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H
+
+/* Clock indexes for use by Device Tree data and the PRCI driver */
+
+#define PRCI_CLK_COREPLL 0
+#define PRCI_CLK_DDRPLL 1
+#define PRCI_CLK_GEMGXLPLL 2
+#define PRCI_CLK_TLCLK 3
+
+#endif
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
index 2b00176c27..e971993b7b 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
@@ -489,6 +489,8 @@
MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+ Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/U540DeviceTree.inf
+
#
# SMBIOS Support
#
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf
index 7471737728..820e19d113 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf
@@ -33,6 +33,7 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|gUefiRiscVPlatformPkgToken
FV = FVMAIN_COMPACT
!include VarStore.fdf.inc
+!include DeviceTree.fdf.inc
################################################################################
@@ -325,3 +326,8 @@ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
RAW ACPI |.acpi
RAW ASL |.aml
}
+
+[Rule.Common.USER_DEFINED.DTB]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW BIN |.dtb
+ }
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
index f72947da61..723632dc79 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
@@ -10,8 +10,8 @@
DEFINE BLOCK_SIZE = 0x1000
DEFINE FW_BASE_ADDRESS = 0x80000000
-DEFINE FW_SIZE = 0x00800000
-DEFINE FW_BLOCKS = 0x800
+DEFINE FW_SIZE = 0x00820000
+DEFINE FW_BLOCKS = 0x820
#
# 0x000000-0x7DFFFF code
@@ -32,13 +32,15 @@ DEFINE FVMAIN_OFFSET = 0x00100000 # Must be power of 2 for PMP setting
DEFINE FVMAIN_SIZE = 0x0018C000
DEFINE VARS_OFFSET = 0x007E0000
DEFINE VARS_SIZE = 0x00020000
+DEFINE DTB_OFFSET = 0x00800000
+DEFINE DTB_SIZE = 0x00002000
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress = $(FW_BASE_ADDRESS) + $(VARS_OFFSET)
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize = $(VARS_SIZE)
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize = $(BLOCK_SIZE)
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress = $(CODE_BASE_ADDRESS)
-SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress = $(CODE_BASE_ADDRESS) + $(SECFV_SIZE) + $(PEIFV_SIZE) + $(SCRATCH_SIZE)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress = $(CODE_BASE_ADDRESS) + $(SECFV_SIZE) + $(PEIFV_SIZE) + $(SCRATCH_SIZE) + $(DTB_SIZE)
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize = 8192
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase = $(CODE_BASE_ADDRESS) + $(SCRATCH_OFFSET)
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize = $(SCRATCH_SIZE)
--
2.33.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [edk2-platforms][PATCH v2 08/14] RISC-V/PlatformPkg: Build DeviceTree and use that in SEC
2021-10-06 11:56 [edk2-platforms][PATCH v2 00/14] Use generic OpenSBI platform Daniel Schaefer
` (6 preceding siblings ...)
2021-10-06 11:56 ` [edk2-platforms][PATCH v2 07/14] U540: Add and build device tree Daniel Schaefer
@ 2021-10-06 11:56 ` Daniel Schaefer
7 siblings, 0 replies; 9+ messages in thread
From: Daniel Schaefer @ 2021-10-06 11:56 UTC (permalink / raw)
To: devel; +Cc: Abner Chang, Sunil V L
OpenSBI uses the device tree for platform specific initialization, so we
need to have it already in SEC.
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 4 ++
Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S | 22 ---------
Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c | 49 ++++++++++++++++++++
Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf | 2 +
Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h | 1 +
5 files changed, 56 insertions(+), 22 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
index 48aeb97431..ad15a155fe 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
@@ -31,6 +31,8 @@
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize|0x0|UINT32|0x00001003
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|0x0|UINT32|0x00001004
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize|0x0|UINT32|0x00001005
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase|0x0|UINT32|0x00001016
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvSize|0x0|UINT32|0x00001017
#
# Definition of EFI Variable region
@@ -66,6 +68,8 @@
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize|0|UINT32|0x00001104
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPeiCorePrivilegeMode|0|UINT32|0x00001105
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdDeviceTreeAddress|0|UINT32|0x00001106
+
[PcdsPatchableInModule]
[PcdsFeatureFlag]
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
index 8434d1a4e0..0e3940180d 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
@@ -75,11 +75,6 @@ _scratch_init:
sd a4, SBI_SCRATCH_FW_START_OFFSET(tp)
sd a5, SBI_SCRATCH_FW_SIZE_OFFSET(tp)
- /*
- * Note: fw_next_arg1() uses a0, a1, and ra
- */
- call fw_next_arg1
- sd a0, SBI_SCRATCH_NEXT_ARG1_OFFSET(tp) /* Save agr1 in scratch buffer*/
/*
Note: fw_next_addr()uses a0, a1, and ra
*/
@@ -500,23 +495,6 @@ _reset_regs:
csrw CSR_MSCRATCH, 0
ret
- .align 3
- .section .entry, "ax", %progbits
- .global fw_prev_arg1
-fw_prev_arg1:
-
- /* We return previous arg1 in 'a0' */
- add a0, zero, zero
- ret
-
- .align 3
- .section .entry, "ax", %progbits
- .global fw_next_arg1
-fw_next_arg1:
- /* We return next arg1 in 'a0' */
- li a0, FixedPcdGet32(PcdRiscVPeiFvBase)
- ret
-
.align 3
.section .entry, "ax", %progbits
.global fw_next_addr
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index fa9ecd789a..0af0b4bac8 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -557,6 +557,12 @@ VOID EFIAPI PeiCore (
&FirmwareContext
));
ThisSbiPlatform->firmware_context = (unsigned long)&FirmwareContext;
+
+ //
+ // Save Flattened Device tree in firmware context
+ //
+ FirmwareContext.FlattenedDeviceTree = FuncArg1;
+
//
// Set firmware context Hart-specific pointer
//
@@ -647,6 +653,42 @@ RiscVOpenSbiHartSwitchMode (
sbi_hart_switch_mode(FuncArg0, FuncArg1, NextAddr, NextMode, NextVirt);
}
+/**
+ Get device tree address
+
+ @retval The address of Device Tree binary.
+**/
+VOID *
+EFIAPI
+GetDeviceTreeAddress (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_COMMON_SECTION_HEADER *FoundSection;
+
+ if (FixedPcdGet32 (PcdDeviceTreeAddress)) {
+ return (VOID *)*((unsigned long *)FixedPcdGet32 (PcdDeviceTreeAddress));
+ } else if (FixedPcdGet32 (PcdRiscVDtbFvBase)) {
+ Status = FindFfsFileAndSection (
+ (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32 (PcdRiscVDtbFvBase),
+ EFI_FV_FILETYPE_FREEFORM,
+ EFI_SECTION_RAW,
+ &FoundSection
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found from FV.\n"));
+ return NULL;
+ }
+ FoundSection ++;
+ return (VOID *)FoundSection;
+ } else {
+ DEBUG ((DEBUG_ERROR, "Must use DTB either from memory or compiled in FW. PCDs configured incorrectly.\n"));
+ ASSERT (FALSE);
+ }
+ return NULL;
+}
+
/**
This function initilizes hart specific information and SBI.
For the boot hart, it boots system through PEI core and initial SBI in the DXE IPL.
@@ -686,6 +728,13 @@ VOID EFIAPI SecCoreStartUpWithStack(
UINT64 NonBootHartMessageLockValue;
EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartFirmwareContext;
+ Scratch->next_arg1 = (unsigned long)GetDeviceTreeAddress ();
+ if (Scratch->next_arg1 == (unsigned long)NULL) {
+ DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n"));
+ ASSERT (FALSE);
+ }
+ DEBUG ((DEBUG_INFO, "DTB address: 0x%08x\n", Scratch->next_arg1));
+
//
// Setup EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC for each hart.
//
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
index 89bcb039a6..78bd75e3ac 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
@@ -57,6 +57,8 @@
[FixedPcd]
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdDeviceTreeAddress
[Pcd]
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
index 2dab696af8..e7ac6d26ee 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
@@ -47,6 +47,7 @@ typedef struct {
typedef struct {
VOID *PeiServiceTable; // PEI Service table
+ UINT64 FlattenedDeviceTree; // Pointer to Flattened Device tree
EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_SUPPORTED];
} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;
--
2.33.0
^ permalink raw reply related [flat|nested] 9+ messages in thread