From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web09.4072.1633660763018722729 for ; Thu, 07 Oct 2021 19:39:31 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: chasel.chiu@intel.com) X-IronPort-AV: E=McAfee;i="6200,9189,10130"; a="287301081" X-IronPort-AV: E=Sophos;i="5.85,356,1624345200"; d="scan'208";a="287301081" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 19:39:30 -0700 X-IronPort-AV: E=Sophos;i="5.85,356,1624345200"; d="scan'208";a="657644489" Received: from cchiu4-mobl.gar.corp.intel.com ([10.252.188.53]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2021 19:39:29 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Sai Chaganty , Nate DeSimone , Heng Luo Subject: [edk2-platforms: PATCH 6/9] TigerlakeOpenBoardPkg: Use same variable name for FspNvsHob. Date: Fri, 8 Oct 2021 10:38:59 +0800 Message-Id: <20211008023902.1066-7-chasel.chiu@intel.com> X-Mailer: git-send-email 2.28.0.windows.1 In-Reply-To: <20211008023902.1066-1-chasel.chiu@intel.com> References: <20211008023902.1066-1-chasel.chiu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3678 To simplify the implementation the variable Name/GUID has been changed to "FspNvsBuffer" and gFspNvsBufferVariableGuid regardless it stores the data from FSP_NON_VOLATILE_STORAGE_HOB2 or FSP_NON_VOLATILE_STORAGE_HOB. Cc: Sai Chaganty Cc: Nate DeSimone Cc: Heng Luo Signed-off-by: Chasel Chiu --- Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLi= b/PeiFspPolicyInitLib.c | 21 ++++++++++++++++++--- Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLi= b/PeiFspPolicyInitLib.inf | 1 + Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc = | 3 +++ 3 files changed, 22 insertions(+), 3 deletions(-) diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFsp= PolicyInitLib/PeiFspPolicyInitLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/= FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c index fc523e93d1..938b74e5d8 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspPolicyInitLib.c +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspPolicyInitLib.c @@ -9,7 +9,9 @@ #include =0D #include =0D #include =0D +#include =0D #include =0D +#include =0D =0D VOID=0D EFIAPI=0D @@ -70,9 +72,11 @@ SiliconPolicyDonePreMem( )=0D {=0D EFI_STATUS Status;=0D + UINTN FspNvsBufferSize;=0D + VOID *FspNvsBufferPtr;=0D #if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0=0D - FSPM_ARCH_CONFIG_PPI *FspmArchConfigPpi;=0D - EFI_PEI_PPI_DESCRIPTOR *FspmArchConfigPpiDesc;=0D + FSPM_ARCH_CONFIG_PPI *FspmArchConfigPpi;=0D + EFI_PEI_PPI_DESCRIPTOR *FspmArchConfigPpiDesc;=0D =0D FspmArchConfigPpi =3D (FSPM_ARCH_CONFIG_PPI *) AllocateZeroPool (sizeof = (FSPM_ARCH_CONFIG_PPI));=0D if (FspmArchConfigPpi =3D=3D NULL) {=0D @@ -80,7 +84,6 @@ SiliconPolicyDonePreMem( return EFI_OUT_OF_RESOURCES;=0D }=0D FspmArchConfigPpi->Revision =3D 1;=0D - FspmArchConfigPpi->NvsBufferPtr =3D NULL;=0D FspmArchConfigPpi->BootLoaderTolumSize =3D 0;=0D =0D FspmArchConfigPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (s= izeof (EFI_PEI_PPI_DESCRIPTOR));=0D @@ -98,6 +101,18 @@ SiliconPolicyDonePreMem( ASSERT_EFI_ERROR (Status);=0D #endif=0D =0D + //=0D + // Initialize S3 Data variable (S3DataPtr). It may be used for warm and = fast boot paths.=0D + //=0D + FspNvsBufferPtr =3D NULL;=0D + FspNvsBufferSize =3D 0;=0D + Status =3D PeiGetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVariableG= uid, &FspNvsBufferPtr, &FspNvsBufferSize);=0D + if (Status =3D=3D EFI_SUCCESS) {=0D + DEBUG ((DEBUG_INFO, "Get L\"FspNvsBuffer\" gFspNvsBufferVariableGuid -= %r\n", Status));=0D + DEBUG ((DEBUG_INFO, "FspNvsBuffer Size - 0x%x\n", FspNvsBufferSize));= =0D + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmArchUpd.NvsBufferPtr, FspmA= rchConfigPpi->NvsBufferPtr, FspNvsBufferPtr);=0D + }=0D +=0D //=0D // Install Policy Ready PPI=0D // While installed, RC assumes the Policy is ready and finalized. So ple= ase=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFsp= PolicyInitLib/PeiFspPolicyInitLib.inf b/Platform/Intel/TigerlakeOpenBoardPk= g/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf index 708fbac08f..0236ae45ae 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspPolicyInitLib.inf +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspPolicyInitLib.inf @@ -181,3 +181,4 @@ gTianoLogoGuid ## CONSUMES=0D gCnviConfigGuid ## CONSUMES=0D gHdAudioPreMemConfigGuid ## CONSUMES=0D + gFspNvsBufferVariableGuid ## CONSUMES=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPk= g.dsc b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc index 1adf634034..451492f984 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc @@ -142,6 +142,9 @@ GpioCheckConflictLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/Library/BaseGpi= oCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf=0D !endif=0D =0D +[LibraryClasses.Common.SEC]=0D + VariableReadLib|MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVaria= bleReadLibNull.inf=0D +=0D [LibraryClasses.IA32.SEC]=0D TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Sec= TestPointCheckLib.inf=0D TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull= /TestPointCheckLibNull.inf=0D --=20 2.28.0.windows.1