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From: "Khasim Mohammed" <khasim.mohammed@arm.com>
To: devel@edk2.groups.io
Cc: nd@arm.com, Khasim Syed Mohammed <khasim.mohammed@arm.com>,
	Sami Mujawar <sami.mujawar@arm.com>,
	Chandni Cherukuri <chandni.cherukuri@arm.com>,
	Manoj Kumar <manoj.kumar3@arm.com>,
	Patrik Berglund <patrik.berglund@arm.com>,
	anukou01 <anurag.koul@arm.com>,
	Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Subject: [PATCH v2 6/7] Platform/ARM/N1Sdp: Configuration Manager for N1Sdp
Date: Sun, 10 Oct 2021 23:59:55 +0530	[thread overview]
Message-ID: <20211010182956.13526-7-khasim.mohammed@arm.com> (raw)
In-Reply-To: <20211010182956.13526-1-khasim.mohammed@arm.com>

The dynamic tables framework utilizes the configuration manager
protocol to get the platform specific information required for
building the firmware tables.

The configuration manager is a platform specific component that
collates the platform hardware information and builds an abstract
platform configuration repository. The configuration manager also
implements the configuration manager protocol which returns the
hardware information requested by the table generators.

This patch implements the configuration manager for N1SDP
platform. It enables support for generating the following
ACPI tables:
             1. FACP
             2. DSDT
             3. GTDT
             4. APIC
             5. SPCR
             6. DBG2
             7. PPTT
             8. IORT
             9. MCFG
            10. SSDT - PCI
            11. SSDT - REMOTE PCI

Also added :
HMAT table and expose CCIX memory as EFI_MEMORY_SP

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Patrik Berglund <patrik.berglund@arm.com>
Signed-off-by: anukou01 <anurag.koul@arm.com>
Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
---
 .../ConfigurationManager.dsc.inc              |   16 +
 .../ConfigurationManager.c                    | 2199 +++++++++++++++++
 .../ConfigurationManager.h                    |  307 +++
 .../ConfigurationManagerDxe.inf               |  167 ++
 .../ConfigurationManagerDxe/Hmat.c            |  103 +
 .../ConfigurationManagerDxe/Platform.h        |   92 +
 6 files changed, 2884 insertions(+)
 create mode 100644 Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManager.dsc.inc
 create mode 100644 Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
 create mode 100644 Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
 create mode 100644 Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
 create mode 100644 Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Hmat.c
 create mode 100644 Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Platform.h

diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManager.dsc.inc b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManager.dsc.inc
new file mode 100644
index 0000000000..bcd4bf334d
--- /dev/null
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManager.dsc.inc
@@ -0,0 +1,16 @@
+## @file
+#  dsc include file for Configuration Manager
+#
+#  Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+
+[BuildOptions]
+
+[Components.common]
+  # Configuration Manager
+  Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
new file mode 100644
index 0000000000..8fc2a89674
--- /dev/null
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
@@ -0,0 +1,2199 @@
+/** @file
+  Configuration Manager Dxe
+
+  Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Glossary:
+    - Cm or CM   - Configuration Manager
+    - Obj or OBJ - Object
+**/
+
+#include <IndustryStandard/DebugPort2Table.h>
+#include <IndustryStandard/IoRemappingTable.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+#include <Library/ArmLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <NeoverseN1Soc.h>
+#include <Protocol/AcpiTable.h>
+#include <Protocol/ConfigurationManagerProtocol.h>
+
+#include "ConfigurationManager.h"
+#include "N1SdpAcpiHeader.h"
+#include "Platform.h"
+
+extern struct EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat;
+
+/** The platform configuration repository information.
+*/
+STATIC
+EDKII_PLATFORM_REPOSITORY_INFO N1sdpRepositoryInfo = {
+  // Configuration Manager information
+  { CONFIGURATION_MANAGER_REVISION, CFG_MGR_OEM_ID },
+
+  // ACPI Table List
+  {
+    // FADT Table
+    {
+      EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+      EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
+      CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdFadt),
+      NULL
+    },
+    // GTDT Table
+    {
+      EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+      EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION,
+      CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdGtdt),
+      NULL
+    },
+    // MADT Table
+    {
+      EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+      EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
+      CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMadt),
+      NULL
+    },
+    // SPCR Table
+    {
+      EFI_ACPI_6_3_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+      EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION,
+      CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSpcr),
+      NULL
+    },
+    // DSDT Table
+    {
+      EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+      0, // Unused
+      CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDsdt),
+      (EFI_ACPI_DESCRIPTION_HEADER*)dsdt_aml_code
+    },
+    // DBG2 Table
+    {
+      EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE,
+      EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
+      CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDbg2),
+      NULL
+    },
+    // PPTT Table
+    {
+      EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+      EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION,
+      CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdPptt),
+      NULL
+    },
+    // IORT Table
+    {
+      EFI_ACPI_6_3_IO_REMAPPING_TABLE_SIGNATURE,
+      EFI_ACPI_IO_REMAPPING_TABLE_REVISION,
+      CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdIort),
+      NULL
+    },
+    // PCI MCFG Table
+    {
+      EFI_ACPI_6_3_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+      EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION,
+      CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMcfg),
+      NULL,
+      SIGNATURE_64 ('A','R','M','N','1','S','D','P'),
+      0x20181101
+    },
+    // SSDT table describing the PCI root complex
+    {
+      EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+      0, // Unused
+      CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdt),
+      (EFI_ACPI_DESCRIPTION_HEADER*)ssdtpci_aml_code
+    },
+    // SRAT Table
+    {
+      EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
+      EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION,
+      CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSrat),
+      NULL
+    },
+    // HMAT Table
+    {
+      EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+      EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION,
+      CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdRaw),
+      (EFI_ACPI_DESCRIPTION_HEADER*)&Hmat
+    },
+    // SSDT table describing the Remote Chip PCI root complex
+    {
+      EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+      0, // Unused
+      CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdt),
+      (EFI_ACPI_DESCRIPTION_HEADER*)ssdtremotepci_aml_code
+    },
+  },
+
+  // Boot architecture information
+  { EFI_ACPI_6_3_ARM_PSCI_COMPLIANT },              // BootArchFlags
+
+  // Fixed feature flag information
+  { EFI_ACPI_6_3_HEADLESS },                        // Fixed feature flags
+
+  // Power management profile information
+  { EFI_ACPI_6_3_PM_PROFILE_ENTERPRISE_SERVER },    // PowerManagement Profile
+
+  /* GIC CPU Interface information
+     GICC_ENTRY (CPUInterfaceNumber, Mpidr, PmuIrq, VGicIrq, GicRedistBase,
+                EnergyEfficiency, SpeIrq, ProximityDomain, ClockDomain)
+  */
+  {
+    GICC_ENTRY (0, GET_MPID3 (0x0, 0x0, 0x0, 0x0), 23, 25, 0, 0, 21, 0, 0),
+    GICC_ENTRY (1, GET_MPID3 (0x0, 0x0, 0x1, 0x0), 23, 25, 0, 0, 21, 0, 0),
+    GICC_ENTRY (2, GET_MPID3 (0x0, 0x1, 0x0, 0x0), 23, 25, 0, 0, 21, 0, 0),
+    GICC_ENTRY (3, GET_MPID3 (0x0, 0x1, 0x1, 0x0), 23, 25, 0, 0, 21, 0, 0),
+    GICC_ENTRY (4, GET_MPID3 (0x1, 0x0, 0x0, 0x0), 23, 25, 0, 0, 21, 1, 0),
+    GICC_ENTRY (5, GET_MPID3 (0x1, 0x0, 0x1, 0x0), 23, 25, 0, 0, 21, 1, 0),
+    GICC_ENTRY (6, GET_MPID3 (0x1, 0x1, 0x0, 0x0), 23, 25, 0, 0, 21, 1, 0),
+    GICC_ENTRY (7, GET_MPID3 (0x1, 0x1, 0x1, 0x0), 23, 25, 0, 0, 21, 1, 0),
+  },
+
+  // GIC Distributor Info
+  {
+    FixedPcdGet64 (PcdGicDistributorBase),  // UINT64  PhysicalBaseAddress
+    0,                                      // UINT32  SystemVectorBase
+    3                                       // UINT8   GicVersion
+  },
+
+  // GIC Re-Distributor Info
+  {
+    {
+      // UINT64  DiscoveryRangeBaseAddress
+      FixedPcdGet64 (PcdGicRedistributorsBase),
+      // UINT32  DiscoveryRangeLength
+      SIZE_1MB
+    },
+    {
+      // UINT64  DiscoveryRangeBaseAddress
+      FixedPcdGet64 (PcdGicRedistributorsBase) + (1ULL << 42),
+      // UINT32  DiscoveryRangeLength
+      SIZE_1MB
+    },
+  },
+
+  // GIC ITS
+  {
+    // GIC ITS - CCIX TCU
+    {
+      // The GIC ITS ID.
+      0,
+      // The physical address for the Interrupt Translation Service
+      0x30040000,
+      //Proximity Domain
+      0
+    },
+    // GIC ITS - PCIe TCU
+    {
+      // The GIC ITS ID.
+      1,
+      // The physical address for the Interrupt Translation Service
+      0x30060000,
+      //Proximity Domain
+      0
+    },
+    // GIC ITS - CCIX RC
+    {
+      // The GIC ITS ID.
+      2,
+      // The physical address for the Interrupt Translation Service
+      0x30080000,
+      //Proximity Domain
+      0
+    },
+    // GIC ITS - PCIe RC
+    {
+      // The GIC ITS ID.
+      3,
+      // The physical address for the Interrupt Translation Service
+      0x300A0000,
+      //Proximity Domain
+      0
+    },
+    //Remote chip GIC ITS - PCIe TCU
+    {
+     ITS_REMOTE_SMMU_PCIE,
+     0x40030060000,
+     1
+    },
+    //Remote chip GIC ITS - PCIe RC
+    {
+     ITS_REMOTE_PCIE,
+     0x400300a0000,
+     1
+    },
+  },
+
+  // Generic Timer Info
+  {
+    // The physical base address for the counter control frame
+    N1SDP_SYSTEM_TIMER_BASE_ADDRESS,
+    // The physical base address for the counter read frame
+    N1SDP_CNT_READ_BASE_ADDRESS,
+    // The secure PL1 timer interrupt
+    FixedPcdGet32 (PcdArmArchTimerSecIntrNum),
+    // The secure PL1 timer flags
+    N1SDP_GTDT_GTIMER_FLAGS,
+    // The non-secure PL1 timer interrupt
+    FixedPcdGet32 (PcdArmArchTimerIntrNum),
+    // The non-secure PL1 timer flags
+    N1SDP_GTDT_GTIMER_FLAGS,
+    // The virtual timer interrupt
+    FixedPcdGet32 (PcdArmArchTimerVirtIntrNum),
+    // The virtual timer flags
+    N1SDP_GTDT_GTIMER_FLAGS,
+    // The non-secure PL2 timer interrupt
+    FixedPcdGet32 (PcdArmArchTimerHypIntrNum),
+    // The non-secure PL2 timer flags
+    N1SDP_GTDT_GTIMER_FLAGS
+  },
+
+  // Generic Timer Block Information
+  {
+    {
+      // The physical base address for the GT Block Timer structure
+      N1SDP_GT_BLOCK_CTL_BASE,
+      // The number of timer frames implemented in the GT Block
+      N1SDP_TIMER_FRAMES_COUNT,
+      // Reference token for the GT Block timer frame list
+      REFERENCE_TOKEN (GTBlock0TimerInfo)
+    }
+  },
+
+  // GT Block Timer Frames
+  {
+    // Frame 0
+    {
+      0,                                  // UINT8   FrameNumber
+      N1SDP_GT_BLOCK_FRAME0_CTL_BASE,     // UINT64  PhysicalAddressCntBase
+      N1SDP_GT_BLOCK_FRAME0_CTL_EL0_BASE, // UINT64  PhysicalAddressCntEL0Base
+      N1SDP_GT_BLOCK_FRAME0_GSIV,         // UINT32  PhysicalTimerGSIV
+      N1SDP_GTX_TIMER_FLAGS,              // UINT32  PhysicalTimerFlags
+      0,                                  // UINT32  VirtualTimerGSIV
+      0,                                  // UINT32  VirtualTimerFlags
+      N1SDP_GTX_COMMON_FLAGS_NS           // UINT32  CommonFlags
+    },
+    // Frame 1
+    {
+      1,                                  // UINT8   FrameNumber
+      N1SDP_GT_BLOCK_FRAME1_CTL_BASE,     // UINT64  PhysicalAddressCntBase
+      N1SDP_GT_BLOCK_FRAME1_CTL_EL0_BASE, // UINT64  PhysicalAddressCntEL0Base
+      N1SDP_GT_BLOCK_FRAME1_GSIV,         // UINT32  PhysicalTimerGSIV
+      N1SDP_GTX_TIMER_FLAGS,              // UINT32  PhysicalTimerFlags
+      0,                                  // UINT32  VirtualTimerGSIV
+      0,                                  // UINT32  VirtualTimerFlags
+      N1SDP_GTX_COMMON_FLAGS_S            // UINT32  CommonFlags
+    },
+  },
+
+  // Watchdog Info
+  {
+    // The physical base address of the SBSA Watchdog control frame
+    FixedPcdGet64 (PcdGenericWatchdogControlBase),
+    // The physical base address of the SBSA Watchdog refresh frame
+    FixedPcdGet64 (PcdGenericWatchdogRefreshBase),
+    // The watchdog interrupt
+    FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),
+    // The watchdog flags
+    N1SDP_SBSA_WATCHDOG_FLAGS
+  },
+
+  // SPCR Serial Port
+  {
+    FixedPcdGet64 (PcdSerialRegisterBase),                  // BaseAddress
+    FixedPcdGet32 (PL011UartInterrupt),                     // Interrupt
+    FixedPcdGet64 (PcdUartDefaultBaudRate),                 // BaudRate
+    FixedPcdGet32 (PL011UartClkInHz),                       // Clock
+    EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART        // Port subtype
+  },
+
+  // Debug Serial Port
+  {
+    FixedPcdGet64 (PcdSerialDbgRegisterBase),               // BaseAddress
+    0,                                                      // Interrupt -unused
+    FixedPcdGet64 (PcdSerialDbgUartBaudRate),               // BaudRate
+    FixedPcdGet32 (PcdSerialDbgUartClkInHz),                // Clock
+    EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART        // Port subtype
+  },
+
+  // Processor Hierarchy Nodes
+  {
+    // Package
+    {
+      // CM_OBJECT_TOKEN  Token
+      REFERENCE_TOKEN (ProcHierarchyInfo[0]),
+      // UINT32  Flags
+      PROC_NODE_FLAGS (
+        EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+        EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
+        EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+      ),
+      // CM_OBJECT_TOKEN  ParentToken
+      CM_NULL_TOKEN,
+      // CM_OBJECT_TOKEN  GicCToken
+      CM_NULL_TOKEN,
+      // UINT32  NoOfPrivateResources
+      SOC_RESOURCE_COUNT,
+      // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
+      REFERENCE_TOKEN (SocResources)
+    },
+    // Cluster0
+    {
+      // CM_OBJECT_TOKEN  Token
+      REFERENCE_TOKEN (ProcHierarchyInfo[1]),
+      // UINT32  Flags
+      PROC_NODE_FLAGS (
+        EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+        EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
+        EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+      ),
+      // CM_OBJECT_TOKEN  ParentToken
+      REFERENCE_TOKEN (ProcHierarchyInfo[0]), // -> Package
+      // CM_OBJECT_TOKEN  GicCToken
+      CM_NULL_TOKEN,
+      // UINT32  NoOfPrivateResources
+      CLUSTER_RESOURCE_COUNT,
+      // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
+      REFERENCE_TOKEN (ClusterResources)
+    },
+    // Cluster1
+    {
+      // CM_OBJECT_TOKEN  Token
+      REFERENCE_TOKEN (ProcHierarchyInfo[2]),
+      // UINT32  Flags
+      PROC_NODE_FLAGS (
+        EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+        EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
+        EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+      ),
+      // CM_OBJECT_TOKEN  ParentToken
+      REFERENCE_TOKEN (ProcHierarchyInfo[0]), // -> Package
+      // CM_OBJECT_TOKEN  GicCToken
+      CM_NULL_TOKEN,
+      // UINT32  NoOfPrivateResources
+      CLUSTER_RESOURCE_COUNT,
+      // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
+      REFERENCE_TOKEN (ClusterResources)
+    },
+    // Cluster0 - Cpu0
+    {
+      // CM_OBJECT_TOKEN  Token
+      REFERENCE_TOKEN (ProcHierarchyInfo[3]),
+      // UINT32  Flags
+      PROC_NODE_FLAGS (
+        EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+        EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+        EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL
+      ),
+      // CM_OBJECT_TOKEN  ParentToken
+      REFERENCE_TOKEN (ProcHierarchyInfo[1]), // -> 'cluster in Cluster0
+      // CM_OBJECT_TOKEN  GicCToken
+      REFERENCE_TOKEN (GicCInfo[0]),
+      // UINT32  NoOfPrivateResources
+      CORE_RESOURCE_COUNT,
+      // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
+      REFERENCE_TOKEN (CoreResources)
+    },
+    // Cluster0 - Cpu1
+    {
+      // CM_OBJECT_TOKEN  Token
+      REFERENCE_TOKEN (ProcHierarchyInfo[4]),
+      // UINT32  Flags
+      PROC_NODE_FLAGS (
+        EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+        EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+        EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL
+      ),
+      // CM_OBJECT_TOKEN  ParentToken
+      REFERENCE_TOKEN (ProcHierarchyInfo[1]), // -> 'cluster in Cluster0
+      // CM_OBJECT_TOKEN  GicCToken
+      REFERENCE_TOKEN (GicCInfo[1]),
+      // UINT32  NoOfPrivateResources
+      CORE_RESOURCE_COUNT,
+      // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
+      REFERENCE_TOKEN (CoreResources)
+    },
+    // Cluster1 - Cpu0
+    {
+      // CM_OBJECT_TOKEN  Token
+      REFERENCE_TOKEN (ProcHierarchyInfo[3]),
+      // UINT32  Flags
+      PROC_NODE_FLAGS (
+        EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+        EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+        EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL
+      ),
+      // CM_OBJECT_TOKEN  ParentToken
+      REFERENCE_TOKEN (ProcHierarchyInfo[2]), // -> 'cluster in Cluster1
+      // CM_OBJECT_TOKEN  GicCToken
+      REFERENCE_TOKEN (GicCInfo[2]),
+      // UINT32  NoOfPrivateResources
+      CORE_RESOURCE_COUNT,
+      // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
+      REFERENCE_TOKEN (CoreResources)
+    },
+    // Cluster1 - Cpu1
+    {
+      // CM_OBJECT_TOKEN  Token
+      REFERENCE_TOKEN (ProcHierarchyInfo[4]),
+      // UINT32  Flags
+      PROC_NODE_FLAGS (
+        EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+        EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+        EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL
+      ),
+      // CM_OBJECT_TOKEN  ParentToken
+      REFERENCE_TOKEN (ProcHierarchyInfo[2]), // -> 'cluster in Cluster1
+      // CM_OBJECT_TOKEN  GicCToken
+      REFERENCE_TOKEN (GicCInfo[3]),
+      // UINT32  NoOfPrivateResources
+      CORE_RESOURCE_COUNT,
+      // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
+      REFERENCE_TOKEN (CoreResources)
+    },
+    // Slave chip hierarchy
+    // Package
+    {
+      // CM_OBJECT_TOKEN  Token
+      REFERENCE_TOKEN (ProcHierarchyInfo[7]),
+      // UINT32  Flags
+      PROC_NODE_FLAGS (
+        EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+        EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
+        EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+      ),
+      // CM_OBJECT_TOKEN  ParentToken
+      CM_NULL_TOKEN,
+      // CM_OBJECT_TOKEN  GicCToken
+      CM_NULL_TOKEN,
+      // UINT32  NoOfPrivateResources
+      SOC_RESOURCE_COUNT,
+      // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
+      REFERENCE_TOKEN (SocResources)
+    },
+    // Cluster0
+    {
+      // CM_OBJECT_TOKEN  Token
+      REFERENCE_TOKEN (ProcHierarchyInfo[8]),
+      // UINT32  Flags
+      PROC_NODE_FLAGS (
+        EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+        EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
+        EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+      ),
+      // CM_OBJECT_TOKEN  ParentToken
+      REFERENCE_TOKEN (ProcHierarchyInfo[7]), // -> Package
+      // CM_OBJECT_TOKEN  GicCToken
+      CM_NULL_TOKEN,
+      // UINT32  NoOfPrivateResources
+      CLUSTER_RESOURCE_COUNT,
+      // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
+      REFERENCE_TOKEN (ClusterResources)
+    },
+    // Cluster1
+    {
+      // CM_OBJECT_TOKEN  Token
+      REFERENCE_TOKEN (ProcHierarchyInfo[9]),
+      // UINT32  Flags
+      PROC_NODE_FLAGS (
+        EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+        EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
+        EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+      ),
+      // CM_OBJECT_TOKEN  ParentToken
+      REFERENCE_TOKEN (ProcHierarchyInfo[7]), // -> Package
+      // CM_OBJECT_TOKEN  GicCToken
+      CM_NULL_TOKEN,
+      // UINT32  NoOfPrivateResources
+      CLUSTER_RESOURCE_COUNT,
+      // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
+      REFERENCE_TOKEN (ClusterResources)
+    },
+    // Cluster0 - Cpu0
+    {
+      // CM_OBJECT_TOKEN  Token
+      REFERENCE_TOKEN (ProcHierarchyInfo[10]),
+      // UINT32  Flags
+      PROC_NODE_FLAGS (
+        EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+        EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+        EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL
+      ),
+      // CM_OBJECT_TOKEN  ParentToken
+      REFERENCE_TOKEN (ProcHierarchyInfo[8]), // -> 'cluster in Cluster0
+      // CM_OBJECT_TOKEN  GicCToken
+      REFERENCE_TOKEN (GicCInfo[4]),
+      // UINT32  NoOfPrivateResources
+      CORE_RESOURCE_COUNT,
+      // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
+      REFERENCE_TOKEN (CoreResources)
+    },
+    // Cluster0 - Cpu1
+    {
+      // CM_OBJECT_TOKEN  Token
+      REFERENCE_TOKEN (ProcHierarchyInfo[11]),
+      // UINT32  Flags
+      PROC_NODE_FLAGS (
+        EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+        EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+        EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL
+      ),
+      // CM_OBJECT_TOKEN  ParentToken
+      REFERENCE_TOKEN (ProcHierarchyInfo[8]), // -> 'cluster in Cluster0
+      // CM_OBJECT_TOKEN  GicCToken
+      REFERENCE_TOKEN (GicCInfo[5]),
+      // UINT32  NoOfPrivateResources
+      CORE_RESOURCE_COUNT,
+      // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
+      REFERENCE_TOKEN (CoreResources)
+    },
+    // Cluster1 - Cpu0
+    {
+      // CM_OBJECT_TOKEN  Token
+      REFERENCE_TOKEN (ProcHierarchyInfo[10]),
+      // UINT32  Flags
+      PROC_NODE_FLAGS (
+        EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+        EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+        EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL
+      ),
+      // CM_OBJECT_TOKEN  ParentToken
+      REFERENCE_TOKEN (ProcHierarchyInfo[9]), // -> 'cluster in Cluster1
+      // CM_OBJECT_TOKEN  GicCToken
+      REFERENCE_TOKEN (GicCInfo[6]),
+      // UINT32  NoOfPrivateResources
+      CORE_RESOURCE_COUNT,
+      // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
+      REFERENCE_TOKEN (CoreResources)
+    },
+    // Cluster1 - Cpu1
+    {
+      // CM_OBJECT_TOKEN  Token
+      REFERENCE_TOKEN (ProcHierarchyInfo[11]),
+      // UINT32  Flags
+      PROC_NODE_FLAGS (
+        EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+        EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+        EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+        EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL
+      ),
+      // CM_OBJECT_TOKEN  ParentToken
+      REFERENCE_TOKEN (ProcHierarchyInfo[9]), // -> 'cluster in Cluster1
+      // CM_OBJECT_TOKEN  GicCToken
+      REFERENCE_TOKEN (GicCInfo[7]),
+      // UINT32  NoOfPrivateResources
+      CORE_RESOURCE_COUNT,
+      // CM_OBJECT_TOKEN  PrivateResourcesArrayToken
+      REFERENCE_TOKEN (CoreResources)
+    },
+  },
+
+  // Cache information
+  {
+    // 'cluster's L3 cache
+    {
+      REFERENCE_TOKEN (CacheInfo[0]),  // CM_OBJECT_TOKEN  Token
+      CM_NULL_TOKEN,                   // CM_OBJECT_TOKEN  NextLevelOfCacheToken
+      SIZE_1MB,                        // UINT32  Size
+      2048,                            // UINT32  NumberOfSets
+      8,                               // UINT32  Associativity
+      CACHE_ATTRIBUTES (               // UINT8   Attributes
+        EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ,
+        EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED,
+        EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK
+      ),
+      64                               // UINT16  LineSize
+    },
+    // 'core's L1 instruction cache
+    {
+      REFERENCE_TOKEN (CacheInfo[1]),  // CM_OBJECT_TOKEN  Token
+      REFERENCE_TOKEN (CacheInfo[3]),  // CM_OBJECT_TOKEN  NextLevelOfCacheToken
+      SIZE_64KB,                       // UINT32  Size
+      256,                             // UINT32  NumberOfSets
+      4,                               // UINT32  Associativity
+      CACHE_ATTRIBUTES (               // UINT8   Attributes
+        EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ,
+        EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION,
+        EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK
+      ),
+      64                               // UINT16  LineSize
+    },
+    // 'core's L1 data cache
+    {
+      REFERENCE_TOKEN (CacheInfo[2]),  // CM_OBJECT_TOKEN  Token
+      REFERENCE_TOKEN (CacheInfo[3]),  // CM_OBJECT_TOKEN  NextLevelOfCacheToken
+      SIZE_64KB,                       // UINT32  Size
+      256,                             // UINT32  NumberOfSets
+      4,                               // UINT32  Associativity
+      CACHE_ATTRIBUTES (               // UINT8   Attributes
+        EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE,
+        EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA,
+        EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK
+      ),
+      64                               // UINT16  LineSize
+    },
+    // cores's L2 cache
+    {
+      REFERENCE_TOKEN (CacheInfo[3]),  // CM_OBJECT_TOKEN  Token
+      CM_NULL_TOKEN,                   // CM_OBJECT_TOKEN  NextLevelOfCacheToken
+      SIZE_1MB,                        // UINT32  Size
+      2048,                            // UINT32  NumberOfSets
+      8,                               // UINT32  Associativity
+      CACHE_ATTRIBUTES (               // UINT8   Attributes
+        EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ,
+        EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED,
+        EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK
+      ),
+      64                               // UINT16  LineSize
+    },
+    // slc cache
+    {
+      REFERENCE_TOKEN (CacheInfo[4]),  // CM_OBJECT_TOKEN  Token
+      CM_NULL_TOKEN,                   // CM_OBJECT_TOKEN  NextLevelOfCacheToken
+      SIZE_8MB,                        // UINT32  Size
+      8192,                            // UINT32  NumberOfSets
+      16,                              // UINT32  Associativity
+      CACHE_ATTRIBUTES (               // UINT8   Attributes
+        EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ,
+        EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED,
+        EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK
+      ),
+      64                               // UINT16  LineSize
+    },
+  },
+
+  // Resources private to the 'cluster (shared among cores) in Cluster
+  {
+    { REFERENCE_TOKEN (CacheInfo[0]) }  // -> 'cluster's L3 cache in Cluster
+  },
+
+  // Resources private to each individual 'core instance in Cluster
+  {
+    { REFERENCE_TOKEN (CacheInfo[1]) }, // -> 'core's L1 I-cache in Cluster
+    { REFERENCE_TOKEN (CacheInfo[2]) }  // -> 'core's L1 D-cache in Cluster
+  },
+
+  // Resources private to the SoC
+  {
+    { REFERENCE_TOKEN (CacheInfo[4])   },  // -> slc for SoC
+  },
+
+  // ITS group node
+  {
+    {
+      // Reference token for this Iort node
+      REFERENCE_TOKEN (ItsGroupInfo[ITS_SMMU_CCIX]),
+      // The number of ITS identifiers in the ITS node.
+      1,
+      // Reference token for the ITS identifier array
+      REFERENCE_TOKEN (ItsIdentifierArray[ITS_SMMU_CCIX])
+    },
+    {
+      // Reference token for this Iort node
+      REFERENCE_TOKEN (ItsGroupInfo[ITS_SMMU_PCIE]),
+      // The number of ITS identifiers in the ITS node.
+      1,
+      // Reference token for the ITS identifier array
+      REFERENCE_TOKEN (ItsIdentifierArray[ITS_SMMU_PCIE])
+    },
+    {
+      // Reference token for this Iort node
+      REFERENCE_TOKEN (ItsGroupInfo[ITS_CCIX]),
+      // The number of ITS identifiers in the ITS node.
+      1,
+      // Reference token for the ITS identifier array
+      REFERENCE_TOKEN (ItsIdentifierArray[ITS_CCIX])
+    },
+    {
+      // Reference token for this Iort node
+      REFERENCE_TOKEN (ItsGroupInfo[ITS_PCIE]),
+      // The number of ITS identifiers in the ITS node.
+      1,
+      // Reference token for the ITS identifier array
+      REFERENCE_TOKEN (ItsIdentifierArray[ITS_PCIE])
+    },
+    //Remote Chip ITS
+    {
+      REFERENCE_TOKEN (ItsGroupInfo[ITS_REMOTE_SMMU_PCIE]),
+      1,
+      REFERENCE_TOKEN (ItsIdentifierArray[ITS_REMOTE_SMMU_PCIE])
+    },
+    {
+      REFERENCE_TOKEN (ItsGroupInfo[ITS_REMOTE_PCIE]),
+      1,
+      REFERENCE_TOKEN (ItsIdentifierArray[ITS_REMOTE_PCIE])
+    },
+  },
+
+  // ITS identifier array
+  {
+    {
+      // The ITS Identifier - 0
+      ITS_SMMU_CCIX
+    },
+    {
+      // The ITS Identifier - 1
+      ITS_SMMU_PCIE
+    },
+    {
+      // The ITS Identifier - 2
+      ITS_CCIX
+    },
+    {
+      // The ITS Identifier - 3
+      ITS_PCIE
+    },
+    {
+      // The ITS Identifier - 4
+      ITS_REMOTE_SMMU_PCIE
+    },
+    {
+      // The ITS Identifier - 5
+      ITS_REMOTE_PCIE
+    }
+  },
+
+  {
+    // SMMUv3 Node
+    {
+      // Reference token for this Iort node
+      REFERENCE_TOKEN (SmmuV3Info[SMMUV3INFO_PCIE]),
+      // Number of ID mappings
+      2,
+      // Reference token for the ID mapping array
+      REFERENCE_TOKEN (DeviceIdMapping[DEVICEIDMAPPING_SMMU_PCIE][0]),
+      // SMMU Base Address
+      0x4F400000,
+      // SMMU flags
+      EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE,
+      // VATOS address
+      0,
+      // Model
+      EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC,
+      // GSIV of the Event interrupt if SPI based
+      0x10B,
+      // PRI Interrupt if SPI based
+      0,
+      // GERR interrupt if GSIV based
+      0x10D,
+      // Sync interrupt if GSIV based
+      0x10C,
+      // Proximity domain flag, ignored in this case
+      0,
+      // Index into the array of ID mapping
+      1
+    },
+    // SMMUv3 Node
+    {
+      // Reference token for this Iort node
+      REFERENCE_TOKEN (SmmuV3Info[SMMUV3INFO_CCIX]),
+      // Number of ID mappings
+      2,
+      // Reference token for the ID mapping array
+      REFERENCE_TOKEN (DeviceIdMapping[DEVICEIDMAPPING_SMMU_CCIX][0]),
+      // SMMU Base Address
+      0x4F000000,
+      // SMMU flags
+      EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE,
+      // VATOS address
+      0,
+      // Model
+      EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC,
+      // GSIV of the Event interrupt if SPI based
+      0x104,
+      // PRI Interrupt if SPI based
+      0,
+      // GERR interrupt if GSIV based
+      0x106,
+      // Sync interrupt if GSIV based
+      0x105,
+      // Proximity domain flag, ignored in this case
+      0,
+      // Index into the array of ID mapping
+      1
+    },
+    //Remote Chip SMMU V3 setting
+    {
+      REFERENCE_TOKEN (SmmuV3Info[SMMUV3INFO_REMOTE_PCIE]),
+      2,
+      REFERENCE_TOKEN (DeviceIdMapping[DEVICEIDMAPPING_REMOTE_SMMU_PCIE][0]),
+      0x4004f400000,
+      EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE,
+      0,
+      EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC,
+      747,
+      0,
+      749,
+      748,
+      0,
+      1
+    }
+  },
+
+  {
+    // Root Complex node info
+    {
+      // Reference token for this Iort node
+      REFERENCE_TOKEN (RootComplexInfo[0]),
+      // Number of ID mappings
+      1,
+      // Reference token for the ID mapping array
+      REFERENCE_TOKEN (DeviceIdMapping[DEVICEIDMAPPING_PCIE][0]),
+      // Memory access properties : Cache coherent attributes
+      EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA,
+      // Memory access properties : Allocation hints
+      0,
+      // Memory access properties : Memory access flags
+      0,
+      // ATS attributes
+      EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED,
+      // PCI segment number
+      0,
+      // Memory address size limit
+      42
+    },
+      // Root Complex node info
+    {
+      // Reference token for this Iort node
+      REFERENCE_TOKEN (RootComplexInfo[1]),
+      // Number of ID mappings
+      1,
+      // Reference token for the ID mapping array
+      REFERENCE_TOKEN (DeviceIdMapping[DEVICEIDMAPPING_PCIE][1]),
+      // Memory access properties : Cache coherent attributes
+      EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA,
+      // Memory access properties : Allocation hints
+      0,
+      // Memory access properties : Memory access flags
+      0,
+      // ATS attributes
+      EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED,
+      // PCI segment number
+      1,
+      // Memory address size limit
+      42
+    },
+     //Remote Chip Root Complex node Info
+    {
+      REFERENCE_TOKEN (RootComplexInfo[ROOT_REMOTE_PCIE]),
+      1,
+      REFERENCE_TOKEN (DeviceIdMapping[DEVICEIDMAPPING_REMOTE_PCIE][0]),
+      EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA,
+      0,
+      0,
+      EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED,
+      2,
+      42
+    }
+  },
+
+  // Array of Device ID mappings
+  {
+    // DeviceIdMapping[0][0] - [0][1]
+    {
+      // Mapping SMMUv3 -> ITS Group
+      // SMMUv3 device ID mapping
+      {
+        // Input base
+        0x0,
+        // Number of input IDs
+        0x0000FFFF,
+        // Output Base
+        0x0,
+        // Output reference
+        REFERENCE_TOKEN (ItsGroupInfo[ITS_PCIE]),
+        // Flags
+        0
+      },
+      // SMMUv3 device ID mapping
+      {
+        // Input base
+        0x0,
+        // Number of input IDs
+        0x00000001,
+        // Output Base
+        0x0,
+        // Output reference token for the IORT node
+        REFERENCE_TOKEN (ItsGroupInfo[ITS_SMMU_PCIE]),
+        // Flags
+        EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE
+      }
+    },
+    // DeviceIdMapping[1][0] - [1][1]
+    {
+      // Mapping SMMUv3 -> ITS Group
+      // SMMUv3 device ID mapping
+      {
+        // Input base
+        0x0,
+        // Number of input IDs
+        0x0000FFFF,
+        // Output Base
+        0x0,
+        // Output reference
+        REFERENCE_TOKEN (ItsGroupInfo[ITS_CCIX]),
+        // Flags
+        0
+      },
+      // SMMUv3 device ID mapping
+      {
+        // Input base
+        0x0,
+        // Number of input IDs
+        0x00000001,
+        // Output Base
+        0x0,
+        // Output reference token for the IORT node
+        REFERENCE_TOKEN (ItsGroupInfo[ITS_SMMU_CCIX]),
+        // Flags
+        EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE
+      }
+    },
+    // DeviceIdMapping[2][0] - [2][1]
+    {
+      // Mapping for  RootComplex -> SMMUv3
+      // Device ID mapping for Root complex node
+      {
+        // Input base
+        0x0,
+        // Number of input IDs
+        0x0000FFFF,
+        // Output Base
+        0x0,
+        // Output reference
+        REFERENCE_TOKEN (SmmuV3Info[SMMUV3INFO_PCIE]),
+        // Flags
+        0
+      },
+      // Device ID mapping for Root complex node
+      {
+        // Input base
+        0x0,
+        // Number of input IDs
+        0x0000FFFF,
+        // Output Base
+        0x0,
+        // Output reference token for the IORT node
+        REFERENCE_TOKEN (SmmuV3Info[SMMUV3INFO_CCIX]),
+        // Flags
+        0
+      }
+    },
+      // Mapping of Remote Chip SMMUv3 -> ITS Group
+    {
+      {
+        0x0,
+        0x0000ffff,
+        0x0,
+        REFERENCE_TOKEN (ItsGroupInfo[ITS_REMOTE_PCIE]),
+        0
+      },
+      {
+        0x0,
+        0x00000001,
+        0x0,
+        REFERENCE_TOKEN (ItsGroupInfo[ITS_REMOTE_SMMU_PCIE]),
+        EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE
+      }
+    },
+      // Mapping for  Remote Chip RootComplex -> SMMUv3
+    {
+      {
+        0x0,
+        0x0000ffff,
+        0x0,
+        REFERENCE_TOKEN (SmmuV3Info[SMMUV3INFO_REMOTE_PCIE]),
+        0
+      }
+    },
+  },
+
+  // PCI Configuration Space Info
+  {
+    // PCIe ECAM
+    {
+      0x70000000,      // Base Address
+      0x0,             // Segment Group Number
+      0x0,             // Start Bus Number
+      17               // End Bus Number
+    },
+    // CCIX ECAM
+    {
+      0x68000000,      // Base Address
+      0x1,             // Segment Group Number
+      0x0,               // Start Bus Number
+      17               // End Bus Number
+    },
+    //Remote Chip PCIe ECAM
+    {
+      0x40070000000,   // Base Address
+      0x2,             // Segment Group Number
+      0x0,             // Start Bus Number
+      17               // End Bus Number
+    }
+  },
+
+  // Memory Affinity Info
+  {
+    {
+      // Proximity domain to which memory range belongs
+      0,
+      //Base Address
+      0x80000000,
+      //Length
+      0x80000000,
+      //Flags
+      EFI_ACPI_6_3_MEMORY_ENABLED
+    },
+    {
+      // Proximity domain to which memory range belongs
+      0,
+      //Base Address
+      0x8080000000,
+      //Length is updated dynamically from SRAM
+      0,
+      //Flags
+      EFI_ACPI_6_3_MEMORY_ENABLED
+    }
+  }
+
+};
+
+/** A helper function for returning the Configuration Manager Objects.
+  @param [in]       CmObjectId     The Configuration Manager Object ID.
+  @param [in]       Object         Pointer to the Object(s).
+  @param [in]       ObjectSize     Total size of the Object(s).
+  @param [in]       ObjectCount    Number of Objects.
+  @param [in, out]  CmObjectDesc   Pointer to the Configuration Manager Object
+                                   descriptor describing the requested Object.
+  @retval EFI_SUCCESS              Success.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+HandleCmObject (
+  IN  CONST CM_OBJECT_ID                CmObjectId,
+  IN        VOID                *       Object,
+  IN  CONST UINTN                       ObjectSize,
+  IN  CONST UINTN                       ObjectCount,
+  IN  OUT   CM_OBJ_DESCRIPTOR   * CONST CmObjectDesc
+  )
+{
+  CmObjectDesc->ObjectId = CmObjectId;
+  CmObjectDesc->Size = ObjectSize;
+  CmObjectDesc->Data = (VOID*)Object;
+  CmObjectDesc->Count = ObjectCount;
+  DEBUG ((
+    DEBUG_INFO,
+    "INFO: CmObjectId = %x, Ptr = 0x%p, Size = %d, Count = %d\n",
+    CmObjectId,
+    CmObjectDesc->Data,
+    CmObjectDesc->Size,
+    CmObjectDesc->Count
+    ));
+  return EFI_SUCCESS;
+}
+
+/** A helper function for returning the Configuration Manager Objects that
+    match the token.
+  @param [in]  This               Pointer to the Configuration Manager Protocol.
+  @param [in]  CmObjectId         The Configuration Manager Object ID.
+  @param [in]  Object             Pointer to the Object(s).
+  @param [in]  ObjectSize         Total size of the Object(s).
+  @param [in]  ObjectCount        Number of Objects.
+  @param [in]  Token              A token identifying the object.
+  @param [in]  HandlerProc        A handler function to search the object
+                                  referenced by the token.
+  @param [in, out]  CmObjectDesc  Pointer to the Configuration Manager Object
+                                  descriptor describing the requested Object.
+  @retval EFI_SUCCESS           Success.
+  @retval EFI_INVALID_PARAMETER A parameter is invalid.
+  @retval EFI_NOT_FOUND         The required object information is not found.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+HandleCmObjectRefByToken (
+  IN  CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL  * CONST This,
+  IN  CONST CM_OBJECT_ID                                  CmObjectId,
+  IN        VOID                                  *       Object,
+  IN  CONST UINTN                                         ObjectSize,
+  IN  CONST UINTN                                         ObjectCount,
+  IN  CONST CM_OBJECT_TOKEN                               Token,
+  IN  CONST CM_OBJECT_HANDLER_PROC                        HandlerProc,
+  IN  OUT   CM_OBJ_DESCRIPTOR                     * CONST CmObjectDesc
+  )
+{
+  EFI_STATUS  Status;
+  CmObjectDesc->ObjectId = CmObjectId;
+  if (Token == CM_NULL_TOKEN) {
+    CmObjectDesc->Size = ObjectSize;
+    CmObjectDesc->Data = (VOID*)Object;
+    CmObjectDesc->Count = ObjectCount;
+    Status = EFI_SUCCESS;
+  } else {
+    Status = HandlerProc (This, CmObjectId, Token, CmObjectDesc);
+  }
+
+  DEBUG ((
+    DEBUG_INFO,
+    "INFO: Token = 0x%p, CmObjectId = %x, Ptr = 0x%p, Size = %d, Count = %d\n",
+    (VOID*)Token,
+    CmObjectId,
+    CmObjectDesc->Data,
+    CmObjectDesc->Size,
+    CmObjectDesc->Count
+    ));
+  return Status;
+}
+
+/** A helper function for returning Configuration Manager Object(s) referenced
+    by token when the entire platform repository is in scope and the
+    CM_NULL_TOKEN value is not allowed.
+  @param [in]  This               Pointer to the Configuration Manager Protocol.
+  @param [in]  CmObjectId         The Configuration Manager Object ID.
+  @param [in]  Token              A token identifying the object.
+  @param [in]  HandlerProc        A handler function to search the object(s)
+                                  referenced by the token.
+  @param [in, out]  CmObjectDesc  Pointer to the Configuration Manager Object
+                                  descriptor describing the requested Object.
+  @retval EFI_SUCCESS           Success.
+  @retval EFI_INVALID_PARAMETER A parameter is invalid.
+  @retval EFI_NOT_FOUND         The required object information is not found.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+HandleCmObjectSearchPlatformRepo (
+  IN  CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL  * CONST This,
+  IN  CONST CM_OBJECT_ID                                  CmObjectId,
+  IN  CONST CM_OBJECT_TOKEN                               Token,
+  IN  CONST CM_OBJECT_HANDLER_PROC                        HandlerProc,
+  IN  OUT   CM_OBJ_DESCRIPTOR                     * CONST CmObjectDesc
+  )
+{
+  EFI_STATUS  Status;
+  CmObjectDesc->ObjectId = CmObjectId;
+  if (Token == CM_NULL_TOKEN) {
+    DEBUG ((
+      DEBUG_ERROR,
+      "ERROR: CM_NULL_TOKEN value is not allowed when searching"
+      " the entire platform repository.\n"
+      ));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Status = HandlerProc (This, CmObjectId, Token, CmObjectDesc);
+  DEBUG ((
+    DEBUG_INFO,
+    "INFO: Token = 0x%p, CmObjectId = %x, Ptr = 0x%p, Size = %d, Count = %d\n",
+    CmObjectId,
+    (VOID*)Token,
+    CmObjectDesc->Data,
+    CmObjectDesc->Size,
+    CmObjectDesc->Count
+    ));
+  return Status;
+}
+
+/** Initialize the Platform Configuration Repository.
+  @param [in]       PlatformRepo   Pointer to the Configuration Manager Protocol.
+  @retval EFI_SUCCESS           Success
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+InitializePlatformRepository (
+  IN  EDKII_PLATFORM_REPOSITORY_INFO  * CONST PlatRepoInfo
+  )
+{
+  NEOVERSEN1SOC_PLAT_INFO       *PlatInfo;
+  UINT64                        Dram2Size;
+  UINT64                        RemoteDdrSize;
+
+  RemoteDdrSize = 0;
+
+  PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
+  Dram2Size = ((PlatInfo->LocalDdrSize - 2) * SIZE_1GB);
+
+  PlatRepoInfo->MemAffInfo[LOCAL_DDR_REGION2].Length = Dram2Size;
+
+  if (PlatInfo->MultichipMode == 1) {
+    RemoteDdrSize = ((PlatInfo->RemoteDdrSize - 2) * SIZE_1GB);
+
+    // Update Remote DDR Region1
+    PlatRepoInfo->MemAffInfo[REMOTE_DDR_REGION1].ProximityDomain = 1;
+    PlatRepoInfo->MemAffInfo[REMOTE_DDR_REGION1]. \
+      BaseAddress = FixedPcdGet64 (PcdExtMemorySpace)
+                    + FixedPcdGet64 (PcdSystemMemoryBase);
+    PlatRepoInfo->MemAffInfo[REMOTE_DDR_REGION1]. \
+      Length = FixedPcdGet64 (PcdSystemMemorySize);
+    PlatRepoInfo->MemAffInfo[REMOTE_DDR_REGION1]. \
+      Flags = EFI_ACPI_6_3_MEMORY_ENABLED;
+
+    // Update Remote DDR Region2
+    PlatRepoInfo->MemAffInfo[REMOTE_DDR_REGION2]. \
+      ProximityDomain = 1;
+    PlatRepoInfo->MemAffInfo[REMOTE_DDR_REGION2]. \
+      BaseAddress = FixedPcdGet64 (PcdExtMemorySpace)
+                    + FixedPcdGet64 (PcdDramBlock2Base);
+    PlatRepoInfo->MemAffInfo[REMOTE_DDR_REGION2]. \
+      Length = RemoteDdrSize;
+    PlatRepoInfo->MemAffInfo[REMOTE_DDR_REGION2]. \
+      Flags = EFI_ACPI_6_3_MEMORY_ENABLED;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/** Return a GT Block timer frame info list.
+
+  @param [in]        This        Pointer to the Configuration Manager Protocol.
+  @param [in]        CmObjectId  The Configuration Manager Object ID.
+  @param [in]        Token       A token for identifying the object
+  @param [in, out]   CmObject    Pointer to the Configuration Manager Object
+                                 descriptor describing the requested Object.
+
+  @retval EFI_SUCCESS            Success.
+  @retval EFI_INVALID_PARAMETER  A parameter is invalid.
+  @retval EFI_NOT_FOUND          The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetGTBlockTimerFrameInfo (
+  IN  CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL  * CONST This,
+  IN  CONST CM_OBJECT_ID                                  CmObjectId,
+  IN  CONST CM_OBJECT_TOKEN                               Token,
+  IN  OUT   CM_OBJ_DESCRIPTOR                     * CONST CmObject
+  )
+{
+  EDKII_PLATFORM_REPOSITORY_INFO  * PlatformRepo;
+
+  if ((This == NULL) || (CmObject == NULL)) {
+    ASSERT (This != NULL);
+    ASSERT (CmObject != NULL);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  PlatformRepo = This->PlatRepoInfo;
+
+  if (Token != (CM_OBJECT_TOKEN)&PlatformRepo->GTBlock0TimerInfo) {
+    return EFI_NOT_FOUND;
+  }
+
+  CmObject->ObjectId = CmObjectId;
+  CmObject->Size = sizeof (PlatformRepo->GTBlock0TimerInfo);
+  CmObject->Data = (VOID*)&PlatformRepo->GTBlock0TimerInfo;
+  CmObject->Count = ARRAY_SIZE (PlatformRepo->GTBlock0TimerInfo);
+  return EFI_SUCCESS;
+}
+
+/** Return an ITS identifier array.
+
+  @param [in]        This        Pointer to the Configuration Manager Protocol.
+  @param [in]        CmObjectId  The Configuration Manager Object ID.
+  @param [in]        Token       A token for identifying the object
+  @param [in, out]   CmObject    Pointer to the Configuration Manager Object
+                                 descriptor describing the requested Object.
+
+  @retval EFI_SUCCESS            Success.
+  @retval EFI_INVALID_PARAMETER  A parameter is invalid.
+  @retval EFI_NOT_FOUND          The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetItsIdentifierArray (
+  IN  CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL  * CONST This,
+  IN  CONST CM_OBJECT_ID                                  CmObjectId,
+  IN  CONST CM_OBJECT_TOKEN                               Token,
+  IN  OUT   CM_OBJ_DESCRIPTOR                     * CONST CmObject
+  )
+{
+  EDKII_PLATFORM_REPOSITORY_INFO  * PlatformRepo;
+  UINTN                             Count;
+  UINTN                             Index;
+
+  if ((This == NULL) || (CmObject == NULL)) {
+    ASSERT (This != NULL);
+    ASSERT (CmObject != NULL);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  PlatformRepo = This->PlatRepoInfo;
+
+  Count = ARRAY_SIZE (PlatformRepo->ItsIdentifierArray);
+
+  for (Index = 0; Index < Count; Index++) {
+    if (Token == (CM_OBJECT_TOKEN)&PlatformRepo->ItsIdentifierArray[Index]) {
+      CmObject->ObjectId = CmObjectId;
+      CmObject->Size = sizeof (PlatformRepo->ItsIdentifierArray[0]);
+      CmObject->Data = (VOID*)&PlatformRepo->ItsIdentifierArray[Index];
+      CmObject->Count = 1;
+      return EFI_SUCCESS;
+    }
+  }
+
+  return EFI_NOT_FOUND;
+}
+
+/** Return an ITS group info.
+
+  @param [in]        This        Pointer to the Configuration Manager Protocol.
+  @param [in]        CmObjectId  The Configuration Manager Object ID.
+  @param [in]        Token       A token for identifying the object
+  @param [in, out]   CmObject    Pointer to the Configuration Manager Object
+                                 descriptor describing the requested Object.
+
+  @retval EFI_SUCCESS            Success.
+  @retval EFI_INVALID_PARAMETER  A parameter is invalid.
+  @retval EFI_NOT_FOUND          The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetItsGroupInfo (
+  IN  CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL  * CONST This,
+  IN  CONST CM_OBJECT_ID                                  CmObjectId,
+  IN  CONST CM_OBJECT_TOKEN                               Token,
+  IN  OUT   CM_OBJ_DESCRIPTOR                     * CONST CmObject
+  )
+{
+  EDKII_PLATFORM_REPOSITORY_INFO  * PlatformRepo;
+  UINTN                             Count;
+  UINTN                             Index;
+
+  if ((This == NULL) || (CmObject == NULL)) {
+    ASSERT (This != NULL);
+    ASSERT (CmObject != NULL);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  PlatformRepo = This->PlatRepoInfo;
+
+  Count = ARRAY_SIZE (PlatformRepo->ItsGroupInfo);
+
+  for (Index = 0; Index < Count; Index++) {
+    if (Token == (CM_OBJECT_TOKEN)&PlatformRepo->ItsGroupInfo[Index]) {
+      CmObject->ObjectId = CmObjectId;
+      CmObject->Size = sizeof (PlatformRepo->ItsGroupInfo[0]);
+      CmObject->Data = (VOID*)&PlatformRepo->ItsGroupInfo[Index];
+      CmObject->Count = 1;
+      return EFI_SUCCESS;
+    }
+  }
+
+  return EFI_NOT_FOUND;
+}
+
+/** Return a device Id mapping array.
+
+  @param [in]        This        Pointer to the Configuration Manager Protocol.
+  @param [in]        CmObjectId  The Configuration Manager Object ID.
+  @param [in]        Token       A token for identifying the object
+  @param [in, out]   CmObject    Pointer to the Configuration Manager Object
+                                 descriptor describing the requested Object.
+
+  @retval EFI_SUCCESS            Success.
+  @retval EFI_INVALID_PARAMETER  A parameter is invalid.
+  @retval EFI_NOT_FOUND          The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetDeviceIdMappingArray (
+  IN  CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL  * CONST This,
+  IN  CONST CM_OBJECT_ID                                  CmObjectId,
+  IN  CONST CM_OBJECT_TOKEN                               Token,
+  IN  OUT   CM_OBJ_DESCRIPTOR                     * CONST CmObject
+  )
+{
+  EDKII_PLATFORM_REPOSITORY_INFO  * PlatformRepo;
+  UINTN                             Count;
+
+  if ((This == NULL) || (CmObject == NULL)) {
+    ASSERT (This != NULL);
+    ASSERT (CmObject != NULL);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  PlatformRepo = This->PlatRepoInfo;
+
+  DEBUG ((DEBUG_INFO, "DeviceIdMapping - Token = %p\n"));
+
+  if (Token == (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[0][0]) {
+    Count = 2;
+    DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[0][0]\n"));
+  } else if (Token ==
+             (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[1][0]) {
+    Count = 2;
+    DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[1][0]\n"));
+  } else if (Token ==
+             (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[2][0]) {
+    Count  = 1;
+    DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[2][0]\n"));
+  } else if (Token ==
+             (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[2][1]) {
+    Count  = 1;
+    DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[2][1]\n"));
+  } else if (Token ==
+             (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[DEVICEIDMAPPING_REMOTE_SMMU_PCIE][0]) {
+    Count = 2;
+    DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[DEVICEIDMAPPING_REMOTE_SMMU_PCIE][0]\n"));
+  } else if (Token ==
+             (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[DEVICEIDMAPPING_REMOTE_PCIE][0]) {
+    Count  = 1;
+    DEBUG ((DEBUG_INFO, "DeviceIdMapping - Found DeviceIdMapping[DEVICEIDMAPPING_REMOTE_PCIE][0]\n"));
+  } else {
+    DEBUG ((DEBUG_INFO, "DeviceIdMapping - Not Found\n"));
+    return EFI_NOT_FOUND;
+  }
+
+  CmObject->Data = (VOID*)Token;
+  CmObject->ObjectId = CmObjectId;
+  CmObject->Count = Count;
+  CmObject->Size = Count * sizeof (CM_ARM_ID_MAPPING);
+
+  return EFI_SUCCESS;
+}
+
+/** Return GIC CPU Interface Info.
+
+  @param [in]        This        Pointer to the Configuration Manager Protocol.
+  @param [in]        CmObjectId  The Object ID of the CM object requested
+  @param [in]        SearchToken A unique token for identifying the requested
+                                 CM_ARM_GICC_INFO object.
+  @param [in, out]   CmObject    Pointer to the Configuration Manager Object
+                                 descriptor describing the requested Object.
+
+  @retval EFI_SUCCESS            Success.
+  @retval EFI_INVALID_PARAMETER  A parameter is invalid.
+  @retval EFI_NOT_FOUND          The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetGicCInfo (
+  IN  CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL  * CONST This,
+  IN  CONST CM_OBJECT_ID                                  CmObjectId,
+  IN  CONST CM_OBJECT_TOKEN                               SearchToken,
+  IN  OUT   CM_OBJ_DESCRIPTOR                     * CONST CmObject
+  )
+{
+  EDKII_PLATFORM_REPOSITORY_INFO  * PlatformRepo;
+  NEOVERSEN1SOC_PLAT_INFO           *PlatInfo;
+  UINT32                            TotalObjCount;
+  UINT32                            ObjIndex;
+
+  if ((This == NULL) || (CmObject == NULL)) {
+    ASSERT (This != NULL);
+    ASSERT (CmObject != NULL);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  PlatformRepo = This->PlatRepoInfo;
+  PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
+
+  if (PlatInfo->MultichipMode == 1) {
+    TotalObjCount = PLAT_CPU_COUNT * 2;
+  } else {
+    TotalObjCount = PLAT_CPU_COUNT;
+  }
+
+  for (ObjIndex = 0; ObjIndex < TotalObjCount; ObjIndex++) {
+    if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->GicCInfo[ObjIndex]) {
+      CmObject->ObjectId = CmObjectId;
+      CmObject->Size = sizeof (PlatformRepo->GicCInfo[ObjIndex]);
+      CmObject->Data = (VOID*)&PlatformRepo->GicCInfo[ObjIndex];
+      CmObject->Count = 1;
+      return EFI_SUCCESS;
+    }
+  }
+
+  return EFI_NOT_FOUND;
+}
+
+/** Return a list of Configuration Manager object references pointed to by the
+    given input token.
+
+  @param [in]        This        Pointer to the Configuration Manager Protocol.
+  @param [in]        CmObjectId  The Object ID of the CM object requested
+  @param [in]        SearchToken A unique token for identifying the requested
+                                 CM_ARM_OBJ_REF list.
+  @param [in, out]   CmObject    Pointer to the Configuration Manager Object
+                                 descriptor describing the requested Object.
+
+  @retval EFI_SUCCESS            Success.
+  @retval EFI_INVALID_PARAMETER  A parameter is invalid.
+  @retval EFI_NOT_FOUND          The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetCmObjRefs (
+  IN  CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL  * CONST This,
+  IN  CONST CM_OBJECT_ID                                  CmObjectId,
+  IN  CONST CM_OBJECT_TOKEN                               SearchToken,
+  IN  OUT   CM_OBJ_DESCRIPTOR                     * CONST CmObject
+  )
+{
+  EDKII_PLATFORM_REPOSITORY_INFO  * PlatformRepo;
+
+  if ((This == NULL) || (CmObject == NULL)) {
+    ASSERT (This != NULL);
+    ASSERT (CmObject != NULL);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  PlatformRepo = This->PlatRepoInfo;
+
+  if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->ClusterResources) {
+    CmObject->Size = sizeof (PlatformRepo->ClusterResources);
+    CmObject->Data = (VOID*)&PlatformRepo->ClusterResources;
+    CmObject->Count = ARRAY_SIZE (PlatformRepo->ClusterResources);
+    return EFI_SUCCESS;
+  }
+  if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->CoreResources) {
+    CmObject->Size = sizeof (PlatformRepo->CoreResources);
+    CmObject->Data = (VOID*)&PlatformRepo->CoreResources;
+    CmObject->Count = ARRAY_SIZE (PlatformRepo->CoreResources);
+    return EFI_SUCCESS;
+  }
+  if (SearchToken == (CM_OBJECT_TOKEN)&PlatformRepo->SocResources) {
+    CmObject->Size = sizeof (PlatformRepo->SocResources);
+    CmObject->Data = (VOID*)&PlatformRepo->SocResources;
+    CmObject->Count = ARRAY_SIZE (PlatformRepo->SocResources);
+    return EFI_SUCCESS;
+  }
+
+  return EFI_NOT_FOUND;
+}
+
+/** Return a standard namespace object.
+
+  @param [in]        This        Pointer to the Configuration Manager Protocol.
+  @param [in]        CmObjectId  The Configuration Manager Object ID.
+  @param [in]        Token       An optional token identifying the object. If
+                                 unused this must be CM_NULL_TOKEN.
+  @param [in, out]   CmObject    Pointer to the Configuration Manager Object
+                                 descriptor describing the requested Object.
+
+  @retval EFI_SUCCESS            Success.
+  @retval EFI_INVALID_PARAMETER  A parameter is invalid.
+  @retval EFI_NOT_FOUND          The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetStandardNameSpaceObject (
+  IN  CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL  * CONST This,
+  IN  CONST CM_OBJECT_ID                                  CmObjectId,
+  IN  CONST CM_OBJECT_TOKEN                               Token OPTIONAL,
+  IN  OUT   CM_OBJ_DESCRIPTOR                     * CONST CmObject
+  )
+{
+  EFI_STATUS                        Status;
+  EDKII_PLATFORM_REPOSITORY_INFO  * PlatformRepo;
+  NEOVERSEN1SOC_PLAT_INFO           *PlatInfo;
+  UINT32                            AcpiTableCount;
+
+  if ((This == NULL) || (CmObject == NULL)) {
+    ASSERT (This != NULL);
+    ASSERT (CmObject != NULL);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Status = EFI_NOT_FOUND;
+  PlatformRepo = This->PlatRepoInfo;
+  PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
+  AcpiTableCount = ARRAY_SIZE (PlatformRepo->CmAcpiTableList);
+  if (PlatInfo->MultichipMode == 0)
+        AcpiTableCount -= 1;
+
+  switch (GET_CM_OBJECT_ID (CmObjectId)) {
+    case EStdObjCfgMgrInfo:
+      Status = HandleCmObject (
+                 CmObjectId,
+                 &PlatformRepo->CmInfo,
+                 sizeof (PlatformRepo->CmInfo),
+                 1,
+                 CmObject
+                 );
+      break;
+    case EStdObjAcpiTableList:
+      Status = HandleCmObject (
+                 CmObjectId,
+                 &PlatformRepo->CmAcpiTableList,
+                 sizeof (PlatformRepo->CmAcpiTableList),
+                 AcpiTableCount,
+                 CmObject
+                 );
+      break;
+    default: {
+      Status = EFI_NOT_FOUND;
+      DEBUG ((
+        DEBUG_ERROR,
+        "ERROR: Object 0x%x. Status = %r\n",
+        CmObjectId,
+        Status
+        ));
+      break;
+    }
+  }
+
+  return Status;
+}
+
+/** Return an ARM namespace object.
+
+  @param [in]        This        Pointer to the Configuration Manager Protocol.
+  @param [in]        CmObjectId  The Configuration Manager Object ID.
+  @param [in]        Token       An optional token identifying the object. If
+                                 unused this must be CM_NULL_TOKEN.
+  @param [in, out]   CmObject    Pointer to the Configuration Manager Object
+                                 descriptor describing the requested Object.
+
+  @retval EFI_SUCCESS            Success.
+  @retval EFI_INVALID_PARAMETER  A parameter is invalid.
+  @retval EFI_NOT_FOUND          The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetArmNameSpaceObject (
+  IN  CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL  * CONST This,
+  IN  CONST CM_OBJECT_ID                                  CmObjectId,
+  IN  CONST CM_OBJECT_TOKEN                               Token OPTIONAL,
+  IN  OUT   CM_OBJ_DESCRIPTOR                     * CONST CmObject
+  )
+{
+  EFI_STATUS                        Status;
+  EDKII_PLATFORM_REPOSITORY_INFO  * PlatformRepo;
+  NEOVERSEN1SOC_PLAT_INFO           *PlatInfo;
+  UINT32                            GicRedistCount;
+  UINT32                            GicCpuCount;
+  UINT32                            ProcHierarchyInfoCount;
+  UINT32                            GicItsInfoCount;
+  UINT32                            ItsGroupInfoCount;
+  UINT32                            ItsIdentifierArrayCount;
+  UINT32                            SmmuV3InfoCount;
+  UINT32                            DeviceIdMappingCount;
+  UINT32                            RootComplexInfoCount;
+  UINT32                            PciConfigInfoCount;
+
+  if ((This == NULL) || (CmObject == NULL)) {
+    ASSERT (This != NULL);
+    ASSERT (CmObject != NULL);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Status = EFI_NOT_FOUND;
+  PlatformRepo = This->PlatRepoInfo;
+
+  // Probe for multi chip information
+  PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
+  if (PlatInfo->MultichipMode == 1) {
+    GicRedistCount = 2;
+    GicCpuCount = PLAT_CPU_COUNT * 2;
+    ProcHierarchyInfoCount = PLAT_PROC_HIERARCHY_NODE_COUNT * 2;
+    GicItsInfoCount = ITS_MAX;
+    ItsGroupInfoCount = ITS_MAX;
+    ItsIdentifierArrayCount = ITS_MAX;
+    SmmuV3InfoCount = SMMUV3INFO_MAX;
+    DeviceIdMappingCount = DEVICEIDMAPPING_MAX;
+    RootComplexInfoCount = ROOT_PCIE_MAX;
+    PciConfigInfoCount = ROOT_PCIE_MAX;
+  } else {
+    GicRedistCount = 1;
+    GicCpuCount = PLAT_CPU_COUNT;
+    ProcHierarchyInfoCount = PLAT_PROC_HIERARCHY_NODE_COUNT;
+    GicItsInfoCount = ITS_MASTER_CHIP_MAX;
+    ItsGroupInfoCount = ITS_MASTER_CHIP_MAX;
+    ItsIdentifierArrayCount = ITS_MASTER_CHIP_MAX;
+    SmmuV3InfoCount = SMMUV3INFO_MASTER_CHIP_MAX;
+    DeviceIdMappingCount = DEVICEIDMAPPING_MASTER_CHIP_MAX;
+    RootComplexInfoCount = ROOT_PCIE_MASTER_CHIP_MAX;
+    PciConfigInfoCount = ROOT_PCIE_MASTER_CHIP_MAX;
+  }
+
+  switch (GET_CM_OBJECT_ID (CmObjectId)) {
+    case EArmObjBootArchInfo:
+      Status = HandleCmObject (
+                 CmObjectId,
+                 &PlatformRepo->BootArchInfo,
+                 sizeof (PlatformRepo->BootArchInfo),
+                 1,
+                 CmObject
+                 );
+      break;
+
+    case EArmObjFixedFeatureFlags:
+      Status = HandleCmObject (
+                 CmObjectId,
+                 &PlatformRepo->FixedFeatureFlags,
+                 sizeof (PlatformRepo->FixedFeatureFlags),
+                 1,
+                 CmObject
+                 );
+      break;
+
+    case EArmObjPowerManagementProfileInfo:
+      Status = HandleCmObject (
+                 CmObjectId,
+                 &PlatformRepo->PmProfileInfo,
+                 sizeof (PlatformRepo->PmProfileInfo),
+                 1,
+                 CmObject
+                 );
+      break;
+
+    case EArmObjGenericTimerInfo:
+      Status = HandleCmObject (
+                 CmObjectId,
+                 &PlatformRepo->GenericTimerInfo,
+                 sizeof (PlatformRepo->GenericTimerInfo),
+                 1,
+                 CmObject
+                 );
+      break;
+
+    case EArmObjPlatformGenericWatchdogInfo:
+      Status = HandleCmObject (
+                 CmObjectId,
+                 &PlatformRepo->Watchdog,
+                 sizeof (PlatformRepo->Watchdog),
+                 1,
+                 CmObject
+                 );
+      break;
+
+    case EArmObjPlatformGTBlockInfo:
+      Status = HandleCmObject (
+                 CmObjectId,
+                 PlatformRepo->GTBlockInfo,
+                 sizeof (PlatformRepo->GTBlockInfo),
+                 ARRAY_SIZE (PlatformRepo->GTBlockInfo),
+                 CmObject
+                 );
+      break;
+
+    case EArmObjGTBlockTimerFrameInfo:
+      Status = HandleCmObjectRefByToken (
+                 This,
+                 CmObjectId,
+                 PlatformRepo->GTBlock0TimerInfo,
+                 sizeof (PlatformRepo->GTBlock0TimerInfo),
+                 ARRAY_SIZE (PlatformRepo->GTBlock0TimerInfo),
+                 Token,
+                 GetGTBlockTimerFrameInfo,
+                 CmObject
+                 );
+      break;
+
+    case EArmObjGicCInfo:
+      Status = HandleCmObjectRefByToken (
+                 This,
+                 CmObjectId,
+                 PlatformRepo->GicCInfo,
+                 sizeof (PlatformRepo->GicCInfo),
+                 GicCpuCount,
+                 Token,
+                 GetGicCInfo,
+                 CmObject
+                 );
+      break;
+
+    case EArmObjGicDInfo:
+      Status = HandleCmObject (
+                 CmObjectId,
+                 &PlatformRepo->GicDInfo,
+                 sizeof (PlatformRepo->GicDInfo),
+                 1,
+                 CmObject
+                 );
+      break;
+
+    case EArmObjGicRedistributorInfo:
+      Status = HandleCmObject (
+                 CmObjectId,
+                 PlatformRepo->GicRedistInfo,
+                 sizeof (PlatformRepo->GicRedistInfo),
+                 GicRedistCount,
+                 CmObject
+                 );
+      break;
+
+    case EArmObjSerialConsolePortInfo:
+      Status = HandleCmObject (
+                 CmObjectId,
+                 &PlatformRepo->SpcrSerialPort,
+                 sizeof (PlatformRepo->SpcrSerialPort),
+                 1,
+                 CmObject
+                 );
+      break;
+
+    case  EArmObjSerialDebugPortInfo:
+      Status = HandleCmObject (
+                 CmObjectId,
+                 &PlatformRepo->DbgSerialPort,
+                 sizeof (PlatformRepo->DbgSerialPort),
+                 1,
+                 CmObject
+                 );
+      break;
+
+    case EArmObjGicItsInfo:
+      Status = HandleCmObject (
+                 CmObjectId,
+                 PlatformRepo->GicItsInfo,
+                 sizeof (PlatformRepo->GicItsInfo),
+                 GicItsInfoCount,
+                 CmObject
+                 );
+      break;
+
+    case EArmObjSmmuV3:
+      Status = HandleCmObject (
+                 CmObjectId,
+                 PlatformRepo->SmmuV3Info,
+                 sizeof (PlatformRepo->SmmuV3Info),
+                 SmmuV3InfoCount,
+                 CmObject
+                 );
+      break;
+
+    case EArmObjItsGroup:
+      Status = HandleCmObjectRefByToken (
+                 This,
+                 CmObjectId,
+                 PlatformRepo->ItsGroupInfo,
+                 sizeof (PlatformRepo->ItsGroupInfo),
+                 ItsGroupInfoCount,
+                 Token,
+                 GetItsGroupInfo,
+                 CmObject
+                 );
+      break;
+
+    case EArmObjGicItsIdentifierArray:
+      Status = HandleCmObjectRefByToken (
+                 This,
+                 CmObjectId,
+                 PlatformRepo->ItsIdentifierArray,
+                 sizeof (PlatformRepo->ItsIdentifierArray),
+                 ItsIdentifierArrayCount,
+                 Token,
+                 GetItsIdentifierArray,
+                 CmObject
+                 );
+      break;
+
+    case EArmObjRootComplex:
+      Status = HandleCmObject (
+                 CmObjectId,
+                 PlatformRepo->RootComplexInfo,
+                 sizeof (PlatformRepo->RootComplexInfo),
+                 RootComplexInfoCount,
+                 CmObject
+                 );
+      break;
+
+    case EArmObjIdMappingArray:
+      Status = HandleCmObjectRefByToken (
+                 This,
+                 CmObjectId,
+                 PlatformRepo->DeviceIdMapping,
+                 sizeof (PlatformRepo->DeviceIdMapping),
+                 DeviceIdMappingCount,
+                 Token,
+                 GetDeviceIdMappingArray,
+                 CmObject
+                 );
+      break;
+
+    case EArmObjProcHierarchyInfo:
+      Status = HandleCmObject (
+                 CmObjectId,
+                 PlatformRepo->ProcHierarchyInfo,
+                 sizeof (PlatformRepo->ProcHierarchyInfo),
+                 ProcHierarchyInfoCount,
+                 CmObject
+                 );
+      break;
+
+    case EArmObjCacheInfo:
+      Status = HandleCmObject (
+                 CmObjectId,
+                 PlatformRepo->CacheInfo,
+                 sizeof (PlatformRepo->CacheInfo),
+                 ARRAY_SIZE (PlatformRepo->CacheInfo),
+                 CmObject
+                 );
+      break;
+
+    case EArmObjCmRef:
+      Status = HandleCmObjectSearchPlatformRepo (
+                 This,
+                 CmObjectId,
+                 Token,
+                 GetCmObjRefs,
+                 CmObject
+                 );
+      break;
+
+    case EArmObjPciConfigSpaceInfo:
+      Status = HandleCmObject (
+                 CmObjectId,
+                 PlatformRepo->PciConfigInfo,
+                 sizeof (PlatformRepo->PciConfigInfo),
+                 PciConfigInfoCount,
+                 CmObject
+                 );
+      break;
+
+    case EArmObjMemoryAffinityInfo:
+      Status = HandleCmObject (
+                 CmObjectId,
+                 PlatformRepo->MemAffInfo,
+                 sizeof (PlatformRepo->MemAffInfo),
+                 ARRAY_SIZE (PlatformRepo->MemAffInfo),
+                 CmObject
+                 );
+      break;
+
+    default: {
+      Status = EFI_NOT_FOUND;
+      DEBUG ((
+        DEBUG_INFO,
+        "INFO: Object 0x%x. Status = %r\n",
+        CmObjectId,
+        Status
+        ));
+      break;
+    }
+  }//switch
+
+  return Status;
+}
+
+/** Return an OEM namespace object.
+
+  @param [in]        This        Pointer to the Configuration Manager Protocol.
+  @param [in]        CmObjectId  The Configuration Manager Object ID.
+  @param [in]        Token       An optional token identifying the object. If
+                                 unused this must be CM_NULL_TOKEN.
+  @param [in, out]   CmObject    Pointer to the Configuration Manager Object
+                                 descriptor describing the requested Object.
+
+  @retval EFI_SUCCESS            Success.
+  @retval EFI_INVALID_PARAMETER  A parameter is invalid.
+  @retval EFI_NOT_FOUND          The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetOemNameSpaceObject (
+  IN  CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL  * CONST This,
+  IN  CONST CM_OBJECT_ID                                  CmObjectId,
+  IN  CONST CM_OBJECT_TOKEN                               Token OPTIONAL,
+  IN  OUT   CM_OBJ_DESCRIPTOR                     * CONST CmObject
+  )
+{
+  EFI_STATUS  Status;
+
+  Status = EFI_SUCCESS;
+  if ((This == NULL) || (CmObject == NULL)) {
+    ASSERT (This != NULL);
+    ASSERT (CmObject != NULL);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  switch (GET_CM_OBJECT_ID (CmObjectId)) {
+    default: {
+      Status = EFI_NOT_FOUND;
+      DEBUG ((
+        DEBUG_ERROR,
+        "ERROR: Object 0x%x. Status = %r\n",
+        CmObjectId,
+        Status
+        ));
+      break;
+    }
+  }
+
+  return Status;
+}
+
+/** The GetObject function defines the interface implemented by the
+    Configuration Manager Protocol for returning the Configuration
+    Manager Objects.
+
+  @param [in]        This        Pointer to the Configuration Manager Protocol.
+  @param [in]        CmObjectId  The Configuration Manager Object ID.
+  @param [in]        Token       An optional token identifying the object. If
+                                 unused this must be CM_NULL_TOKEN.
+  @param [in, out]   CmObject    Pointer to the Configuration Manager Object
+                                 descriptor describing the requested Object.
+
+  @retval EFI_SUCCESS            Success.
+  @retval EFI_INVALID_PARAMETER  A parameter is invalid.
+  @retval EFI_NOT_FOUND          The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+N1sdpPlatformGetObject (
+  IN  CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL  * CONST This,
+  IN  CONST CM_OBJECT_ID                                  CmObjectId,
+  IN  CONST CM_OBJECT_TOKEN                               Token OPTIONAL,
+  IN  OUT   CM_OBJ_DESCRIPTOR                     * CONST CmObject
+  )
+{
+  EFI_STATUS  Status;
+
+  if ((This == NULL) || (CmObject == NULL)) {
+    ASSERT (This != NULL);
+    ASSERT (CmObject != NULL);
+    return EFI_INVALID_PARAMETER;
+  }
+
+  switch (GET_CM_NAMESPACE_ID (CmObjectId)) {
+    case EObjNameSpaceStandard:
+      Status = GetStandardNameSpaceObject (This, CmObjectId, Token, CmObject);
+      break;
+    case EObjNameSpaceArm:
+      Status = GetArmNameSpaceObject (This, CmObjectId, Token, CmObject);
+      break;
+    case EObjNameSpaceOem:
+      Status = GetOemNameSpaceObject (This, CmObjectId, Token, CmObject);
+      break;
+    default: {
+      Status = EFI_INVALID_PARAMETER;
+      DEBUG ((
+        DEBUG_ERROR,
+        "ERROR: Unknown Namespace Object = 0x%x. Status = %r\n",
+        CmObjectId,
+        Status
+        ));
+      break;
+    }
+  }
+
+  return Status;
+}
+
+/** The SetObject function defines the interface implemented by the
+    Configuration Manager Protocol for updating the Configuration
+    Manager Objects.
+
+  @param [in]        This        Pointer to the Configuration Manager Protocol.
+  @param [in]        CmObjectId  The Configuration Manager Object ID.
+  @param [in]        Token       An optional token identifying the object. If
+                                 unused this must be CM_NULL_TOKEN.
+  @param [in]        CmObject    Pointer to the Configuration Manager Object
+                                 descriptor describing the Object.
+
+  @retval EFI_UNSUPPORTED        This operation is not supported.
+**/
+EFI_STATUS
+EFIAPI
+N1sdpPlatformSetObject (
+  IN  CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL  * CONST This,
+  IN  CONST CM_OBJECT_ID                                  CmObjectId,
+  IN  CONST CM_OBJECT_TOKEN                               Token OPTIONAL,
+  IN        CM_OBJ_DESCRIPTOR                     * CONST CmObject
+  )
+{
+  return EFI_UNSUPPORTED;
+}
+
+/** A structure describing the configuration manager protocol interface.
+*/
+STATIC
+CONST
+EDKII_CONFIGURATION_MANAGER_PROTOCOL N1sdpPlatformConfigManagerProtocol = {
+  CREATE_REVISION(1,0),
+  N1sdpPlatformGetObject,
+  N1sdpPlatformSetObject,
+  &N1sdpRepositoryInfo
+};
+
+/**
+  Entrypoint of Configuration Manager Dxe.
+
+  @param  ImageHandle
+  @param  SystemTable
+
+  @return EFI_SUCCESS
+  @return EFI_LOAD_ERROR
+  @return EFI_OUT_OF_RESOURCES
+**/
+EFI_STATUS
+EFIAPI
+ConfigurationManagerDxeInitialize (
+  IN EFI_HANDLE          ImageHandle,
+  IN EFI_SYSTEM_TABLE  * SystemTable
+  )
+{
+  EFI_STATUS  Status;
+
+  // Initialize the Platform Configuration Repository before installing the
+  // Configuration Manager Protocol
+  Status = InitializePlatformRepository (
+    N1sdpPlatformConfigManagerProtocol.PlatRepoInfo
+    );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((
+      DEBUG_ERROR,
+      "ERROR: Failed to initialize the Platform Configuration Repository." \
+      " Status = %r\n",
+      Status
+      ));
+  }
+
+  Status = gBS->InstallProtocolInterface (
+                  &ImageHandle,
+                  &gEdkiiConfigurationManagerProtocolGuid,
+                  EFI_NATIVE_INTERFACE,
+                  (VOID*)&N1sdpPlatformConfigManagerProtocol
+                  );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((
+      DEBUG_ERROR,
+      "ERROR: Failed to get Install Configuration Manager Protocol." \
+      " Status = %r\n",
+      Status
+      ));
+    goto error_handler;
+  }
+
+error_handler:
+  return Status;
+}
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
new file mode 100644
index 0000000000..e2edbf6ee5
--- /dev/null
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
@@ -0,0 +1,307 @@
+/** @file
+
+  Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Glossary:
+    - Cm or CM   - Configuration Manager
+    - Obj or OBJ - Object
+**/
+
+#ifndef CONFIGURATION_MANAGER_H_
+#define CONFIGURATION_MANAGER_H_
+
+/** C array containing the compiled AML template.
+    This symbol is defined in the auto generated C file
+    containing the AML bytecode array.
+*/
+extern CHAR8 dsdt_aml_code[];
+extern CHAR8 ssdtpci_aml_code[];
+extern CHAR8 ssdtremotepci_aml_code[];
+
+/** The configuration manager version.
+*/
+#define CONFIGURATION_MANAGER_REVISION CREATE_REVISION (1, 0)
+
+/** The OEM ID
+*/
+#define CFG_MGR_OEM_ID    { 'A', 'R', 'M', 'L', 'T', 'D' }
+
+/** A helper macro for mapping a reference token
+*/
+#define REFERENCE_TOKEN(Field)                                    \
+  (CM_OBJECT_TOKEN)((UINT8*)&N1sdpRepositoryInfo +                \
+    OFFSET_OF (EDKII_PLATFORM_REPOSITORY_INFO, Field))
+
+/** A helper macro that constructs the MPID based on the
+    Aff0, Aff1, Aff2, Aff3 values
+*/
+#define GET_MPID3(Aff3, Aff2, Aff1, Aff0)                         \
+  (((Aff3##ULL) << 32) | ((Aff2) << 16) | ((Aff1) << 8) | (Aff0))
+
+/** A helper macro for populating the GIC CPU information
+*/
+#define GICC_ENTRY(                                                      \
+          CPUInterfaceNumber,                                            \
+          Mpidr,                                                         \
+          PmuIrq,                                                        \
+          VGicIrq,                                                       \
+          GicRedistBase,                                                 \
+          EnergyEfficiency,                                              \
+          SpeIrq,                                                        \
+          ProximityDomain,                                               \
+          ClockDomain                                                    \
+          ) {                                                            \
+    CPUInterfaceNumber,       /* UINT32  CPUInterfaceNumber           */ \
+    CPUInterfaceNumber,       /* UINT32  AcpiProcessorUid             */ \
+    EFI_ACPI_6_2_GIC_ENABLED, /* UINT32  Flags                        */ \
+    0,                        /* UINT32  ParkingProtocolVersion       */ \
+    PmuIrq,                   /* UINT32  PerformanceInterruptGsiv     */ \
+    0,                        /* UINT64  ParkedAddress                */ \
+    FixedPcdGet64 (                                                      \
+      PcdGicInterruptInterfaceBase                                       \
+      ),                      /* UINT64  PhysicalBaseAddress          */ \
+    0,                        /* UINT64  GICV                         */ \
+    0,                        /* UINT64  GICH                         */ \
+    VGicIrq,                  /* UINT32  VGICMaintenanceInterrupt     */ \
+    GicRedistBase,            /* UINT64  GICRBaseAddress              */ \
+    Mpidr,                    /* UINT64  MPIDR                        */ \
+    EnergyEfficiency,         /* UINT8   ProcessorPowerEfficiencyClass*/ \
+    SpeIrq,                   /* UINT16  SpeOverflowInterrupt         */ \
+    ProximityDomain,          /* UINT32  ProximityDomain              */ \
+    ClockDomain,              /* UINT32  ClockDomain                  */ \
+    EFI_ACPI_6_3_GICC_ENABLED,/* UINT32  Flags                        */ \
+    }
+
+/** A helper macro for populating the Processor Hierarchy Node flags
+*/
+#define PROC_NODE_FLAGS(                                                \
+          PhysicalPackage,                                              \
+          AcpiProcessorIdValid,                                         \
+          ProcessorIsThread,                                            \
+          NodeIsLeaf,                                                   \
+          IdenticalImplementation                                       \
+          )                                                             \
+  (                                                                     \
+    PhysicalPackage |                                                   \
+    (AcpiProcessorIdValid << 1) |                                       \
+    (ProcessorIsThread << 2) |                                          \
+    (NodeIsLeaf << 3) |                                                 \
+    (IdenticalImplementation << 4)                                      \
+  )
+
+/** A helper macro for populating the Cache Type Structure's attributes
+*/
+#define CACHE_ATTRIBUTES(                                               \
+          AllocationType,                                               \
+          CacheType,                                                    \
+          WritePolicy                                                   \
+          )                                                             \
+  (                                                                     \
+    AllocationType |                                                    \
+    (CacheType << 2) |                                                  \
+    (WritePolicy << 4)                                                  \
+  )
+
+/** A function that prepares Configuration Manager Objects for returning.
+  @param [in]  This        Pointer to the Configuration Manager Protocol.
+  @param [in]  CmObjectId  The Configuration Manager Object ID.
+  @param [in]  Token       A token for identifying the object.
+  @param [out] CmObject    Pointer to the Configuration Manager Object
+                           descriptor describing the requested Object.
+  @retval EFI_SUCCESS           Success.
+  @retval EFI_INVALID_PARAMETER A parameter is invalid.
+  @retval EFI_NOT_FOUND         The required object information is not found.
+**/
+typedef EFI_STATUS (*CM_OBJECT_HANDLER_PROC) (
+  IN  CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL  * CONST This,
+  IN  CONST CM_OBJECT_ID                                  CmObjectId,
+  IN  CONST CM_OBJECT_TOKEN                               Token,
+  IN  OUT   CM_OBJ_DESCRIPTOR                     * CONST CmObject
+  );
+
+/** The number of CPUs
+*/
+#define PLAT_CPU_COUNT              4
+
+/** The number of ACPI tables to install
+*/
+#define PLAT_ACPI_TABLE_COUNT       13
+
+/** The number of platform generic timer blocks
+*/
+#define PLAT_GTBLOCK_COUNT          1
+
+/** The number of timer frames per generic timer block
+*/
+#define PLAT_GTFRAME_COUNT          2
+
+/** The number of Processor Hierarchy Nodes
+    - one package node
+    - two cluster nodes
+    - two cores in cluster 0
+    - two cores in cluster 1
+*/
+#define PLAT_PROC_HIERARCHY_NODE_COUNT  7
+
+/** The number of unique cache structures:
+    - cluster L3 unified cache
+    - core L1 instruction cache
+    - core L1 data cache
+    - core L2 cache
+    - slc unified cache
+*/
+#define PLAT_CACHE_COUNT                5
+
+/** The number of resources private to the cluster
+    - L3 cache
+*/
+#define CLUSTER_RESOURCE_COUNT  1
+
+/** The number of resources private to 'core instance
+    - L1 data cache
+    - L1 instruction cache
+*/
+#define CORE_RESOURCE_COUNT  2
+
+/** The number of resources private to SoC
+    - slc cache
+*/
+#define SOC_RESOURCE_COUNT  1
+
+/** Number of memory affinity entries
+*/
+#define LOCAL_DDR_REGION1   0
+#define LOCAL_DDR_REGION2   1
+#define REMOTE_DDR_REGION1  2
+#define REMOTE_DDR_REGION2  3
+#define DDR_REGION_COUNT    4
+
+typedef enum {
+   ITS_SMMU_CCIX = 0,
+   ITS_SMMU_PCIE,
+   ITS_CCIX,
+   ITS_PCIE,
+   ITS_MASTER_CHIP_MAX,
+   ITS_REMOTE_SMMU_PCIE = ITS_MASTER_CHIP_MAX,
+   ITS_REMOTE_PCIE,
+   ITS_MAX
+} ITS_ID;
+
+typedef enum {
+   SMMUV3INFO_PCIE = 0,
+   SMMUV3INFO_CCIX,
+   SMMUV3INFO_MASTER_CHIP_MAX,
+   SMMUV3INFO_REMOTE_PCIE = SMMUV3INFO_MASTER_CHIP_MAX,
+   SMMUV3INFO_MAX
+} SMMU_INFO_V3;
+
+typedef enum {
+   ROOT_PCIE = 0,
+   ROOT_PCIE_CCIX,
+   ROOT_PCIE_MASTER_CHIP_MAX,
+   ROOT_REMOTE_PCIE = ROOT_PCIE_MASTER_CHIP_MAX,
+   ROOT_PCIE_MAX
+} N1SDP_ROOT_PORT;
+
+typedef enum {
+   DEVICEIDMAPPING_SMMU_PCIE = 0,
+   DEVICEIDMAPPING_SMMU_CCIX,
+   DEVICEIDMAPPING_PCIE,
+   DEVICEIDMAPPING_MASTER_CHIP_MAX,
+   DEVICEIDMAPPING_REMOTE_SMMU_PCIE = DEVICEIDMAPPING_MASTER_CHIP_MAX,
+   DEVICEIDMAPPING_REMOTE_PCIE,
+   DEVICEIDMAPPING_MAX,
+} N1SDP_DEVID;
+
+/** A structure describing the platform configuration
+    manager repository information
+*/
+typedef struct PlatformRepositoryInfo {
+  /// Configuration Manager Information
+  CM_STD_OBJ_CONFIGURATION_MANAGER_INFO CmInfo;
+
+  /// List of ACPI tables
+  CM_STD_OBJ_ACPI_TABLE_INFO            CmAcpiTableList[PLAT_ACPI_TABLE_COUNT];
+
+  /// Boot architecture information
+  CM_ARM_BOOT_ARCH_INFO                 BootArchInfo;
+
+  /// Fixed feature flag information
+  CM_ARM_FIXED_FEATURE_FLAGS            FixedFeatureFlags;
+
+  /// Power management profile information
+  CM_ARM_POWER_MANAGEMENT_PROFILE_INFO  PmProfileInfo;
+
+  /// GIC CPU interface information
+  CM_ARM_GICC_INFO                      GicCInfo[PLAT_CPU_COUNT * 2];
+
+  /// GIC distributor information
+  CM_ARM_GICD_INFO                      GicDInfo;
+
+  /// GIC Redistributor information
+  CM_ARM_GIC_REDIST_INFO                GicRedistInfo[2];
+
+  /// GIC ITS information
+  CM_ARM_GIC_ITS_INFO                   GicItsInfo[ITS_MAX];
+
+  /// Generic timer information
+  CM_ARM_GENERIC_TIMER_INFO             GenericTimerInfo;
+
+  /// Generic timer block information
+  CM_ARM_GTBLOCK_INFO                   GTBlockInfo[PLAT_GTBLOCK_COUNT];
+
+  /// Generic timer frame information
+  CM_ARM_GTBLOCK_TIMER_FRAME_INFO       GTBlock0TimerInfo[PLAT_GTFRAME_COUNT];
+
+  /// Watchdog information
+  CM_ARM_GENERIC_WATCHDOG_INFO          Watchdog;
+
+  /** Serial port information for the
+      serial port console redirection port
+  */
+  CM_ARM_SERIAL_PORT_INFO               SpcrSerialPort;
+
+  /// Serial port information for the DBG2 UART port
+  CM_ARM_SERIAL_PORT_INFO               DbgSerialPort;
+
+  // Processor topology information
+  CM_ARM_PROC_HIERARCHY_INFO            ProcHierarchyInfo[PLAT_PROC_HIERARCHY_NODE_COUNT * 2];
+
+  // Cache information
+  CM_ARM_CACHE_INFO                     CacheInfo[PLAT_CACHE_COUNT];
+
+  // Cluster private resources
+  CM_ARM_OBJ_REF                        ClusterResources[CLUSTER_RESOURCE_COUNT];
+
+  // Core private resources
+  CM_ARM_OBJ_REF                        CoreResources[CORE_RESOURCE_COUNT];
+
+  // SoC Resources
+  CM_ARM_OBJ_REF                        SocResources[SOC_RESOURCE_COUNT];
+
+  /// ITS Group node
+  CM_ARM_ITS_GROUP_NODE                 ItsGroupInfo[ITS_MAX];
+
+  /// ITS Identifier array
+  CM_ARM_ITS_IDENTIFIER                 ItsIdentifierArray[ITS_MAX];
+
+  /// SMMUv3 node
+  CM_ARM_SMMUV3_NODE                    SmmuV3Info[SMMUV3INFO_MAX];
+
+  /// PCI Root complex node
+  CM_ARM_ROOT_COMPLEX_NODE              RootComplexInfo[ROOT_PCIE_MAX];
+
+  /// Array of DeviceID mapping
+  CM_ARM_ID_MAPPING                     DeviceIdMapping[DEVICEIDMAPPING_MAX][2];
+
+  /// PCI configuration space information
+  CM_ARM_PCI_CONFIG_SPACE_INFO          PciConfigInfo[ROOT_PCIE_MAX];
+
+  /// Memory Affinity Info
+  CM_ARM_MEMORY_AFFINITY_INFO           MemAffInfo[DDR_REGION_COUNT];
+
+} EDKII_PLATFORM_REPOSITORY_INFO;
+
+#endif // CONFIGURATION_MANAGER_H_
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
new file mode 100644
index 0000000000..52207e7f7d
--- /dev/null
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
@@ -0,0 +1,167 @@
+## @file
+#  Configuration Manager Dxe
+#
+#  Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001B
+  BASE_NAME                      = ConfigurationManagerDxe
+  FILE_GUID                      = 6f9c3b47-6f7d-44b6-87e5-4b7f44a60147
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = ConfigurationManagerDxeInitialize
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = ARM AARCH64
+#
+
+[Sources]
+  AslTables/Dsdt.asl
+  AslTables/SsdtPci.asl
+  AslTables/SsdtRemotePci.asl
+  ConfigurationManager.c
+  ConfigurationManager.h
+  Hmat.c
+  Platform.h
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  DynamicTablesPkg/DynamicTablesPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Platform/ARM/N1Sdp/N1SdpPlatform.dec
+  Platform/ARM/VExpressPkg/ArmVExpressPkg.dec
+  Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+
+[LibraryClasses]
+  ArmPlatformLib
+  PrintLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  UefiRuntimeServicesTableLib
+
+[Protocols]
+  gEdkiiConfigurationManagerProtocolGuid
+
+[FixedPcd]
+  # PL011 Serial Debug UART
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz
+
+  gArmPlatformTokenSpaceGuid.PL011UartClkInHz
+  gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+  # SBSA Generic Watchdog
+  gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+  gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum
+  gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+
+  gArmN1SdpTokenSpaceGuid.PcdPcieExpressBaseAddress
+
+  gArmNeoverseN1SocTokenSpaceGuid.PcdExtMemorySpace
+  gArmNeoverseN1SocTokenSpaceGuid.PcdDramBlock2Base
+
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
+  gArmPlatformTokenSpaceGuid.PcdClusterCount
+
+  gArmTokenSpaceGuid.PcdSystemMemoryBase
+  gArmTokenSpaceGuid.PcdSystemMemorySize
+
+  #PCIe
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusCount
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMax
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieBusMin
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoBase
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoMaxBase
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoSize
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieIoTranslation
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Base
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32MaxBase
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Size
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio32Translation
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Base
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64MaxBase
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Size
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieMmio64Translation
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseAddress
+  gArmNeoverseN1SocTokenSpaceGuid.PcdPcieRootPortConfigBaseSize
+
+  # CCIX
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusCount
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMax
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixBusMin
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixExpressBaseAddress
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoBase
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoMaxBase
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoSize
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixIoTranslation
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Base
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32MaxBase
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Size
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio32Translation
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Base
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64MaxBase
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Size
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixMmio64Translation
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseAddress
+  gArmNeoverseN1SocTokenSpaceGuid.PcdCcixRootPortConfigBaseSize
+
+  # Coresight
+  gArmN1SdpTokenSpaceGuid.PcdCsComponentSize
+  gArmN1SdpTokenSpaceGuid.PcdCsEtf0Base
+  gArmN1SdpTokenSpaceGuid.PcdCsEtf0MaxBase
+  gArmN1SdpTokenSpaceGuid.PcdCsEtf1Base
+  gArmN1SdpTokenSpaceGuid.PcdCsEtf1MaxBase
+  gArmN1SdpTokenSpaceGuid.PcdCsEtf2Base
+  gArmN1SdpTokenSpaceGuid.PcdCsEtf2MaxBase
+  gArmN1SdpTokenSpaceGuid.PcdCsEtm0Base
+  gArmN1SdpTokenSpaceGuid.PcdCsEtm0MaxBase
+  gArmN1SdpTokenSpaceGuid.PcdCsEtm1Base
+  gArmN1SdpTokenSpaceGuid.PcdCsEtm1MaxBase
+  gArmN1SdpTokenSpaceGuid.PcdCsEtm2Base
+  gArmN1SdpTokenSpaceGuid.PcdCsEtm2MaxBase
+  gArmN1SdpTokenSpaceGuid.PcdCsEtm3Base
+  gArmN1SdpTokenSpaceGuid.PcdCsEtm3MaxBase
+  gArmN1SdpTokenSpaceGuid.PcdCsEtrBase
+  gArmN1SdpTokenSpaceGuid.PcdCsEtrMaxBase
+  gArmN1SdpTokenSpaceGuid.PcdCsFunnel0Base
+  gArmN1SdpTokenSpaceGuid.PcdCsFunnel0MaxBase
+  gArmN1SdpTokenSpaceGuid.PcdCsFunnel1Base
+  gArmN1SdpTokenSpaceGuid.PcdCsFunnel1MaxBase
+  gArmN1SdpTokenSpaceGuid.PcdCsReplicatorBase
+  gArmN1SdpTokenSpaceGuid.PcdCsReplicatorMaxBase
+  gArmN1SdpTokenSpaceGuid.PcdCsStmBase
+  gArmN1SdpTokenSpaceGuid.PcdCsStmMaxBase
+  gArmN1SdpTokenSpaceGuid.PcdCsStmStimulusBase
+  gArmN1SdpTokenSpaceGuid.PcdCsStmStimulusSize
+  gArmN1SdpTokenSpaceGuid.PcdCsTpiuBase
+  gArmN1SdpTokenSpaceGuid.PcdCsTpiuMaxBase
+
+  # Remote PCIe
+  gArmN1SdpTokenSpaceGuid.PcdRemotePcieIoTranslation
+  gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio32Translation
+  gArmN1SdpTokenSpaceGuid.PcdRemotePcieMmio64Translation
+
+[Depex]
+  TRUE
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Hmat.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Hmat.c
new file mode 100644
index 0000000000..52fc3108a2
--- /dev/null
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Hmat.c
@@ -0,0 +1,103 @@
+/** @file
+  Heterogeneous Memory Attribute Table (HMAT)
+
+  Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include "N1SdpAcpiHeader.h"
+
+//
+// Heterogeneous Memory Attribute Table
+//
+#pragma pack (1)
+
+typedef struct {
+  EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO LatencyStruct;
+  UINT32 InitiatorProximityDomainList[1];
+  UINT32 TargetProximityDomainList[2];
+  UINT16 LatencyEntry[1][2];
+} EFI_ACPI_6_3_HMAT_SYSTEM_LOCALITY_LATENCY_STRUCTURE;
+
+typedef struct {
+  EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER       Header;
+  EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES Memory[2];
+  EFI_ACPI_6_3_HMAT_SYSTEM_LOCALITY_LATENCY_STRUCTURE            LatencyInfo;
+} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
+
+#pragma pack ()
+
+EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
+  // Header
+  {
+    ARM_ACPI_HEADER (
+      EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+      EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
+      EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
+    ),
+    {0x00, 0x00, 0x00, 0x00},
+  },
+
+  // Memory Attribute Structure
+  {
+    {
+      EFI_ACPI_6_3_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES, // Type
+      {0x00, 0x00}, // Reserved
+      40, // Length
+      {.InitiatorProximityDomainValid = 1}, // Flags
+      {0x00, 0x00}, // Reserved1
+      0, // InitiatorProximityDomain
+      0, // MemoryProximityDomain
+      { 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00,
+      }, // Reserved2
+    },
+    {
+      EFI_ACPI_6_3_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES, // Type
+      {0x00, 0x00}, // Reserved
+      40, // Length
+      {.InitiatorProximityDomainValid = 1}, // Flags
+      {0x00, 0x00}, // Reserved1
+      0, // InitiatorProximityDomain
+      1, // MemoryProximityDomain
+      { 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00,
+      }, // Reserved2
+    },
+  },
+
+  // System Locality Latency Structure (LatencyInfo)
+  {
+    // LatencyStruct
+    {
+      EFI_ACPI_6_3_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO, // Type
+      {0x00, 0x00}, // Reserved
+      sizeof (EFI_ACPI_6_3_HMAT_SYSTEM_LOCALITY_LATENCY_STRUCTURE), // Length
+      {.MemoryHierarchy = 0}, // Flags
+      0, // DataType - Access latency
+      {0x00, 0x00}, // Reserved1
+      1, // NumberOfInitiatorProximityDomains
+      2, // NumberOfTargetProximityDomains
+      {0x00, 0x00, 0x00, 0x00}, // Reserved2
+      1000, // EntryBaseUnit - 1000ps = 1ns
+    },
+    // InitiatorProximityDomainList
+    { 0 },
+    // TargetProximityDomainList
+    { 0, 1 },
+    // LatencyEntry
+    {
+      {119, 200},
+    },
+  },
+};
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Platform.h b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Platform.h
new file mode 100644
index 0000000000..d220b09446
--- /dev/null
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Platform.h
@@ -0,0 +1,92 @@
+/** @file
+
+  Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PLATFORM_H_
+#define PLATFORM_H_
+
+#define ENABLE_MEM_MAPPED_TIMER
+
+#ifdef ENABLE_MEM_MAPPED_TIMER
+// REFCLK CNTControl
+#define N1SDP_SYSTEM_TIMER_BASE_ADDRESS   0x2A430000
+// REFCLK CNTRead
+#define N1SDP_CNT_READ_BASE_ADDRESS       0x2A800000
+#else
+#define N1SDP_SYSTEM_TIMER_BASE_ADDRESS   0xFFFFFFFFFFFFFFFF
+#define N1SDP_CNT_READ_BASE_ADDRESS       0xFFFFFFFFFFFFFFFF
+#endif
+
+// GT Block Timer
+// AP_REFCLK CNTCTL
+#define N1SDP_GT_BLOCK_CTL_BASE           0x2A810000
+#define N1SDP_TIMER_FRAMES_COUNT          2
+
+// GT Block Timer Frames
+// AP_REFCLK_S CNTBase0
+#define N1SDP_GT_BLOCK_FRAME0_CTL_BASE      0x2A830000
+#define N1SDP_GT_BLOCK_FRAME0_CTL_EL0_BASE  0xFFFFFFFFFFFFFFFF
+#define N1SDP_GT_BLOCK_FRAME0_GSIV          92
+
+// AP_REFCLK_NS CNTBase1
+#define N1SDP_GT_BLOCK_FRAME1_CTL_BASE      0x2A820000
+#define N1SDP_GT_BLOCK_FRAME1_CTL_EL0_BASE  0xFFFFFFFFFFFFFFFF
+#define N1SDP_GT_BLOCK_FRAME1_GSIV          91
+
+#define GTDT_TIMER_EDGE_TRIGGERED   \
+          EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED  0
+#define GTDT_TIMER_ACTIVE_LOW       \
+          EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH      0
+#define GTDT_TIMER_SAVE_CONTEXT     \
+          EFI_ACPI_6_3_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY
+#define GTDT_TIMER_LOSE_CONTEXT     0
+
+#define N1SDP_GTDT_GTIMER_FLAGS       (GTDT_TIMER_LOSE_CONTEXT   | \
+                                         GTDT_TIMER_ACTIVE_LOW   | \
+                                         GTDT_TIMER_LEVEL_TRIGGERED)
+
+// GT Block Timer Flags
+#define GTX_TIMER_EDGE_TRIGGERED    \
+          EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTX_TIMER_LEVEL_TRIGGERED   0
+#define GTX_TIMER_ACTIVE_LOW        \
+          EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTX_TIMER_ACTIVE_HIGH       0
+
+#define N1SDP_GTX_TIMER_FLAGS         (GTX_TIMER_ACTIVE_HIGH | \
+                                         GTX_TIMER_LEVEL_TRIGGERED)
+
+#define GTX_TIMER_SECURE            \
+          EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER
+#define GTX_TIMER_NON_SECURE        0
+#define GTX_TIMER_SAVE_CONTEXT      \
+          EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY
+#define GTX_TIMER_LOSE_CONTEXT      0
+
+#define N1SDP_GTX_COMMON_FLAGS_S      (GTX_TIMER_SAVE_CONTEXT      | \
+                                         GTX_TIMER_SECURE)
+#define N1SDP_GTX_COMMON_FLAGS_NS     (GTX_TIMER_SAVE_CONTEXT      | \
+                                         GTX_TIMER_NON_SECURE)
+
+// Watchdog
+#define SBSA_WATCHDOG_EDGE_TRIGGERED   \
+          EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE
+#define SBSA_WATCHDOG_LEVEL_TRIGGERED  0
+#define SBSA_WATCHDOG_ACTIVE_LOW       \
+          EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY
+#define SBSA_WATCHDOG_ACTIVE_HIGH      0
+#define SBSA_WATCHDOG_SECURE           \
+          EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER
+#define SBSA_WATCHDOG_NON_SECURE       0
+
+#define N1SDP_SBSA_WATCHDOG_FLAGS        (SBSA_WATCHDOG_NON_SECURE       | \
+                                            SBSA_WATCHDOG_ACTIVE_HIGH    | \
+                                            SBSA_WATCHDOG_LEVEL_TRIGGERED)
+
+#endif // PLATFORM_H_
-- 
2.17.1


  parent reply	other threads:[~2021-10-10 18:31 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-10 18:29 [PATCH v2 0/7] N1Sdp ACPI table and configuration manager support Khasim Mohammed
2021-10-10 18:29 ` [PATCH v2 1/7] Silicon/ARM/NeoverseN1Soc: Fix missing function documentation Khasim Mohammed
2021-10-13  9:30   ` [edk2-devel] " PierreGondois
2021-10-10 18:29 ` [PATCH v2 2/7] Silicon/ARM/NeoverseN1Soc: Define new PCDs and configure memory map Khasim Mohammed
2021-10-13  9:31   ` [edk2-devel] " PierreGondois
2021-10-10 18:29 ` [PATCH v2 3/7] Platform/ARM/N1Sdp: Introduce platform DXE driver Khasim Mohammed
2021-10-13  9:32   ` [edk2-devel] " PierreGondois
2021-10-10 18:29 ` [PATCH v2 4/7] Platform/ARM/N1Sdp: Enable N1Sdp platform specific configurations Khasim Mohammed
2021-10-13  9:42   ` [edk2-devel] " PierreGondois
2021-10-20 17:36     ` Khasim Mohammed
2021-10-10 18:29 ` [PATCH v2 5/7] Platform/ARM/N1Sdp: Introduce platform specific asl tables Khasim Mohammed
2021-10-19  8:14   ` [edk2-devel] " PierreGondois
2021-10-26 17:46     ` Khasim Mohammed
2021-10-10 18:29 ` Khasim Mohammed [this message]
2021-10-19  8:40   ` [edk2-devel] [PATCH v2 6/7] Platform/ARM/N1Sdp: Configuration Manager for N1Sdp PierreGondois
2021-10-10 18:29 ` [PATCH v2 7/7] Platform/ARM/N1Sdp: Enable ACPI tables and configuration manager Khasim Mohammed
2021-10-19  8:42   ` [edk2-devel] " PierreGondois

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