From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mx.groups.io with SMTP id smtpd.web11.11746.1634033764948223431 for ; Tue, 12 Oct 2021 03:16:05 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=N6GN8eRz; spf=pass (domain: redhat.com, ip: 170.10.133.124, mailfrom: kraxel@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1634033764; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=zFc8EiyqApDqyXy1IF8HNQVHGdmXvS1z8JJjjWA+FPI=; b=N6GN8eRzXzWnrLYCRqDr8KmbK2VtOt4M3FylBDa0YjekVmURJUXU3HphGXUNawjQpfkh8/ u3eRBmqHU41vwP00Wb/vChwcRAPHP23asMPDUB6/Sy5WnRYWCOMONsvC7g+efrZyTiotPc TMLONrkdcb/0FgkxuO/sFiE+xe8aZn0= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-454-zZst2dSyOLecXoBC7KYDVA-1; Tue, 12 Oct 2021 06:16:01 -0400 X-MC-Unique: zZst2dSyOLecXoBC7KYDVA-1 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 3ACF8801AC5; Tue, 12 Oct 2021 10:15:59 +0000 (UTC) Received: from sirius.home.kraxel.org (unknown [10.39.193.22]) by smtp.corp.redhat.com (Postfix) with ESMTPS id E4C2F60C04; Tue, 12 Oct 2021 10:15:58 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id 51F78180060E; Tue, 12 Oct 2021 12:15:57 +0200 (CEST) Date: Tue, 12 Oct 2021 12:15:57 +0200 From: "Gerd Hoffmann" To: devel@edk2.groups.io, min.m.xu@intel.com Cc: Eric Dong , Ray Ni , Rahul Kumar , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: Re: [edk2-devel] [PATCH V2 07/28] UefiCpuPkg: Support TDX in BaseXApicX2ApicLib Message-ID: <20211012101557.j5xjtrlyofj3tadb@sirius.home.kraxel.org> References: <0dcb1ac3ad788cc7a4fd293fcf183b6ea9bdffb9.1633401643.git.min.m.xu@intel.com> MIME-Version: 1.0 In-Reply-To: <0dcb1ac3ad788cc7a4fd293fcf183b6ea9bdffb9.1633401643.git.min.m.xu@intel.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=kraxel@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi, > + do { > + AsmCpuid (0, &LargestEax, &Ebx, &Ecx, &Edx); Use ConfidentialComputing PCD ? > +BOOLEAN > +EFIAPI > +AccessMsrNative ( I'd suggest to reverse the logic, i.e. have a AccessMsrTdxCall() which returns true in case (a) tdx is active and (b) the msr is not on the white list for native access ... > +{ > + UINT64 Val; > + UINT64 Status; > + if (!AccessMsrNative (MsrIndex) && BaseXApicIsTdxGuest ()) { ... the just use "if (AccessMsrTdxCall(MsrIndex)) { ..." here. Beside that: Are the apic msr registers the only ones which can be accessed directly? take care, Gerd