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Date: Thu, 14 Oct 2021 10:31:30 +0200
From: "Gerd Hoffmann" <kraxel@redhat.com>
To: Brijesh Singh <brijesh.singh@amd.com>
Cc: devel@edk2.groups.io, James Bottomley <jejb@linux.ibm.com>,
	Min Xu <min.m.xu@intel.com>, Jiewen Yao <jiewen.yao@intel.com>,
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	Ard Biesheuvel <ardb+tianocore@kernel.org>,
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	Michael Roth <Michael.Roth@amd.com>
Subject: Re: [PATCH v9 17/32] OvmfPkg/MemEncryptSevLib: add support to validate > 4GB memory in PEI phase
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 <20211013165713.727815-18-brijesh.singh@amd.com>
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On Wed, Oct 13, 2021 at 11:56:58AM -0500, Brijesh Singh wrote:
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275
> 
> The initial page built during the SEC phase is used by the
> MemEncryptSevSnpValidateSystemRam() for the system RAM validation. The
> page validation process requires using the PVALIDATE instruction;  the
> instruction accepts a virtual address of the memory region that needs
> to be validated. If hardware encounters a page table walk failure (due
> to page-not-present) then it raises #GP.
> 
> The initial page table built in SEC phase address up to 4GB. Add an
> internal function to extend the page table to cover > 4GB. The function
> builds 1GB entries in the page table for access > 4GB. This will provide
> the support to call PVALIDATE instruction for the virtual address >
> 4GB in PEI phase.

I think I asked this before:  This is likewise temporary until the
memory core can track page state and ovmf can handle lazy
acceptance/validation of memory > 4G in DXE phase, correct?

Can you add a comment for that?

The code looks good.

take care,
  Gerd