From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web08.7023.1634203069770685282 for ; Thu, 14 Oct 2021 02:17:55 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.88, mailfrom: chasel.chiu@intel.com) X-IronPort-AV: E=McAfee;i="6200,9189,10136"; a="251071795" X-IronPort-AV: E=Sophos;i="5.85,372,1624345200"; d="scan'208";a="251071795" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2021 02:17:54 -0700 X-IronPort-AV: E=Sophos;i="5.85,372,1624345200"; d="scan'208";a="491871829" Received: from cchiu4-mobl.gar.corp.intel.com ([10.252.188.134]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2021 02:17:53 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Sai Chaganty , Nate DeSimone , Heng Luo Subject: [edk2-platforms: PATCH v5 6/9] TigerlakeOpenBoardPkg: Use same variable name for FspNvsHob. Date: Thu, 14 Oct 2021 17:16:19 +0800 Message-Id: <20211014091622.2168-7-chasel.chiu@intel.com> X-Mailer: git-send-email 2.28.0.windows.1 In-Reply-To: <20211014091622.2168-1-chasel.chiu@intel.com> References: <20211014091622.2168-1-chasel.chiu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3678 To simplify the implementation the variable Name/GUID has been changed to "FspNvsBuffer" and gFspNvsBufferVariableGuid regardless it stores the data from FSP_NON_VOLATILE_STORAGE_HOB2 or FSP_NON_VOLATILE_STORAGE_HOB. Cc: Sai Chaganty Cc: Nate DeSimone Cc: Heng Luo Signed-off-by: Chasel Chiu Reviewed-by: Nate DeSimone Reviewed-by: Heng Luo --- Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLi= b/PeiFspPolicyInitLib.c | 21 ++++++++++++++++++--- Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLi= b/PeiFspPolicyInitLib.inf | 1 + 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFsp= PolicyInitLib/PeiFspPolicyInitLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/= FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c index fc523e93d1..938b74e5d8 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspPolicyInitLib.c +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspPolicyInitLib.c @@ -9,7 +9,9 @@ #include =0D #include =0D #include =0D +#include =0D #include =0D +#include =0D =0D VOID=0D EFIAPI=0D @@ -70,9 +72,11 @@ SiliconPolicyDonePreMem( )=0D {=0D EFI_STATUS Status;=0D + UINTN FspNvsBufferSize;=0D + VOID *FspNvsBufferPtr;=0D #if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0=0D - FSPM_ARCH_CONFIG_PPI *FspmArchConfigPpi;=0D - EFI_PEI_PPI_DESCRIPTOR *FspmArchConfigPpiDesc;=0D + FSPM_ARCH_CONFIG_PPI *FspmArchConfigPpi;=0D + EFI_PEI_PPI_DESCRIPTOR *FspmArchConfigPpiDesc;=0D =0D FspmArchConfigPpi =3D (FSPM_ARCH_CONFIG_PPI *) AllocateZeroPool (sizeof = (FSPM_ARCH_CONFIG_PPI));=0D if (FspmArchConfigPpi =3D=3D NULL) {=0D @@ -80,7 +84,6 @@ SiliconPolicyDonePreMem( return EFI_OUT_OF_RESOURCES;=0D }=0D FspmArchConfigPpi->Revision =3D 1;=0D - FspmArchConfigPpi->NvsBufferPtr =3D NULL;=0D FspmArchConfigPpi->BootLoaderTolumSize =3D 0;=0D =0D FspmArchConfigPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (s= izeof (EFI_PEI_PPI_DESCRIPTOR));=0D @@ -98,6 +101,18 @@ SiliconPolicyDonePreMem( ASSERT_EFI_ERROR (Status);=0D #endif=0D =0D + //=0D + // Initialize S3 Data variable (S3DataPtr). It may be used for warm and = fast boot paths.=0D + //=0D + FspNvsBufferPtr =3D NULL;=0D + FspNvsBufferSize =3D 0;=0D + Status =3D PeiGetLargeVariable (L"FspNvsBuffer", &gFspNvsBufferVariableG= uid, &FspNvsBufferPtr, &FspNvsBufferSize);=0D + if (Status =3D=3D EFI_SUCCESS) {=0D + DEBUG ((DEBUG_INFO, "Get L\"FspNvsBuffer\" gFspNvsBufferVariableGuid -= %r\n", Status));=0D + DEBUG ((DEBUG_INFO, "FspNvsBuffer Size - 0x%x\n", FspNvsBufferSize));= =0D + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmArchUpd.NvsBufferPtr, FspmA= rchConfigPpi->NvsBufferPtr, FspNvsBufferPtr);=0D + }=0D +=0D //=0D // Install Policy Ready PPI=0D // While installed, RC assumes the Policy is ready and finalized. So ple= ase=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFsp= PolicyInitLib/PeiFspPolicyInitLib.inf b/Platform/Intel/TigerlakeOpenBoardPk= g/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf index 708fbac08f..0236ae45ae 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspPolicyInitLib.inf +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspPolicyInitLib.inf @@ -181,3 +181,4 @@ gTianoLogoGuid ## CONSUMES=0D gCnviConfigGuid ## CONSUMES=0D gHdAudioPreMemConfigGuid ## CONSUMES=0D + gFspNvsBufferVariableGuid ## CONSUMES=0D --=20 2.28.0.windows.1