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X-Proofpoint-GUID: QYvmDVxJJBy-JXkIHN-O5_C5sccSc9YO X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-18_07,2021-10-18_01,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 mlxscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 phishscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109230001 definitions=main-2110190019 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain Cc: Daniel Schaefer Cc: Abner Chang Cc: Sunil V L Reviewed-by: Abner Chang Signed-off-by: Daniel Schaefer --- Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc = | 2 + Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf = | 6 + Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/U54= 0DeviceTree.inf | 25 ++ Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/gpi= o.h | 42 +++ Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/sif= ive-fu540-prci.h | 18 ++ Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree.fdf= .inc | 35 +++ Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/fu5= 40-c000.dtsi | 287 ++++++++++++++++++++ Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/hif= ive-unleashed-a00.dts | 106 ++++++++ Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc = | 8 +- 9 files changed, 526 insertions(+), 3 deletions(-) diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.d= sc index 2b00176c27a0..e971993b7b00 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc @@ -489,6 +489,8 @@ MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.in= f=0D MdeModulePkg/Universal/SerialDxe/SerialDxe.inf=0D =0D + Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/U= 540DeviceTree.inf=0D +=0D #=0D # SMBIOS Support=0D #=0D diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.fdf b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.f= df index 74717377287b..820e19d11334 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf @@ -33,6 +33,7 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|gUe= fiRiscVPlatformPkgToken FV =3D FVMAIN_COMPACT=0D =0D !include VarStore.fdf.inc=0D +!include DeviceTree.fdf.inc=0D =0D ##########################################################################= ######=0D =0D @@ -325,3 +326,8 @@ FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { RAW ACPI |.acpi=0D RAW ASL |.aml=0D }=0D +=0D +[Rule.Common.USER_DEFINED.DTB]=0D + FILE FREEFORM =3D $(NAMED_GUID) {=0D + RAW BIN |.dtb=0D + }=0D diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/De= viceTree/U540DeviceTree.inf b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFive= UnleashedBoard/DeviceTree/U540DeviceTree.inf new file mode 100644 index 000000000000..ebf0881c68bd --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTre= e/U540DeviceTree.inf @@ -0,0 +1,25 @@ +## @file=0D +#=0D +# Device tree description of the Hifive Unleashed platform=0D +#=0D +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001A=0D + BASE_NAME =3D U540DeviceTree=0D + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid=0D + MODULE_TYPE =3D USER_DEFINED=0D + VERSION_STRING =3D 1.0=0D +=0D +[Sources]=0D + gpio.h=0D + hifive-unleashed-a00.dts=0D + fu540-c000.dtsi=0D + sifive-fu540-prci.h=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/De= viceTree/gpio.h b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoa= rd/DeviceTree/gpio.h new file mode 100644 index 000000000000..c029467e828b --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTre= e/gpio.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for most GPIO bindings. + * + * Most GPIO bindings include a flags cell as part of the GPIO specifier. + * In most cases, the format of the flags cell uses the standard values + * defined in this header. + */ + +#ifndef _DT_BINDINGS_GPIO_GPIO_H +#define _DT_BINDINGS_GPIO_GPIO_H + +/* Bit 0 express polarity */ +#define GPIO_ACTIVE_HIGH 0 +#define GPIO_ACTIVE_LOW 1 + +/* Bit 1 express single-endedness */ +#define GPIO_PUSH_PULL 0 +#define GPIO_SINGLE_ENDED 2 + +/* Bit 2 express Open drain or open source */ +#define GPIO_LINE_OPEN_SOURCE 0 +#define GPIO_LINE_OPEN_DRAIN 4 + +/* + * Open Drain/Collector is the combination of single-ended open drain inte= rface. + * Open Source/Emitter is the combination of single-ended open source inte= rface. + */ +#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) +#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) + +/* Bit 3 express GPIO suspend/resume and reset persistence */ +#define GPIO_PERSISTENT 0 +#define GPIO_TRANSITORY 8 + +/* Bit 4 express pull up */ +#define GPIO_PULL_UP 16 + +/* Bit 5 express pull down */ +#define GPIO_PULL_DOWN 32 + +#endif diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/De= viceTree/sifive-fu540-prci.h b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiv= eUnleashedBoard/DeviceTree/sifive-fu540-prci.h new file mode 100644 index 000000000000..6a0b70a37d78 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTre= e/sifive-fu540-prci.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018-2019 SiFive, Inc. + * Wesley Terpstra + * Paul Walmsley + */ + +#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H +#define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H + +/* Clock indexes for use by Device Tree data and the PRCI driver */ + +#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_TLCLK 3 + +#endif diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/De= viceTree.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBo= ard/DeviceTree.fdf.inc new file mode 100644 index 000000000000..fb28be2767e7 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTre= e.fdf.inc @@ -0,0 +1,35 @@ +## @file=0D +# FDF include file with Layout Regions that define an empty variable stor= e.=0D +#=0D +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +# Copyright (C) 2014, Red Hat, Inc.=0D +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
= =0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +$(DTB_OFFSET)|$(DTB_SIZE)=0D +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase|gUefiRiscVPlatformPk= gTokenSpaceGuid.PcdRiscVDtbFvSize=0D +FV =3D DTBFV=0D +=0D +[FV.DTBFV]=0D +BlockSize =3D 0x1000=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +=0D +INF RuleOverride =3D DTB Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnle= ashedBoard/DeviceTree/U540DeviceTree.inf=0D diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/De= viceTree/fu540-c000.dtsi b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnl= eashedBoard/DeviceTree/fu540-c000.dtsi new file mode 100644 index 000000000000..e44b6f7c562e --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTre= e/fu540-c000.dtsi @@ -0,0 +1,287 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +/dts-v1/; + +/*#include */ +#include "sifive-fu540-prci.h" + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "sifive,fu540-c000", "sifive,fu540"; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + ethernet0 =3D ð0; + }; + + chosen { + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + cpu0: cpu@0 { + compatible =3D "sifive,e51", "sifive,rocket0", "riscv"; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <128>; + i-cache-size =3D <16384>; + reg =3D <0>; + riscv,isa =3D "rv64imac"; + status =3D "disabled"; + cpu0_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <1>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + next-level-cache =3D <&l2cache>; + cpu1_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <2>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + next-level-cache =3D <&l2cache>; + cpu2_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <3>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + next-level-cache =3D <&l2cache>; + cpu3_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <4>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + next-level-cache =3D <&l2cache>; + cpu4_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "sifive,fu540-c000", "sifive,fu540", "simple-bus"; + ranges; + plic0: interrupt-controller@c000000 { + #interrupt-cells =3D <1>; + compatible =3D "sifive,plic-1.0.0"; + reg =3D <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev =3D <53>; + interrupt-controller; + interrupts-extended =3D < + &cpu0_intc 0xffffffff + &cpu1_intc 0xffffffff &cpu1_intc 9 + &cpu2_intc 0xffffffff &cpu2_intc 9 + &cpu3_intc 0xffffffff &cpu3_intc 9 + &cpu4_intc 0xffffffff &cpu4_intc 9>; + }; + prci: clock-controller@10000000 { + compatible =3D "sifive,fu540-c000-prci"; + reg =3D <0x0 0x10000000 0x0 0x1000>; + clocks =3D <&hfclk>, <&rtcclk>; + #clock-cells =3D <1>; + }; + uart0: serial@10010000 { + compatible =3D "sifive,fu540-c000-uart", "sifive,uart0"; + reg =3D <0x0 0x10010000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <4>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + status =3D "disabled"; + }; + dma: dma@3000000 { + compatible =3D "sifive,fu540-c000-pdma"; + reg =3D <0x0 0x3000000 0x0 0x8000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <23 24 25 26 27 28 29 30>; + #dma-cells =3D <1>; + }; + uart1: serial@10011000 { + compatible =3D "sifive,fu540-c000-uart", "sifive,uart0"; + reg =3D <0x0 0x10011000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <5>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + status =3D "disabled"; + }; + i2c0: i2c@10030000 { + compatible =3D "sifive,fu540-c000-i2c", "sifive,i2c0"; + reg =3D <0x0 0x10030000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <50>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + reg-shift =3D <2>; + reg-io-width =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + qspi0: spi@10040000 { + compatible =3D "sifive,fu540-c000-spi", "sifive,spi0"; + reg =3D <0x0 0x10040000 0x0 0x1000 + 0x0 0x20000000 0x0 0x10000000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <51>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + qspi1: spi@10041000 { + compatible =3D "sifive,fu540-c000-spi", "sifive,spi0"; + reg =3D <0x0 0x10041000 0x0 0x1000 + 0x0 0x30000000 0x0 0x10000000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <52>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + qspi2: spi@10050000 { + compatible =3D "sifive,fu540-c000-spi", "sifive,spi0"; + reg =3D <0x0 0x10050000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <6>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + eth0: ethernet@10090000 { + compatible =3D "sifive,fu540-c000-gem"; + interrupt-parent =3D <&plic0>; + interrupts =3D <53>; + reg =3D <0x0 0x10090000 0x0 0x2000 + 0x0 0x100a0000 0x0 0x1000>; + local-mac-address =3D [00 00 00 00 00 00]; + clock-names =3D "pclk", "hclk"; + clocks =3D <&prci PRCI_CLK_GEMGXLPLL>, + <&prci PRCI_CLK_GEMGXLPLL>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + pwm0: pwm@10020000 { + compatible =3D "sifive,fu540-c000-pwm", "sifive,pwm0"; + reg =3D <0x0 0x10020000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <42 43 44 45>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + pwm1: pwm@10021000 { + compatible =3D "sifive,fu540-c000-pwm", "sifive,pwm0"; + reg =3D <0x0 0x10021000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <46 47 48 49>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + l2cache: cache-controller@2010000 { + compatible =3D "sifive,fu540-c000-ccache", "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <1024>; + cache-size =3D <2097152>; + cache-unified; + interrupt-parent =3D <&plic0>; + interrupts =3D <1 2 3>; + reg =3D <0x0 0x2010000 0x0 0x1000>; + }; + gpio: gpio@10060000 { + compatible =3D "sifive,fu540-c000-gpio", "sifive,gpio0"; + interrupt-parent =3D <&plic0>; + interrupts =3D <7>, <8>, <9>, <10>, <11>, <12>, <13>, + <14>, <15>, <16>, <17>, <18>, <19>, <20>, + <21>, <22>; + reg =3D <0x0 0x10060000 0x0 0x1000>; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + status =3D "disabled"; + }; + }; +}; diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/De= viceTree/hifive-unleashed-a00.dts b/Platform/SiFive/U5SeriesPkg/FreedomU540= HiFiveUnleashedBoard/DeviceTree/hifive-unleashed-a00.dts new file mode 100644 index 000000000000..df06f1c8c435 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTre= e/hifive-unleashed-a00.dts @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +#include "fu540-c000.dtsi" +/*#include */ +#include "gpio.h" + +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + model =3D "SiFive HiFive Unleashed A00"; + compatible =3D "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; + + chosen { + stdout-path =3D "serial0"; + }; + + cpus { + timebase-frequency =3D ; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x2 0x00000000>; + }; + + soc { + }; + + hfclk: hfclk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <33333333>; + clock-output-names =3D "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D ; + clock-output-names =3D "rtcclk"; + }; + gpio-restart { + compatible =3D "gpio-restart"; + gpios =3D <&gpio 10 GPIO_ACTIVE_LOW>; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; +}; + +&qspi0 { + status =3D "okay"; + flash@0 { + compatible =3D "issi,is25wp256", "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <50000000>; + m25p,fast-read; + spi-tx-bus-width =3D <4>; + spi-rx-bus-width =3D <4>; + }; +}; + +&qspi2 { + status =3D "okay"; + mmc@0 { + compatible =3D "mmc-spi-slot"; + reg =3D <0>; + spi-max-frequency =3D <20000000>; + voltage-ranges =3D <3300 3300>; + disable-wp; + }; +}; + +ð0 { + status =3D "okay"; + phy-mode =3D "gmii"; + phy-handle =3D <&phy0>; + phy0: ethernet-phy@0 { + reg =3D <0>; + }; +}; + +&pwm0 { + status =3D "okay"; +}; + +&pwm1 { + status =3D "okay"; +}; + +&gpio { + status =3D "okay"; +}; diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.fdf.inc index f72947da61af..723632dc792d 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.= inc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.= inc @@ -10,8 +10,8 @@ DEFINE BLOCK_SIZE =3D 0x1000=0D =0D DEFINE FW_BASE_ADDRESS =3D 0x80000000=0D -DEFINE FW_SIZE =3D 0x00800000=0D -DEFINE FW_BLOCKS =3D 0x800=0D +DEFINE FW_SIZE =3D 0x00820000=0D +DEFINE FW_BLOCKS =3D 0x820=0D =0D #=0D # 0x000000-0x7DFFFF code=0D @@ -32,13 +32,15 @@ DEFINE FVMAIN_OFFSET =3D 0x00100000 # Must be power= of 2 for PMP setting DEFINE FVMAIN_SIZE =3D 0x0018C000=0D DEFINE VARS_OFFSET =3D 0x007E0000=0D DEFINE VARS_SIZE =3D 0x00020000=0D +DEFINE DTB_OFFSET =3D 0x00800000=0D +DEFINE DTB_SIZE =3D 0x00002000=0D =0D SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress =3D $(FW_= BASE_ADDRESS) + $(VARS_OFFSET)=0D SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize =3D $(VAR= S_SIZE)=0D SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize =3D $(BLO= CK_SIZE)=0D =0D SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress =3D $(CODE_BAS= E_ADDRESS)=0D -SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress =3D $(CODE_BAS= E_ADDRESS) + $(SECFV_SIZE) + $(PEIFV_SIZE) + $(SCRATCH_SIZE)=0D +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress =3D $(CODE_BAS= E_ADDRESS) + $(SECFV_SIZE) + $(PEIFV_SIZE) + $(SCRATCH_SIZE) + $(DTB_SIZE)= =0D SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize =3D 8192=0D SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase =3D $(CODE_BAS= E_ADDRESS) + $(SCRATCH_OFFSET)=0D SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize =3D $(SCRATCH_= SIZE)=0D --=20 2.31.1