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Cc: Daniel Schaefer Cc: Abner Chang Cc: Sunil V L Reviewed-by: Abner Chang Signed-off-by: Daniel Schaefer --- Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 4 ++ Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf | 2 + Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h | 1 + Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c | 49 += +++++++++++++++++++ Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S | 22 -= -------- 5 files changed, 56 insertions(+), 22 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RI= SC-V/PlatformPkg/RiscVPlatformPkg.dec index 48aeb97431d7..ad15a155fe31 100644 --- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec +++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec @@ -31,6 +31,8 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize|0x0|UINT32|0x00001= 003=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|0x0|UINT32|0x00001= 004=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize|0x0|UINT32|0x00001= 005=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase|0x0|UINT32|0x00001= 016=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvSize|0x0|UINT32|0x00001= 017=0D =0D #=0D # Definition of EFI Variable region=0D @@ -66,6 +68,8 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize|0|UINT32|0x00001= 104=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPeiCorePrivilegeMode|0|UINT32|0x0= 0001105=0D =0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdDeviceTreeAddress|0|UINT32|0x0000= 1106=0D +=0D [PcdsPatchableInModule]=0D =0D [PcdsFeatureFlag]=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platfo= rm/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf index 89bcb039a6ab..78bd75e3ac11 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf @@ -57,6 +57,8 @@ [FixedPcd]=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdDeviceTreeAddress=0D =0D [Pcd]=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId=0D diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpen= sbi.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h index 2dab696af84d..e7ac6d26ee85 100644 --- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h +++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h @@ -47,6 +47,7 @@ typedef struct { =0D typedef struct {=0D VOID *PeiServiceTable; // PEI Service table=0D + UINT64 FlattenedDeviceTree; // Pointer to Flattened Device t= ree=0D EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_= SUPPORTED];=0D } EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;=0D =0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.c index fa9ecd789a57..0af0b4bac831 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c @@ -557,6 +557,12 @@ VOID EFIAPI PeiCore ( &FirmwareContext=0D ));=0D ThisSbiPlatform->firmware_context =3D (unsigned long)&FirmwareContext;=0D +=0D + //=0D + // Save Flattened Device tree in firmware context=0D + //=0D + FirmwareContext.FlattenedDeviceTree =3D FuncArg1;=0D +=0D //=0D // Set firmware context Hart-specific pointer=0D //=0D @@ -647,6 +653,42 @@ RiscVOpenSbiHartSwitchMode ( sbi_hart_switch_mode(FuncArg0, FuncArg1, NextAddr, NextMode, NextVirt);= =0D }=0D =0D +/**=0D + Get device tree address=0D +=0D + @retval The address of Device Tree binary.=0D +**/=0D +VOID *=0D +EFIAPI=0D +GetDeviceTreeAddress (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_COMMON_SECTION_HEADER *FoundSection;=0D +=0D + if (FixedPcdGet32 (PcdDeviceTreeAddress)) {=0D + return (VOID *)*((unsigned long *)FixedPcdGet32 (PcdDeviceTreeAddres= s));=0D + } else if (FixedPcdGet32 (PcdRiscVDtbFvBase)) {=0D + Status =3D FindFfsFileAndSection (=0D + (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32 (PcdRiscVDtbF= vBase),=0D + EFI_FV_FILETYPE_FREEFORM,=0D + EFI_SECTION_RAW,=0D + &FoundSection=0D + );=0D + if (EFI_ERROR(Status)) {=0D + DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found from FV.\n= "));=0D + return NULL;=0D + }=0D + FoundSection ++;=0D + return (VOID *)FoundSection;=0D + } else {=0D + DEBUG ((DEBUG_ERROR, "Must use DTB either from memory or compiled in= FW. PCDs configured incorrectly.\n"));=0D + ASSERT (FALSE);=0D + }=0D + return NULL;=0D +}=0D +=0D /**=0D This function initilizes hart specific information and SBI.=0D For the boot hart, it boots system through PEI core and initial SBI in t= he DXE IPL.=0D @@ -686,6 +728,13 @@ VOID EFIAPI SecCoreStartUpWithStack( UINT64 NonBootHartMessageLockValue;=0D EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartFirmwareContext;=0D =0D + Scratch->next_arg1 =3D (unsigned long)GetDeviceTreeAddress ();=0D + if (Scratch->next_arg1 =3D=3D (unsigned long)NULL) {=0D + DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n"));=0D + ASSERT (FALSE);=0D + }=0D + DEBUG ((DEBUG_INFO, "DTB address: 0x%08x\n", Scratch->next_arg1));=0D +=0D //=0D // Setup EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC for each hart.=0D //=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b= /Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S index 8434d1a4e0e9..0e3940180d44 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S @@ -75,11 +75,6 @@ _scratch_init: sd a4, SBI_SCRATCH_FW_START_OFFSET(tp)=0D sd a5, SBI_SCRATCH_FW_SIZE_OFFSET(tp)=0D =0D - /*=0D - * Note: fw_next_arg1() uses a0, a1, and ra=0D - */=0D - call fw_next_arg1=0D - sd a0, SBI_SCRATCH_NEXT_ARG1_OFFSET(tp) /* Save agr1 in scratch buffe= r*/=0D /*=0D Note: fw_next_addr()uses a0, a1, and ra=0D */=0D @@ -500,23 +495,6 @@ _reset_regs: csrw CSR_MSCRATCH, 0=0D ret=0D =0D - .align 3=0D - .section .entry, "ax", %progbits=0D - .global fw_prev_arg1=0D -fw_prev_arg1:=0D -=0D - /* We return previous arg1 in 'a0' */=0D - add a0, zero, zero=0D - ret=0D -=0D - .align 3=0D - .section .entry, "ax", %progbits=0D - .global fw_next_arg1=0D -fw_next_arg1:=0D - /* We return next arg1 in 'a0' */=0D - li a0, FixedPcdGet32(PcdRiscVPeiFvBase)=0D - ret=0D -=0D .align 3=0D .section .entry, "ax", %progbits=0D .global fw_next_addr=0D --=20 2.31.1