From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web08.7301.1634634494222951479 for ; Tue, 19 Oct 2021 02:08:22 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=GeVlDbn9; spf=temperror, err=temporary DNS error (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=0926d272d9=abner.chang@hpe.com) Received: from pps.filterd (m0150241.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J91tlS017699; Tue, 19 Oct 2021 09:08:12 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding; s=pps0720; bh=keqh65+x0Kz6y8JMrv7uxsglq76xmAkw0MESZuKua54=; b=GeVlDbn9njP/V/1F2JaQR5TILO5JljS/6CmbNd6clXaPg+GskBDTs1CVHR+zV3f4YhG/ IZSTWOgHcqj/VxbJp78ARTw8EQDO3nUBDIddJCSUuSqUR6As6oq7/rmyz1iU6Ox2XhqT ZxWvM6ZTi4qfiFyt0ujcK1UmA1y3h9UHlrZTF9Rs5HeTPreKh5KDieeYmozhm+qaaY55 FP6bcFgLGr7dVy1FgDkZ0m8UZR/JurTvba2+Mv/6Tu2vrofacxt0kWO6Afqb4mJN4SyC mp5REtNRqHG0MFP7/Y4E2re7sSUugWLAc5w3cmyAV1vgo4j89AZG6ygli6rpPS0G9TKK xw== Received: from g9t5008.houston.hpe.com (g9t5008.houston.hpe.com [15.241.48.72]) by mx0a-002e3701.pphosted.com with ESMTP id 3bs9b3qrun-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:12 +0000 Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g9t5008.houston.hpe.com (Postfix) with ESMTP id B4CF36F; Tue, 19 Oct 2021 09:08:11 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 8C3B94A; Tue, 19 Oct 2021 09:08:10 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Date: Tue, 19 Oct 2021 16:09:37 +0800 Message-Id: <20211019081007.31165-1-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Proofpoint-GUID: _wnUXKDhiSBBznSyJopYjKsTq673qsKt X-Proofpoint-ORIG-GUID: _wnUXKDhiSBBznSyJopYjKsTq673qsKt X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-18_07,2021-10-18_01,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 impostorscore=0 malwarescore=0 adultscore=0 mlxlogscore=919 mlxscore=0 bulkscore=0 spamscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109230001 definitions=main-2110190056 Content-Transfer-Encoding: 8bit This is the patch set to incorporate opensbi v0.9 with edk2 RISC-V port. There are many architecture changes to compliant with the RISC-V SBI implementation (opensbi) and also provide the flexibility to OEM platform. Below is the summary of major changes. You can also refer to patch (1/31) to understand the architecture design. - Flexibly support privilege modes for edk2 execution phases using PCD. - M-mode SEC then S-mode all the way to boot OS. - M-mode SEC and PEI, then S-mode for DXE to boot OS. - M-mode firmware all the way to S-mode OS. Default is M-mode SEC then S-mode all the way to boot OS. Still have to implemente priviledge mode switching for PEI to DXE and BDSto Boot OS. - Apply opensbi firmware domain solution to protect firmware regions using FDF/PCD. - Provide Platform SEC PPI library that can be executed in either M-mode or S-mode PEI phases according to OEM platform definition. - Determine boot hart using Device Tree or PCD. This allows OEM to flexibly select the desired HARTs for booting system. Non-boot HARTs can be used for other applications/purposes. - Provide an edk2 library wrapper of opensbi platform functions. This allows OEM to have procedures that hooks before or after the certain opensbi platform functions. - Other patches to adopt opensbi v0.9. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang Abner Chang (30): RISC-V/PlatformPkg: Update document RISC-V: Add RISC-V PeiCoreEntryPoint library RISC-V: Create opensbi firmware domains RISC-V: Use RISC-V PeiCoreEntryPoint library Platform/RISC-V: Add library to get PPI descriptor Platform/U540: Provide PlatormSecPpiLib Platform/RISC-V: Use PlatformSecPpiLib Platform/SiFive: CoreInfoHob uses RiscVFirmwareContextLib SiFive/U5SeriesPkg: Add CLINT to Device Tree Platform/RISC-V: Add NULL library instance of RiscVSpecialPlatformLib SiFive/U540: RiscVSpecialPlatformLib instance of U540 Platform/RISC-V: Remove platform dependency from this library Platform/RISC-V: Remove Null instance of OpensbilatformLibNull RiscVPlatformPkg/Sec: Initial hart_index2Id array RiscVPlatformPkg/OpensbiPlatformLib: Remove platform code RiscVPlatformPkg/U540: Only use four harts on U540 U5SeriesPkg/PeiCoreInfoHob: Remove hart count check RiscVPlatformPkg/RiscVSpecialPlatformLib: Rename module name RiscVPlatformPkg/U540: Add SortLib ProcessorPkg/opensbi: Update opensbi library RiscVPlatformPkg/Sec: Check Cold/Warm hart RiscVPlatformPkg/Sec: Add more comments to Secmain.c RiscV/ProcessorPkg: Create read mtime CSR library instances RiscV/ProcessorPkg: Use mtime CSR library Silicon/SiFive: Use mtime CSR library SiFive/SerialPortLib: Remove global variable RISC-V/PlatformPkg: Updates for the latest OpenSBI RiscVPlatformPkg/Sec: Separate EDK2 Opensbi platform hook. RISC-V/PlatformPkg: Determine hart number from DTB Silicon/RISC-V: Add PciCpuIoDxe driver .../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 52 +- .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 1 + .../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 20 +- .../FreedomU500VC707Board/U500.dsc | 1 + .../FreedomU540HiFiveUnleashedBoard/U540.dsc | 11 +- .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 3 + .../U540.fdf.inc | 94 +- .../VarStore.fdf.inc | 8 +- .../Edk2OpensbiPlatformWrapperLib.inf | 44 + .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 11 +- .../OpensbiPlatformLibNull.inf | 38 - .../PeiCoreEntryPoint/PeiCoreEntryPoint.inf | 37 + .../PlatformSecPpiLibNull.inf | 36 + .../RiscVSpecialPlatformLibNull.inf | 36 + .../PlatformPkg/Universal/Sec/SecMain.inf | 15 +- .../RiscVSpecialPlatformLib.inf | 36 + .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 3 +- .../PlatformSecPpiLib/PlatformSecPpiLib.inf | 43 + .../Universal/Dxe/TimerDxe/TimerDxe.inf | 1 + .../EmulatedMachineModeTimerLib.inf | 34 + .../MachineModeTimerLib.inf | 38 + .../RiscVTimerLib/BaseRiscVTimerLib.inf | 3 +- .../ProcessorPkg/Universal/CpuDxe/CpuDxe.inf | 1 + .../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 47 + .../Library/Edk2OpensbiPlatformWrapperLib.h | 16 + .../Include/Library/PlatformSecPpiLib.h | 24 + .../Include/Library/RiscVSpecialPlatformLib.h | 20 + .../OpensbiPlatformLib/PlatformOverride.h | 30 - .../PlatformPkg/Universal/Sec/SecMain.h | 28 +- .../SiFive/U5SeriesPkg/Include/SifiveU5Uart.h | 1 + .../Include/IndustryStandard/RiscV.h | 5 + .../Include/IndustryStandard/RiscVOpensbi.h | 8 +- .../Include/Library/RiscVCpuLib.h | 3 + .../Edk2OpensbiPlatformWrapperLib.c | 530 +++++ .../Library/OpensbiPlatformLib/Platform.c | 77 +- .../Library/OpensbiPlatformLibNull/Platform.c | 51 - .../PeiCoreEntryPoint/PeiCoreEntryPoint.c | 108 + .../PlatformSecPpiLibNull/PlatformSecPpiLib.c | 28 + .../RiscVSpecialPlatformLib.c | 20 + .../PlatformPkg/Universal/Sec/SecMain.c | 268 +-- .../RiscVSpecialPlatformLib}/SifiveFu540.c | 11 +- .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 9 +- .../PlatformSecPpiLib/PlatformSecPpiLib.c | 148 ++ .../Library/SerialIoLib/SerialPortLib.c | 58 +- .../Universal/Dxe/TimerDxe/Timer.c | 14 +- .../Library/RiscVTimerLib/RiscVTimerLib.c | 6 +- .../ProcessorPkg/Universal/CpuDxe/CpuDxe.c | 2 +- .../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 554 +++++ .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 6 +- Platform/RISC-V/PlatformPkg/Readme.md | 132 +- .../Documents/Media/RiscVEdk2BootProcess.svg | 1928 +++++++++++++++++ .../Documents/Media/RiscVEdk2FwDomain.svg | 1290 +++++++++++ .../PeiCoreEntryPoint/PeiCoreEntryPoint.uni | 14 + .../Universal/Sec/Riscv64/SecEntry.S | 372 ++-- .../DeviceTree/fu540-c000.dtsi | 591 ++--- .../Library/RiscVOpensbiLib/opensbi | 2 +- .../EmulatedMachineModeTimerLib.S | 24 + .../MachineModeTimerLib/MachineModeTimerLib.S | 25 + 58 files changed, 6105 insertions(+), 911 deletions(-) create mode 100644 Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf create mode 100644 Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf create mode 100644 Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.inf create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/Edk2OpensbiPlatformWrapperLib.h create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/PlatformSecPpiLib.h create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/RiscVSpecialPlatformLib.h delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/PlatformOverride.h create mode 100644 Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c create mode 100644 Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c rename Platform/{RISC-V/PlatformPkg/Library/OpensbiPlatformLib => SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/RiscVSpecialPlatformLib}/SifiveFu540.c (76%) create mode 100644 Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.c create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c create mode 100644 Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2BootProcess.svg create mode 100644 Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2FwDomain.svg create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.uni create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S -- 2.31.1