From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web08.7305.1634634505981371978 for ; Tue, 19 Oct 2021 02:08:26 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=RJNmN76e; spf=temperror, err=temporary DNS error (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=0926d272d9=abner.chang@hpe.com) Received: from pps.filterd (m0134422.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J86nB2022318; Tue, 19 Oct 2021 09:08:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=8UPF+vojhnFWSp4QdjXlZHRAtgubIBtQFdnHHOkDB6Q=; b=RJNmN76esfLgKA4AdCXuFquW6Z3E/0sb+8y3dY4XIkCDBeeCqKEXd3IOVgqaoa8gtS96 wA20qwHtgcIV4A8FCTZyXxJcN/AXFU/R09bFBZHpticLs7Duh7EKXAouWMxhfUWCCgw2 GYF3kjPYa/7V0yzK8bL8+mJ0IFl9VdngudTQ2uxxFv0oV2gT5Htw8Ma+v1fMhzSFz+zx 8u+KsMLPhGuZgB1bxXK3l1JBcw+D+TM52Rzc76Se458VYiLImrpfLJmYaXAObSvLWiV/ vvdeirIraCROMJn9KYE+8eKf65Tgu9jmwk7P//+/3+P+yOaGSmjDR8DSPdQEB/RSzOfQ EQ== Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 3bst7b8g68-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:25 +0000 Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id C4D5C62; Tue, 19 Oct 2021 09:08:24 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id B527648; Tue, 19 Oct 2021 09:08:23 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-platforms][PATCH 09/30] SiFive/U5SeriesPkg: Add CLINT to Device Tree Date: Tue, 19 Oct 2021 16:09:46 +0800 Message-Id: <20211019081007.31165-10-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: z7xr94y2J0tEsKNnYJ5sypUhcZ-cQynl X-Proofpoint-GUID: z7xr94y2J0tEsKNnYJ5sypUhcZ-cQynl X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-18_07,2021-10-18_01,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 malwarescore=0 phishscore=0 suspectscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 clxscore=1015 priorityscore=1501 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109230001 definitions=main-2110190056 Content-Transfer-Encoding: quoted-printable Add CLINT to Device Tree on U540 platform for M-mode timer and IPI. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang --- .../DeviceTree/fu540-c000.dtsi | 591 +++++++++--------- 1 file changed, 304 insertions(+), 287 deletions(-) diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/De= viceTree/fu540-c000.dtsi b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnl= eashedBoard/DeviceTree/fu540-c000.dtsi index e44b6f7c56..1d8518cfb7 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTre= e/fu540-c000.dtsi +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTre= e/fu540-c000.dtsi @@ -1,287 +1,304 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2018-2019 SiFive, Inc */ - -/dts-v1/; - -/*#include */ -#include "sifive-fu540-prci.h" - -/ { - #address-cells =3D <2>; - #size-cells =3D <2>; - compatible =3D "sifive,fu540-c000", "sifive,fu540"; - - aliases { - serial0 =3D &uart0; - serial1 =3D &uart1; - ethernet0 =3D ð0; - }; - - chosen { - }; - - cpus { - #address-cells =3D <1>; - #size-cells =3D <0>; - cpu0: cpu@0 { - compatible =3D "sifive,e51", "sifive,rocket0", "riscv"; - device_type =3D "cpu"; - i-cache-block-size =3D <64>; - i-cache-sets =3D <128>; - i-cache-size =3D <16384>; - reg =3D <0>; - riscv,isa =3D "rv64imac"; - status =3D "disabled"; - cpu0_intc: interrupt-controller { - #interrupt-cells =3D <1>; - compatible =3D "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu1: cpu@1 { - compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size =3D <64>; - d-cache-sets =3D <64>; - d-cache-size =3D <32768>; - d-tlb-sets =3D <1>; - d-tlb-size =3D <32>; - device_type =3D "cpu"; - i-cache-block-size =3D <64>; - i-cache-sets =3D <64>; - i-cache-size =3D <32768>; - i-tlb-sets =3D <1>; - i-tlb-size =3D <32>; - mmu-type =3D "riscv,sv39"; - reg =3D <1>; - riscv,isa =3D "rv64imafdc"; - tlb-split; - next-level-cache =3D <&l2cache>; - cpu1_intc: interrupt-controller { - #interrupt-cells =3D <1>; - compatible =3D "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu2: cpu@2 { - compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size =3D <64>; - d-cache-sets =3D <64>; - d-cache-size =3D <32768>; - d-tlb-sets =3D <1>; - d-tlb-size =3D <32>; - device_type =3D "cpu"; - i-cache-block-size =3D <64>; - i-cache-sets =3D <64>; - i-cache-size =3D <32768>; - i-tlb-sets =3D <1>; - i-tlb-size =3D <32>; - mmu-type =3D "riscv,sv39"; - reg =3D <2>; - riscv,isa =3D "rv64imafdc"; - tlb-split; - next-level-cache =3D <&l2cache>; - cpu2_intc: interrupt-controller { - #interrupt-cells =3D <1>; - compatible =3D "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu3: cpu@3 { - compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size =3D <64>; - d-cache-sets =3D <64>; - d-cache-size =3D <32768>; - d-tlb-sets =3D <1>; - d-tlb-size =3D <32>; - device_type =3D "cpu"; - i-cache-block-size =3D <64>; - i-cache-sets =3D <64>; - i-cache-size =3D <32768>; - i-tlb-sets =3D <1>; - i-tlb-size =3D <32>; - mmu-type =3D "riscv,sv39"; - reg =3D <3>; - riscv,isa =3D "rv64imafdc"; - tlb-split; - next-level-cache =3D <&l2cache>; - cpu3_intc: interrupt-controller { - #interrupt-cells =3D <1>; - compatible =3D "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu4: cpu@4 { - compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size =3D <64>; - d-cache-sets =3D <64>; - d-cache-size =3D <32768>; - d-tlb-sets =3D <1>; - d-tlb-size =3D <32>; - device_type =3D "cpu"; - i-cache-block-size =3D <64>; - i-cache-sets =3D <64>; - i-cache-size =3D <32768>; - i-tlb-sets =3D <1>; - i-tlb-size =3D <32>; - mmu-type =3D "riscv,sv39"; - reg =3D <4>; - riscv,isa =3D "rv64imafdc"; - tlb-split; - next-level-cache =3D <&l2cache>; - cpu4_intc: interrupt-controller { - #interrupt-cells =3D <1>; - compatible =3D "riscv,cpu-intc"; - interrupt-controller; - }; - }; - }; - soc { - #address-cells =3D <2>; - #size-cells =3D <2>; - compatible =3D "sifive,fu540-c000", "sifive,fu540", "simple-bus"; - ranges; - plic0: interrupt-controller@c000000 { - #interrupt-cells =3D <1>; - compatible =3D "sifive,plic-1.0.0"; - reg =3D <0x0 0xc000000 0x0 0x4000000>; - riscv,ndev =3D <53>; - interrupt-controller; - interrupts-extended =3D < - &cpu0_intc 0xffffffff - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - &cpu4_intc 0xffffffff &cpu4_intc 9>; - }; - prci: clock-controller@10000000 { - compatible =3D "sifive,fu540-c000-prci"; - reg =3D <0x0 0x10000000 0x0 0x1000>; - clocks =3D <&hfclk>, <&rtcclk>; - #clock-cells =3D <1>; - }; - uart0: serial@10010000 { - compatible =3D "sifive,fu540-c000-uart", "sifive,uart0"; - reg =3D <0x0 0x10010000 0x0 0x1000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <4>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - status =3D "disabled"; - }; - dma: dma@3000000 { - compatible =3D "sifive,fu540-c000-pdma"; - reg =3D <0x0 0x3000000 0x0 0x8000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <23 24 25 26 27 28 29 30>; - #dma-cells =3D <1>; - }; - uart1: serial@10011000 { - compatible =3D "sifive,fu540-c000-uart", "sifive,uart0"; - reg =3D <0x0 0x10011000 0x0 0x1000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <5>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - status =3D "disabled"; - }; - i2c0: i2c@10030000 { - compatible =3D "sifive,fu540-c000-i2c", "sifive,i2c0"; - reg =3D <0x0 0x10030000 0x0 0x1000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <50>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - reg-shift =3D <2>; - reg-io-width =3D <1>; - #address-cells =3D <1>; - #size-cells =3D <0>; - status =3D "disabled"; - }; - qspi0: spi@10040000 { - compatible =3D "sifive,fu540-c000-spi", "sifive,spi0"; - reg =3D <0x0 0x10040000 0x0 0x1000 - 0x0 0x20000000 0x0 0x10000000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <51>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - #address-cells =3D <1>; - #size-cells =3D <0>; - status =3D "disabled"; - }; - qspi1: spi@10041000 { - compatible =3D "sifive,fu540-c000-spi", "sifive,spi0"; - reg =3D <0x0 0x10041000 0x0 0x1000 - 0x0 0x30000000 0x0 0x10000000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <52>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - #address-cells =3D <1>; - #size-cells =3D <0>; - status =3D "disabled"; - }; - qspi2: spi@10050000 { - compatible =3D "sifive,fu540-c000-spi", "sifive,spi0"; - reg =3D <0x0 0x10050000 0x0 0x1000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <6>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - #address-cells =3D <1>; - #size-cells =3D <0>; - status =3D "disabled"; - }; - eth0: ethernet@10090000 { - compatible =3D "sifive,fu540-c000-gem"; - interrupt-parent =3D <&plic0>; - interrupts =3D <53>; - reg =3D <0x0 0x10090000 0x0 0x2000 - 0x0 0x100a0000 0x0 0x1000>; - local-mac-address =3D [00 00 00 00 00 00]; - clock-names =3D "pclk", "hclk"; - clocks =3D <&prci PRCI_CLK_GEMGXLPLL>, - <&prci PRCI_CLK_GEMGXLPLL>; - #address-cells =3D <1>; - #size-cells =3D <0>; - status =3D "disabled"; - }; - pwm0: pwm@10020000 { - compatible =3D "sifive,fu540-c000-pwm", "sifive,pwm0"; - reg =3D <0x0 0x10020000 0x0 0x1000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <42 43 44 45>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - #pwm-cells =3D <3>; - status =3D "disabled"; - }; - pwm1: pwm@10021000 { - compatible =3D "sifive,fu540-c000-pwm", "sifive,pwm0"; - reg =3D <0x0 0x10021000 0x0 0x1000>; - interrupt-parent =3D <&plic0>; - interrupts =3D <46 47 48 49>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - #pwm-cells =3D <3>; - status =3D "disabled"; - }; - l2cache: cache-controller@2010000 { - compatible =3D "sifive,fu540-c000-ccache", "cache"; - cache-block-size =3D <64>; - cache-level =3D <2>; - cache-sets =3D <1024>; - cache-size =3D <2097152>; - cache-unified; - interrupt-parent =3D <&plic0>; - interrupts =3D <1 2 3>; - reg =3D <0x0 0x2010000 0x0 0x1000>; - }; - gpio: gpio@10060000 { - compatible =3D "sifive,fu540-c000-gpio", "sifive,gpio0"; - interrupt-parent =3D <&plic0>; - interrupts =3D <7>, <8>, <9>, <10>, <11>, <12>, <13>, - <14>, <15>, <16>, <17>, <18>, <19>, <20>, - <21>, <22>; - reg =3D <0x0 0x10060000 0x0 0x1000>; - gpio-controller; - #gpio-cells =3D <2>; - interrupt-controller; - #interrupt-cells =3D <2>; - clocks =3D <&prci PRCI_CLK_TLCLK>; - status =3D "disabled"; - }; - }; -}; +// SPDX-License-Identifier: (GPL-2.0 OR MIT)=0D +/* Copyright (c) 2018-2019 SiFive, Inc */=0D +=0D +/dts-v1/;=0D +=0D +/**@file=0D + SiFive U540 platform Device Tree=0D +=0D + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "sifive-fu540-prci.h"=0D +=0D +/ {=0D + #address-cells =3D <2>;=0D + #size-cells =3D <2>;=0D + compatible =3D "sifive,fu540-c000", "sifive,fu540";=0D +=0D + aliases {=0D + serial0 =3D &uart0;=0D + serial1 =3D &uart1;=0D + ethernet0 =3D ð0;=0D + };=0D +=0D + chosen {=0D + };=0D +=0D + cpus {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + cpu0: cpu@0 {=0D + compatible =3D "sifive,e51", "sifive,rocket0", "ri= scv";=0D + device_type =3D "cpu";=0D + i-cache-block-size =3D <64>;=0D + i-cache-sets =3D <128>;=0D + i-cache-size =3D <16384>;=0D + reg =3D <0>;=0D + riscv,isa =3D "rv64imac";=0D + status =3D "disabled";=0D + cpu0_intc: interrupt-controller {=0D + #interrupt-cells =3D <1>;=0D + compatible =3D "riscv,cpu-intc";=0D + interrupt-controller;=0D + };=0D + };=0D + cpu1: cpu@1 {=0D + compatible =3D "sifive,u54-mc", "sifive,rocket0", = "riscv";=0D + d-cache-block-size =3D <64>;=0D + d-cache-sets =3D <64>;=0D + d-cache-size =3D <32768>;=0D + d-tlb-sets =3D <1>;=0D + d-tlb-size =3D <32>;=0D + device_type =3D "cpu";=0D + i-cache-block-size =3D <64>;=0D + i-cache-sets =3D <64>;=0D + i-cache-size =3D <32768>;=0D + i-tlb-sets =3D <1>;=0D + i-tlb-size =3D <32>;=0D + mmu-type =3D "riscv,sv39";=0D + reg =3D <1>;=0D + riscv,isa =3D "rv64imafdc";=0D + tlb-split;=0D + next-level-cache =3D <&l2cache>;=0D + cpu1_intc: interrupt-controller {=0D + #interrupt-cells =3D <1>;=0D + compatible =3D "riscv,cpu-intc";=0D + interrupt-controller;=0D + };=0D + };=0D + cpu2: cpu@2 {=0D + compatible =3D "sifive,u54-mc", "sifive,rocket0", = "riscv";=0D + d-cache-block-size =3D <64>;=0D + d-cache-sets =3D <64>;=0D + d-cache-size =3D <32768>;=0D + d-tlb-sets =3D <1>;=0D + d-tlb-size =3D <32>;=0D + device_type =3D "cpu";=0D + i-cache-block-size =3D <64>;=0D + i-cache-sets =3D <64>;=0D + i-cache-size =3D <32768>;=0D + i-tlb-sets =3D <1>;=0D + i-tlb-size =3D <32>;=0D + mmu-type =3D "riscv,sv39";=0D + reg =3D <2>;=0D + riscv,isa =3D "rv64imafdc";=0D + tlb-split;=0D + next-level-cache =3D <&l2cache>;=0D + cpu2_intc: interrupt-controller {=0D + #interrupt-cells =3D <1>;=0D + compatible =3D "riscv,cpu-intc";=0D + interrupt-controller;=0D + };=0D + };=0D + cpu3: cpu@3 {=0D + compatible =3D "sifive,u54-mc", "sifive,rocket0", = "riscv";=0D + d-cache-block-size =3D <64>;=0D + d-cache-sets =3D <64>;=0D + d-cache-size =3D <32768>;=0D + d-tlb-sets =3D <1>;=0D + d-tlb-size =3D <32>;=0D + device_type =3D "cpu";=0D + i-cache-block-size =3D <64>;=0D + i-cache-sets =3D <64>;=0D + i-cache-size =3D <32768>;=0D + i-tlb-sets =3D <1>;=0D + i-tlb-size =3D <32>;=0D + mmu-type =3D "riscv,sv39";=0D + reg =3D <3>;=0D + riscv,isa =3D "rv64imafdc";=0D + tlb-split;=0D + next-level-cache =3D <&l2cache>;=0D + cpu3_intc: interrupt-controller {=0D + #interrupt-cells =3D <1>;=0D + compatible =3D "riscv,cpu-intc";=0D + interrupt-controller;=0D + };=0D + };=0D + cpu4: cpu@4 {=0D + compatible =3D "sifive,u54-mc", "sifive,rocket0", = "riscv";=0D + d-cache-block-size =3D <64>;=0D + d-cache-sets =3D <64>;=0D + d-cache-size =3D <32768>;=0D + d-tlb-sets =3D <1>;=0D + d-tlb-size =3D <32>;=0D + device_type =3D "cpu";=0D + i-cache-block-size =3D <64>;=0D + i-cache-sets =3D <64>;=0D + i-cache-size =3D <32768>;=0D + i-tlb-sets =3D <1>;=0D + i-tlb-size =3D <32>;=0D + mmu-type =3D "riscv,sv39";=0D + reg =3D <4>;=0D + riscv,isa =3D "rv64imafdc";=0D + tlb-split;=0D + next-level-cache =3D <&l2cache>;=0D + cpu4_intc: interrupt-controller {=0D + #interrupt-cells =3D <1>;=0D + compatible =3D "riscv,cpu-intc";=0D + interrupt-controller;=0D + };=0D + };=0D + };=0D + soc {=0D + #address-cells =3D <2>;=0D + #size-cells =3D <2>;=0D + compatible =3D "sifive,fu540-c000", "sifive,fu540", "simpl= e-bus";=0D + ranges;=0D + plic0: interrupt-controller@c000000 {=0D + #interrupt-cells =3D <1>;=0D + compatible =3D "sifive,plic-1.0.0";=0D + reg =3D <0x0 0xc000000 0x0 0x4000000>;=0D + riscv,ndev =3D <53>;=0D + interrupt-controller;=0D + interrupts-extended =3D <=0D + &cpu0_intc 0xffffffff=0D + &cpu1_intc 0xffffffff &cpu1_intc 9=0D + &cpu2_intc 0xffffffff &cpu2_intc 9=0D + &cpu3_intc 0xffffffff &cpu3_intc 9=0D + &cpu4_intc 0xffffffff &cpu4_intc 9>;=0D + };=0D + prci: clock-controller@10000000 {=0D + compatible =3D "sifive,fu540-c000-prci";=0D + reg =3D <0x0 0x10000000 0x0 0x1000>;=0D + clocks =3D <&hfclk>, <&rtcclk>;=0D + #clock-cells =3D <1>;=0D + };=0D + uart0: serial@10010000 {=0D + compatible =3D "sifive,fu540-c000-uart", "sifive,u= art0";=0D + reg =3D <0x0 0x10010000 0x0 0x1000>;=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <4>;=0D + clocks =3D <&prci PRCI_CLK_TLCLK>;=0D + status =3D "disabled";=0D + };=0D + dma: dma@3000000 {=0D + compatible =3D "sifive,fu540-c000-pdma";=0D + reg =3D <0x0 0x3000000 0x0 0x8000>;=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <23 24 25 26 27 28 29 30>;=0D + #dma-cells =3D <1>;=0D + };=0D + uart1: serial@10011000 {=0D + compatible =3D "sifive,fu540-c000-uart", "sifive,u= art0";=0D + reg =3D <0x0 0x10011000 0x0 0x1000>;=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <5>;=0D + clocks =3D <&prci PRCI_CLK_TLCLK>;=0D + status =3D "disabled";=0D + };=0D + i2c0: i2c@10030000 {=0D + compatible =3D "sifive,fu540-c000-i2c", "sifive,i2= c0";=0D + reg =3D <0x0 0x10030000 0x0 0x1000>;=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <50>;=0D + clocks =3D <&prci PRCI_CLK_TLCLK>;=0D + reg-shift =3D <2>;=0D + reg-io-width =3D <1>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + status =3D "disabled";=0D + };=0D + qspi0: spi@10040000 {=0D + compatible =3D "sifive,fu540-c000-spi", "sifive,sp= i0";=0D + reg =3D <0x0 0x10040000 0x0 0x1000=0D + 0x0 0x20000000 0x0 0x10000000>;=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <51>;=0D + clocks =3D <&prci PRCI_CLK_TLCLK>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + status =3D "disabled";=0D + };=0D + qspi1: spi@10041000 {=0D + compatible =3D "sifive,fu540-c000-spi", "sifive,sp= i0";=0D + reg =3D <0x0 0x10041000 0x0 0x1000=0D + 0x0 0x30000000 0x0 0x10000000>;=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <52>;=0D + clocks =3D <&prci PRCI_CLK_TLCLK>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + status =3D "disabled";=0D + };=0D + qspi2: spi@10050000 {=0D + compatible =3D "sifive,fu540-c000-spi", "sifive,sp= i0";=0D + reg =3D <0x0 0x10050000 0x0 0x1000>;=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <6>;=0D + clocks =3D <&prci PRCI_CLK_TLCLK>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + status =3D "disabled";=0D + };=0D + eth0: ethernet@10090000 {=0D + compatible =3D "sifive,fu540-c000-gem";=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <53>;=0D + reg =3D <0x0 0x10090000 0x0 0x2000=0D + 0x0 0x100a0000 0x0 0x1000>;=0D + local-mac-address =3D [00 00 00 00 00 00];=0D + clock-names =3D "pclk", "hclk";=0D + clocks =3D <&prci PRCI_CLK_GEMGXLPLL>,=0D + <&prci PRCI_CLK_GEMGXLPLL>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + status =3D "disabled";=0D + };=0D + pwm0: pwm@10020000 {=0D + compatible =3D "sifive,fu540-c000-pwm", "sifive,pw= m0";=0D + reg =3D <0x0 0x10020000 0x0 0x1000>;=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <42 43 44 45>;=0D + clocks =3D <&prci PRCI_CLK_TLCLK>;=0D + #pwm-cells =3D <3>;=0D + status =3D "disabled";=0D + };=0D + pwm1: pwm@10021000 {=0D + compatible =3D "sifive,fu540-c000-pwm", "sifive,pw= m0";=0D + reg =3D <0x0 0x10021000 0x0 0x1000>;=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <46 47 48 49>;=0D + clocks =3D <&prci PRCI_CLK_TLCLK>;=0D + #pwm-cells =3D <3>;=0D + status =3D "disabled";=0D + };=0D + l2cache: cache-controller@2010000 {=0D + compatible =3D "sifive,fu540-c000-ccache", "cache"= ;=0D + cache-block-size =3D <64>;=0D + cache-level =3D <2>;=0D + cache-sets =3D <1024>;=0D + cache-size =3D <2097152>;=0D + cache-unified;=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <1 2 3>;=0D + reg =3D <0x0 0x2010000 0x0 0x1000>;=0D + };=0D + gpio: gpio@10060000 {=0D + compatible =3D "sifive,fu540-c000-gpio", "sifive,g= pio0";=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <7>, <8>, <9>, <10>, <11>, <12>, <1= 3>,=0D + <14>, <15>, <16>, <17>, <18>, <19>, <= 20>,=0D + <21>, <22>;=0D + reg =3D <0x0 0x10060000 0x0 0x1000>;=0D + gpio-controller;=0D + #gpio-cells =3D <2>;=0D + interrupt-controller;=0D + #interrupt-cells =3D <2>;=0D + clocks =3D <&prci PRCI_CLK_TLCLK>;=0D + status =3D "disabled";=0D + };=0D + clint: clint@2000000 {=0D + compatible =3D "riscv,clint0";=0D + interrupts-extended =3D <&cpu0_intc 3 &cpu0_intc 7=0D + &cpu1_intc 3 &cpu1_intc 7=0D + &cpu2_intc 3 &cpu2_intc 7=0D + &cpu3_intc 3 &cpu3_intc 7=0D + &cpu4_intc 3 &cpu4_intc 7>;=0D + reg =3D <0x0 0x2000000 0x0 0xc0000>;=0D + };=0D + };=0D +};=0D --=20 2.31.1