From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web11.7154.1634634514249341246 for ; Tue, 19 Oct 2021 02:08:38 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=DHRcP9D4; spf=temperror, err=temporary DNS error (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=0926d272d9=abner.chang@hpe.com) Received: from pps.filterd (m0134425.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J41xF6026456; Tue, 19 Oct 2021 09:08:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=v+e/Fsnhp8fOEuheKgY1fCZc8+JzzaWYigXAHQ/MgPE=; b=DHRcP9D4aIwzehOfy459H2rPwKlQ1AL7jAHorPhjjzj2WJSSotYcJCo4Us73jW9qVbWr Q8SFZA5Ivrdf3J8cs/SvAhrubsWaBYXoeMoXJnW0MNIux/aU4c6WCI8zo4u5T3iv1PJK VuG4bpvTj1iuDXs+0Hd3GSvep09KDWg3Rk7ZiNVyc1WIo7uuagvwdpOucisrFdW7e0ku LN628sE7PYkXV30slq/uCOyHje7LByZSbkfhkCHh7mRRbC62fRjh3LG0V2FcvzTj5Fbp Y6N0gHZBoU/mAEsuFhWrK1HT5arB81fOZhPjFR8JorhoU3Q3rG/1JCNlPK0SX/cjIo6C vg== Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 3bs9u4ygub-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:32 +0000 Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id BCCD75C; Tue, 19 Oct 2021 09:08:31 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id AF69451; Tue, 19 Oct 2021 09:08:30 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-platforms][PATCH 14/30] RiscVPlatformPkg/Sec: Initial hart_index2Id array Date: Tue, 19 Oct 2021 16:09:51 +0800 Message-Id: <20211019081007.31165-15-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 7VzD1J5C09Bxuv06ZbWq9k8Gt6xBN_UU X-Proofpoint-GUID: 7VzD1J5C09Bxuv06ZbWq9k8Gt6xBN_UU X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-18_07,2021-10-18_01,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 impostorscore=0 suspectscore=0 clxscore=1015 bulkscore=0 mlxlogscore=999 mlxscore=0 adultscore=0 priorityscore=1501 spamscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109230001 definitions=main-2110190056 Content-Transfer-Encoding: quoted-printable Initial hart index to Id array by invoking OpenSBI fw_platform_init function. Introduce PcdBootableHartIndexToId PCD which could be used to overwrite the hart_index2Id arrary built from Devie tree according to platform demand. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang --- .../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 13 +++- .../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 3 +- .../PlatformPkg/Universal/Sec/SecMain.inf | 2 + .../PlatformPkg/Universal/Sec/SecMain.c | 62 ++++++++++++++++--- .../Universal/Sec/Riscv64/SecEntry.S | 29 ++++++++- 5 files changed, 96 insertions(+), 13 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RI= SC-V/PlatformPkg/RiscVPlatformPkg.dec index 7e41e7bdb2..947ae40e20 100644 --- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec +++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec @@ -55,10 +55,21 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001083=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001084=0D #=0D -# The bootable hart core number, which is incorporate with OpenSBI platfor= m hart_index2id value.=0D +# The bootable hart core number, which incorporates with OpenSBI platform = hart_index2id value.=0D +# PcdBootableHartNumber =3D 0 means the number of bootable hart comes from= Device Tree.=0D +# Otherwise the number assigned in PcdBootableHartNumber overwrite it.=0D #=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber|0|UINT32|0x000= 01085=0D #=0D +# PcdBootableHartIndexToId is valid if PcdBootableHartNumber !=3D 0.=0D +# If PcdBootableHartNumber !=3D 0, then PcdBootableHartIndexToId is an arr= ay of=0D +# bootable hart ID.=0D +# For example,=0D +# if PcdBootableHartNumber =3D=3D 3 then PcdBootableHartIndexToId could be= defined=0D +# as {0x1, 0x2, 0x3}.=0D +#=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId|NULL|VOID*|= 0x00001086=0D +#=0D # Definitions for OpenSbi=0D #=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase|0|UINT32|0x0000110= 0=0D diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RI= SC-V/PlatformPkg/RiscVPlatformPkg.dsc index 93b3cd8de9..97d5dd08a0 100644 --- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc +++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc @@ -39,7 +39,8 @@ !include MdePkg/MdeLibs.dsc.inc=0D =0D [LibraryClasses.common]=0D - RiscVOpensbiPlatformLib|Platform/RISC-V/PlatformPkg/Library/OpensbiPlatf= ormLibNull/OpensbiPlatformLibNull.inf=0D + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf=0D + RiscVOpensbiPlatformLib|Platform/RISC-V/PlatformPkg/Library/OpensbiPlatf= ormLib/OpensbiPlatformLib.inf=0D RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.= inf=0D RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/Risc= VEdk2SbiLib.inf=0D RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/Risc= VOpensbiLib.inf=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platfo= rm/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf index 9736277fa1..1cfbef961f 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf @@ -41,6 +41,7 @@ DebugAgentLib=0D DebugLib=0D ExtractGuidedSectionLib=0D + FdtLib=0D IoLib=0D PcdLib=0D PeCoffLib=0D @@ -62,6 +63,7 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.c index fb0adbca54..51d9edfe75 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c @@ -615,16 +615,17 @@ GetDeviceTreeAddress ( EFI_COMMON_SECTION_HEADER *FoundSection;=0D =0D if (FixedPcdGet32 (PcdDeviceTreeAddress)) {=0D + DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddr= ess.\n"));=0D return (VOID *)*((unsigned long *)FixedPcdGet32 (PcdDeviceTreeAddres= s));=0D } else if (FixedPcdGet32 (PcdRiscVDtbFvBase)) {=0D + DEBUG ((DEBUG_INFO, "Use DBT FV\n"));=0D Status =3D FindFfsFileAndSection (=0D (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32 (PcdRiscVDtbF= vBase),=0D EFI_FV_FILETYPE_FREEFORM,=0D EFI_SECTION_RAW,=0D &FoundSection=0D - );=0D + );=0D if (EFI_ERROR(Status)) {=0D - DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found from FV.\n= "));=0D return NULL;=0D }=0D FoundSection ++;=0D @@ -635,6 +636,35 @@ GetDeviceTreeAddress ( }=0D return NULL;=0D }=0D +/**=0D + Overwrite hart_index2id array if platform would like to use the=0D + bootable harts other than those declared in Device Tree=0D +=0D + @param[in] SbiPlatform Pointer to SBI platform=0D + @retval hart_index2id Index to ID value may be overwrote.=0D + @retval hart_count Index to ID value may be overwrote.=0D +=0D +**/=0D +VOID=0D +Edk2PlatformHartIndex2Id (=0D + IN struct sbi_platform *SbiPlatform=0D + )=0D +{=0D + UINT32 Index;=0D + UINT32 *HartIndexToId;=0D + UINT32 BootableHartCount;=0D + UINT8 *PlatformHartIndex2IdArray;=0D +=0D + BootableHartCount =3D FixedPcdGet32(PcdBootableHartNumber);=0D + if (BootableHartCount !=3D 0) {=0D + HartIndexToId =3D (UINT32 *)SbiPlatform->hart_index2id;=0D + PlatformHartIndex2IdArray =3D (UINT8 *)FixedPcdGetPtr (PcdBootableHart= IndexToId);=0D + for (Index =3D 0; Index < BootableHartCount; Index++) {=0D + *(HartIndexToId + Index) =3D (UINT32)(*(PlatformHartIndex2IdArray + = Index));=0D + }=0D + SbiPlatform->hart_count =3D BootableHartCount;=0D + }=0D +}=0D =0D /**=0D This function initilizes hart specific information and SBI.=0D @@ -671,17 +701,13 @@ VOID EFIAPI SecCoreStartUpWithStack( IN struct sbi_scratch *Scratch=0D )=0D {=0D + UINT32 HardIndex;=0D UINT64 BootHartDoneSbiInit;=0D UINT64 NonBootHartMessageLockValue;=0D struct sbi_platform *ThisSbiPlatform;=0D EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartFirmwareContext;=0D =0D - Scratch->next_arg1 =3D (unsigned long)GetDeviceTreeAddress ();=0D - if (Scratch->next_arg1 =3D=3D (unsigned long)NULL) {=0D - DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n"));=0D - ASSERT (FALSE);=0D - }=0D - DEBUG ((DEBUG_INFO, "DTB address: 0x%08x\n", Scratch->next_arg1));=0D + DEBUG ((DEBUG_INFO, "HART ID: 0x%x enter SecCoreStartUpWithStack\n", Har= tId));=0D =0D //=0D // Setup EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC for each hart.=0D @@ -705,6 +731,18 @@ VOID EFIAPI SecCoreStartUpWithStack( ThisSbiPlatform->platform_ops_addr =3D (unsigned long)&Edk2OpensbiPlatfo= rmOps;=0D =0D if (HartId =3D=3D FixedPcdGet32(PcdBootHartId)) {=0D +=0D + Scratch->next_arg1 =3D (unsigned long)GetDeviceTreeAddress ();=0D + if (Scratch->next_arg1 =3D=3D (unsigned long)NULL) {=0D + DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n"));=0D + ASSERT (FALSE);=0D + }=0D +=0D + DEBUG ((DEBUG_INFO, "HART number: 0x%x\n", ThisSbiPlatform->hart_count= ));=0D + DEBUG ((DEBUG_INFO, "HART index to HART ID:\n"));=0D + for (HardIndex =3D 0; HardIndex < ThisSbiPlatform->hart_count; HardInd= ex ++) {=0D + DEBUG ((DEBUG_INFO, " Index: %d -> Hard ID: %x\n", HardIndex, ThisS= biPlatform->hart_index2id [HardIndex]));=0D + }=0D LaunchPeiCore (HartId, Scratch);=0D }=0D =0D @@ -739,3 +777,11 @@ VOID EFIAPI SecCoreStartUpWithStack( sbi_init(Scratch);=0D }=0D =0D +void xxxx (char *debugstr, ...)=0D +{=0D + VA_LIST Marker;=0D +=0D + VA_START (Marker, debugstr);=0D + DebugVPrint (DEBUG_INFO, debugstr, Marker);=0D + VA_END (Marker);=0D +}=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b= /Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S index 0a69c50065..dc410703e0 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S @@ -101,16 +101,35 @@ _scratch_init: /* Loop to next hart */=0D blt t1, s7, _scratch_init=0D =0D - /* Fill-out temporary memory with 55aa*/=0D + li a4, FixedPcdGet32 (PcdTemporaryRamBase)=0D + li a5, FixedPcdGet32 (PcdTemporaryRamSize)=0D +=0D + /* Use Temp memory as the stack for calling to C code */=0D + add sp, a4, a5=0D + /* Get the address of device tree and call generic fw_platform_init */=0D + call GetDeviceTreeAddress /* a0 return the device tree address */=0D + beqz a0, skip_fw_init=0D + add a1, a0, 0 /* a1 is device tree */=0D + csrr a0, CSR_MHARTID /* a0 is hart ID */=0D + call fw_platform_init=0D +skip_fw_init:=0D +=0D + /* Zero out temporary memory */=0D li a4, FixedPcdGet32 (PcdTemporaryRamBase)=0D li a5, FixedPcdGet32 (PcdTemporaryRamSize)=0D add a5, a4, a5=0D 1:=0D - li a3, 0x5AA55AA55AA55AA5=0D + li a3, 0x0=0D sd a3, (a4)=0D add a4, a4, __SIZEOF_POINTER__=0D blt a4, a5, 1b=0D =0D + /* Overwrite hart_index2id array of=0D + platform would like to use the bootable hart=0D + other than it defined in Device Tree */=0D + la a0, platform=0D + call Edk2PlatformHartIndex2Id=0D +=0D /* Update boot hart flag */=0D la a4, _boot_hart_done=0D li a5, 1=0D @@ -136,6 +155,10 @@ _start_warm: csrw CSR_MIP, zero=0D =0D li s7, FixedPcdGet32 (PcdBootableHartNumber)=0D + bnez s7, 1f=0D + la a4, platform=0D + REG_L s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)=0D +1:=0D li s8, FixedPcdGet32 (PcdOpenSbiStackSize)=0D la a4, platform=0D =0D @@ -205,7 +228,7 @@ _start_warm: /* Setup stack */=0D add sp, tp, zero=0D =0D - /* Setup stack for the Hart executing EFI to top of temporary ram*/=0D + /* Setup stack for the boot hart executing EFI to top of temporary ram*/= =0D csrr a6, CSR_MHARTID=0D li a5, FixedPcdGet32 (PcdBootHartId)=0D bne a6, a5, 1f=0D --=20 2.31.1