public inbox for devel@edk2.groups.io
 help / color / mirror / Atom feed
From: "Abner Chang" <abner.chang@hpe.com>
To: devel@edk2.groups.io
Cc: abner.chang@hpe.com, Sunil V L <sunilvl@ventanamicro.com>,
	Daniel Schaefer <daniel.schaefer@hpe.com>
Subject: [edk2-platforms][PATCH 16/30] RiscVPlatformPkg/U540: Only use four harts on U540
Date: Tue, 19 Oct 2021 16:09:53 +0800	[thread overview]
Message-ID: <20211019081007.31165-17-abner.chang@hpe.com> (raw)
In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com>

Only use four harts on U540 reference code. This
overwrites the bootable harts declared in Device Tree.

Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>

Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
 .../FreedomU540HiFiveUnleashedBoard/U540.fdf.inc    | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
index f708f4d8be..1a525dc874 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
@@ -92,9 +92,16 @@ SET gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz    = 1000000
 SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock = 1000000000 # 1GHz system clock
 SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount                   = 5          # Total cores on U540 platform
 SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId                  = 1          # Boot hart ID
-SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber          = 4          # The bootable hart core number.
-                                                                                    # Which is incorporate with OpenSBI
-                                                                                    # platform hart_index2id value.
+
+#
+# The bootable hart number the platform would like to use during boot.
+#
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber          = 4
+#
+# Only use hart ID 1, 2, 3, 4
+#
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId       = {0x1,0x2,0x3,0x4}
+                                                                                    # during boot
 SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdNumberofU5Cores       = 4          # Total U5 cores enabled on U540 platform
 SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdE5MCSupported         = True       # E51 MC exists.
 SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase            = 0x10010000 # Serial port base address
-- 
2.31.1


  parent reply	other threads:[~2021-10-19  9:08 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-19  8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
2021-10-19  8:09 ` [edk2-platforms][PATCH 01/30] RISC-V/PlatformPkg: Update document Abner Chang
2021-10-19  8:09 ` [edk2-platforms][PATCH 02/30] RISC-V: Add RISC-V PeiCoreEntryPoint library Abner Chang
2021-10-19  8:09 ` [edk2-platforms][PATCH 03/30] RISC-V: Create opensbi firmware domains Abner Chang
2021-10-19  8:09 ` [edk2-platforms][PATCH 04/30] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
2021-10-19  8:09 ` [edk2-platforms][PATCH 05/30] Platform/RISC-V: Add library to get PPI descriptor Abner Chang
2021-10-19  8:09 ` [edk2-platforms][PATCH 06/30] Platform/U540: Provide PlatormSecPpiLib Abner Chang
2021-10-19  8:09 ` [edk2-platforms][PATCH 07/30] Platform/RISC-V: Use PlatformSecPpiLib Abner Chang
2021-10-19  8:09 ` [edk2-platforms][PATCH 08/30] Platform/SiFive: CoreInfoHob uses RiscVFirmwareContextLib Abner Chang
2021-10-19  8:09 ` [edk2-platforms][PATCH 09/30] SiFive/U5SeriesPkg: Add CLINT to Device Tree Abner Chang
2021-10-19  8:09 ` [edk2-platforms][PATCH 10/30] Platform/RISC-V: Add NULL library instance of RiscVSpecialPlatformLib Abner Chang
2021-10-19  8:09 ` [edk2-platforms][PATCH 11/30] SiFive/U540: RiscVSpecialPlatformLib instance of U540 Abner Chang
2021-10-19  8:09 ` [edk2-platforms][PATCH 12/30] Platform/RISC-V: Remove platform dependency from this library Abner Chang
2021-10-19  8:09 ` [edk2-platforms][PATCH 13/30] Platform/RISC-V: Remove Null instance of OpensbilatformLibNull Abner Chang
2021-10-19  8:09 ` [edk2-platforms][PATCH 14/30] RiscVPlatformPkg/Sec: Initial hart_index2Id array Abner Chang
2021-10-19  8:09 ` [edk2-platforms][PATCH 15/30] RiscVPlatformPkg/OpensbiPlatformLib: Remove platform code Abner Chang
2021-10-19  8:09 ` Abner Chang [this message]
2021-10-19  8:09 ` [edk2-platforms][PATCH 17/30] U5SeriesPkg/PeiCoreInfoHob: Remove hart count check Abner Chang
2021-10-19  8:09 ` [edk2-platforms][PATCH 18/30] RiscVPlatformPkg/RiscVSpecialPlatformLib: Rename module name Abner Chang
2021-10-19  8:09 ` [edk2-platforms][PATCH 19/30] RiscVPlatformPkg/U540: Add SortLib Abner Chang
2021-10-19  8:09 ` [edk2-platforms][PATCH 20/30] ProcessorPkg/opensbi: Update opensbi library Abner Chang
2021-10-19  8:09 ` [edk2-platforms][PATCH 21/30] RiscVPlatformPkg/Sec: Check Cold/Warm hart Abner Chang
2021-10-19  8:09 ` [edk2-platforms][PATCH 22/30] RiscVPlatformPkg/Sec: Add more comments to Secmain.c Abner Chang
2021-10-19  8:10 ` [edk2-platforms][PATCH 23/30] RiscV/ProcessorPkg: Create read mtime CSR library instances Abner Chang
2021-10-19  8:10 ` [edk2-platforms][PATCH 24/30] RiscV/ProcessorPkg: Use mtime CSR library Abner Chang
2021-10-19  8:10 ` [edk2-platforms][PATCH 25/30] Silicon/SiFive: " Abner Chang
2021-10-19  8:10 ` [edk2-platforms][PATCH 26/30] SiFive/SerialPortLib: Remove global variable Abner Chang
2021-10-19  8:10 ` [edk2-platforms][PATCH 27/30] RISC-V/PlatformPkg: Updates for the latest OpenSBI Abner Chang
2021-10-19  8:10 ` [edk2-platforms][PATCH 28/30] RiscVPlatformPkg/Sec: Separate EDK2 Opensbi platform hook Abner Chang
2021-10-19  8:10 ` [edk2-platforms][PATCH 29/30] RISC-V/PlatformPkg: Determine hart number from DTB Abner Chang
2021-10-19  8:10 ` [edk2-platforms][PATCH 30/30] Silicon/RISC-V: Add PciCpuIoDxe driver Abner Chang
2021-11-09  4:26 ` [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Daniel Schaefer
2021-11-09 10:06 ` Sunil V L

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-list from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20211019081007.31165-17-abner.chang@hpe.com \
    --to=devel@edk2.groups.io \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox