From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web12.7281.1634634528484674495 for ; Tue, 19 Oct 2021 02:08:49 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=plB8TROP; spf=temperror, err=temporary DNS error (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=0926d272d9=abner.chang@hpe.com) Received: from pps.filterd (m0150241.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J81swW005268; Tue, 19 Oct 2021 09:08:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=hrPyw0P33hVk2040ZZPWKo2fPRlVg4A5vV5+Qn1kSoo=; b=plB8TROPVrZdh7HDJKVM2VtSNt0TJ2+8ZM5/Lr7bn197O6/+k+t2ZXZeZTHnGpzOGw9G ecwHRehGaATvgGd9KY52xiJC6yAHoq/sZMIHytbqM7Bd1urdh+4QcdcXPbyVgqVetV2M znvocQLG7NLstyxcxd1DlT9VhyC7hCwt7jFdYD35XPzDRmUXO0CBZcHAwGB9C5+M1/2R lKNQFgWx6sEmr2eJaegw8fx1j4QPK8qib5yExsPVytGskDBEMwtblW6db44ixcExkRFB Y4NcVwNxwIa9sfHNqBP37rJxY+OvFaKlptbMMegEgJS4v4cyiC7UDPRDLBdjymkf0gb3 xA== Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0a-002e3701.pphosted.com with ESMTP id 3bs9b3qs0g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:48 +0000 Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id 4569EB4; Tue, 19 Oct 2021 09:08:47 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 33C0248; Tue, 19 Oct 2021 09:08:46 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-platforms][PATCH 25/30] Silicon/SiFive: Use mtime CSR library Date: Tue, 19 Oct 2021 16:10:02 +0800 Message-Id: <20211019081007.31165-26-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: pArvweNFQOkZj9pTZJ8yJlAJKH0lnTc8 X-Proofpoint-ORIG-GUID: pArvweNFQOkZj9pTZJ8yJlAJKH0lnTc8 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-18_07,2021-10-18_01,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 impostorscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 mlxscore=0 bulkscore=0 spamscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109230001 definitions=main-2110190056 Content-Transfer-Encoding: quoted-printable Use mtime CSR library interface to access mtime CSR in Timer DXE driver. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang --- .../FreedomU540HiFiveUnleashedBoard/U540.dsc | 2 ++ .../Universal/Dxe/TimerDxe/TimerDxe.inf | 1 + .../U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c | 14 +++++--------- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.d= sc index 4d16adfc82..c29b36e9bb 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc @@ -148,6 +148,8 @@ RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.= inf=0D RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/Risc= VEdk2SbiLib.inf=0D RiscVPlatformTimerLib|Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformT= imerLib/RiscVPlatformTimerLib.inf=0D + #MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachin= eModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf=0D + MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachine= ModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf=0D CpuExceptionHandlerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptio= nLib/CpuExceptionHandlerDxeLib.inf=0D =0D =0D diff --git a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.in= f b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf index 25cb3bb8b4..4571621a2e 100644 --- a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf +++ b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf @@ -30,6 +30,7 @@ BaseLib=0D DebugLib=0D IoLib=0D + MachineModeTimerLib=0D RiscVCpuLib=0D RiscVEdk2SbiLib=0D UefiBootServicesTableLib=0D diff --git a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c b/P= latform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c index 065ecdda86..deb5799277 100644 --- a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c +++ b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c @@ -15,9 +15,6 @@ #include =0D #include =0D =0D -STATIC volatile VOID * const p_mtime =3D (VOID *)CLINT_REG_MTIME;=0D -#define MTIME (*p_mtime)=0D -#define MTIMECMP(i) (p_mtimecmp[i])=0D BOOLEAN TimerHandlerReentry =3D FALSE;=0D =0D //=0D @@ -73,7 +70,7 @@ TimerInterruptHandler ( // MMode timer occurred when processing=0D // SMode timer handler.=0D //=0D - RiscvTimer =3D readq_relaxed(p_mtime);=0D + RiscvTimer =3D RiscVReadMachineTimerInterface();=0D SbiSetTimer (RiscvTimer +=3D mTimerPeriod);=0D csr_clear(CSR_SIP, MIP_STIP);=0D return;=0D @@ -91,7 +88,7 @@ TimerInterruptHandler ( if (mTimerNotifyFunction !=3D NULL) {=0D mTimerNotifyFunction (mTimerPeriod);=0D }=0D - RiscvTimer =3D readq_relaxed(p_mtime);=0D + RiscvTimer =3D RiscVReadMachineTimerInterface();=0D SbiSetTimer (RiscvTimer +=3D mTimerPeriod);=0D gBS->RestoreTPL (OriginalTPL);=0D csr_set(CSR_SIE, MIP_STIP); // enable SMode timer int=0D @@ -185,10 +182,9 @@ TimerDriverSetTimerPeriod ( return EFI_SUCCESS;=0D }=0D =0D - mTimerPeriod =3D TimerPeriod / 10; // convert unit from 100ns to 1us=0D -=0D - RiscvTimer =3D readq_relaxed(p_mtime);=0D - SbiSetTimer(RiscvTimer + mTimerPeriod);=0D + mTimerPeriod =3D TimerPeriod; // convert unit from 100ns to 1us=0D + RiscvTimer =3D RiscVReadMachineTimerInterface();=0D + SbiSetTimer(RiscvTimer + mTimerPeriod / 10);=0D =0D mCpu->EnableInterrupt(mCpu);=0D csr_set(CSR_SIE, MIP_STIP); // enable timer int=0D --=20 2.31.1