From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web09.7334.1634634531212199292 for ; Tue, 19 Oct 2021 02:08:52 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=YCkOxkE6; spf=temperror, err=temporary DNS error (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=0926d272d9=abner.chang@hpe.com) Received: from pps.filterd (m0134421.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J7Wc19031246; Tue, 19 Oct 2021 09:08:51 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=0hWAjCTdr4oFWPu5I2nxnYdUqm/mqnP3vx2fr5sgPVs=; b=YCkOxkE6Je2u19+AR5h3AHaBJcMD+UbLzi7qYSiujU4/iqfO1WNw9CzM5FQRs6RUvLvL ChxuDati1kvWTrUzIdxPhCJwaBYAyU4aloztAGc1N6uMk9WFsRILkp10epL++jBIFbzI 2bspftXW/jb0PIGpkyczzOzmOWZCbA3keuKVeiTZR0EcbTroVQ07H4BkLgXjVij/JF8z Hs9KJxSL/oRdbUYJdLbh2wdI+m0eDChtidendSeD/UABI5k6FcA0AcPA4YtiMde/9lU+ gAB3bbovil+GZbb4Ctqk8GTnlfNf6+xx0PwRhDRcnJWUd7mn4afF90eeNNdwM2g/bsO5 Ng== Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0b-002e3701.pphosted.com with ESMTP id 3bsd6x5gve-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:50 +0000 Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id 13EFA9A; Tue, 19 Oct 2021 09:08:50 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id 050B756; Tue, 19 Oct 2021 09:08:48 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-platforms][PATCH 27/30] RISC-V/PlatformPkg: Updates for the latest OpenSBI Date: Tue, 19 Oct 2021 16:10:04 +0800 Message-Id: <20211019081007.31165-28-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: yIEZoIrQHjhOwmeDXrSLo7XJb6H197TK X-Proofpoint-ORIG-GUID: yIEZoIrQHjhOwmeDXrSLo7XJb6H197TK X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-18_07,2021-10-18_01,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 spamscore=0 suspectscore=0 bulkscore=0 phishscore=0 clxscore=1015 mlxlogscore=999 malwarescore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109230001 definitions=main-2110190056 Content-Transfer-Encoding: quoted-printable Code changes to incorporate with OpenSBI commit ID: a731c7e36988c3308e1978ecde491f2f6182d490 Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang --- .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 10 +- .../PlatformPkg/Universal/Sec/SecMain.inf | 4 + .../Library/OpensbiPlatformLib/Platform.c | 57 ---- .../Universal/Sec/Edk2OpenSbiPlatform.c | 149 --------- .../PlatformPkg/Universal/Sec/SecMain.c | 48 ++- .../Universal/Sec/Riscv64/SecEntry.S | 300 ++++++++++-------- 6 files changed, 212 insertions(+), 356 deletions(-) diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Opensbi= PlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Op= ensbiPlatformLib.inf index 909fbffa8d..2e1227733a 100644 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatfor= mLib.inf +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatfor= mLib.inf @@ -51,12 +51,4 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize=0D =0D - gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase=0D - gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock=0D -=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress= =0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize=0D +=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platfo= rm/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf index 1cfbef961f..dd5f01ab4d 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf @@ -66,6 +66,10 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize=0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress= =0D + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize=0D diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platfor= m.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c index b477b81d74..c62d235333 100644 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c @@ -197,68 +197,11 @@ static u64 generic_tlbr_flush_limit(void) return SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT;=0D }=0D =0D -static int generic_system_reset_check(u32 reset_type, u32 reset_reason)=0D -{=0D - if (generic_plat && generic_plat->system_reset_check)=0D - return generic_plat->system_reset_check(reset_type,=0D - reset_reason,=0D - generic_plat_match);=0D - return fdt_system_reset_check(reset_type, reset_reason);=0D -}=0D -=0D -static void generic_system_reset(u32 reset_type, u32 reset_reason)=0D -{=0D - if (generic_plat && generic_plat->system_reset) {=0D - generic_plat->system_reset(reset_type, reset_reason,=0D - generic_plat_match);=0D - return;=0D - }=0D -=0D - fdt_system_reset(reset_type, reset_reason);=0D -}=0D -=0D -#define EDK2_ROOT_FW_REGION 0=0D -#define EDK2_FW_REGION 1=0D -#define EDK2_VARIABLE_REGION 2=0D -#define EDK2_ALL_REGION 3=0D -#define EDK2_END_REGION 4=0D -static struct sbi_domain_memregion root_memregs[EDK2_END_REGION + 1] =3D {= 0 };=0D -=0D -struct sbi_domain_memregion *get_mem_regions(void) {=0D - /* EDK2 root firmware domain memory region */=0D - root_memregs[EDK2_ROOT_FW_REGION].order =3D log2roundup(FixedPcdGet32(Pc= dRootFirmwareDomainSize));=0D - root_memregs[EDK2_ROOT_FW_REGION].base =3D FixedPcdGet32(PcdRootFirmware= DomainBaseAddress);=0D - root_memregs[EDK2_ROOT_FW_REGION].flags =3D 0;=0D -=0D - /*EDK2 firmware domain memory region */=0D - root_memregs[EDK2_FW_REGION].order =3D log2roundup(FixedPcdGet32(PcdFirm= wareDomainSize));=0D - root_memregs[EDK2_FW_REGION].base =3D FixedPcdGet32(PcdFirmwareDomainBas= eAddress);=0D - root_memregs[EDK2_FW_REGION].flags =3D SBI_DOMAIN_MEMREGION_EXECUTABLE |= SBI_DOMAIN_MEMREGION_READABLE;=0D -=0D - /*EDK2 firmware domain memory region */=0D - root_memregs[EDK2_VARIABLE_REGION].order =3D log2roundup(FixedPcdGet32(P= cdVariableFirmwareRegionSize));=0D - root_memregs[EDK2_VARIABLE_REGION].base =3D FixedPcdGet32(PcdVariableFir= mwareRegionBaseAddress);=0D - root_memregs[EDK2_VARIABLE_REGION].flags =3D SBI_DOMAIN_MEMREGION_READAB= LE | SBI_DOMAIN_MEMREGION_WRITEABLE;=0D -=0D - /* EDK2 domain allow everything memory region */=0D - root_memregs[EDK2_ALL_REGION].order =3D __riscv_xlen;=0D - root_memregs[EDK2_ALL_REGION].base =3D 0;=0D - root_memregs[EDK2_ALL_REGION].flags =3D (SBI_DOMAIN_MEMREGION_READABLE |= =0D - SBI_DOMAIN_MEMREGION_WRITEABLE |=0D - SBI_DOMAIN_MEMREGION_EXECUTABLE);=0D -=0D - /* EDK2 domain memory region end */=0D - root_memregs[EDK2_END_REGION].order =3D 0;=0D -=0D - return root_memregs;=0D -}=0D -=0D const struct sbi_platform_operations platform_ops =3D {=0D .early_init =3D generic_early_init,=0D .final_init =3D generic_final_init,=0D .early_exit =3D generic_early_exit,=0D .final_exit =3D generic_final_exit,=0D - .domains_root_regions =3D get_mem_regions,=0D .domains_init =3D generic_domains_init,=0D .console_init =3D fdt_serial_init,=0D .irqchip_init =3D fdt_irqchip_init,=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.= c b/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c index 79b2f33675..779705489c 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c @@ -117,18 +117,6 @@ int Edk2OpensbiPlatforMMISAGetXLEN (VOID) return 0;=0D }=0D =0D -/** Get platform specific root domain memory regions */=0D -struct sbi_domain_memregion *=0D -Edk2OpensbiPlatformGetMemRegions (VOID)=0D -{=0D - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));=0D -=0D - if (platform_ops.domains_root_regions) {=0D - return platform_ops.domains_root_regions ();=0D - }=0D - return 0;=0D -}=0D -=0D /** Initialize (or populate) domains for the platform */=0D int Edk2OpensbiPlatformDomainsInit (VOID)=0D {=0D @@ -140,25 +128,6 @@ int Edk2OpensbiPlatformDomainsInit (VOID) return 0;=0D }=0D =0D -/** Write a character to the platform console output */=0D -VOID Edk2OpensbiPlatformSerialPutc (=0D - CHAR8 Ch=0D - )=0D -{=0D - if (platform_ops.console_putc) {=0D - return platform_ops.console_putc (Ch);=0D - }=0D -}=0D -=0D -/** Read a character from the platform console input */=0D -int Edk2OpensbiPlatformSerialGetc (VOID)=0D -{=0D - if (platform_ops.console_getc) {=0D - return platform_ops.console_getc ();=0D - }=0D - return 0;=0D -}=0D -=0D /** Initialize the platform console */=0D int Edk2OpensbiPlatformSerialInit (VOID)=0D {=0D @@ -193,30 +162,6 @@ VOID Edk2OpensbiPlatformIrqchipExit (VOID) }=0D }=0D =0D -/** Send IPI to a target HART */=0D -VOID Edk2OpensbiPlatformIpiSend (=0D - UINT32 TargetHart=0D - )=0D -{=0D - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));=0D -=0D - if (platform_ops.ipi_send) {=0D - return platform_ops.ipi_send (TargetHart);=0D - }=0D -}=0D -=0D -/** Clear IPI for a target HART */=0D -VOID Edk2OpensbiPlatformIpiClear (=0D - UINT32 TargetHart=0D - )=0D -{=0D - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));=0D -=0D - if (platform_ops.ipi_clear) {=0D - return platform_ops.ipi_clear (TargetHart);=0D - }=0D -}=0D -=0D /** Initialize IPI for current HART */=0D int Edk2OpensbiPlatformIpiInit (=0D BOOLEAN ColdBoot=0D @@ -251,33 +196,6 @@ UINT64 Edk2OpensbiPlatformTlbrFlushLimit (VOID) return 0;=0D }=0D =0D -/** Get platform timer value */=0D -UINT64 Edk2OpensbiPlatformTimerValue (VOID)=0D -{=0D - if (platform_ops.timer_value) {=0D - return platform_ops.timer_value ();=0D - }=0D - return 0;=0D -}=0D -=0D -/** Start platform timer event for current HART */=0D -VOID Edk2OpensbiPlatformTimerEventStart (=0D - UINT64 NextEvent=0D - )=0D -{=0D - if (platform_ops.timer_event_start) {=0D - return platform_ops.timer_event_start (NextEvent);=0D - }=0D -}=0D -=0D -/** Stop platform timer event for current HART */=0D -VOID Edk2OpensbiPlatformTimerEventStop (VOID)=0D -{=0D - if (platform_ops.timer_event_stop) {=0D - return platform_ops.timer_event_stop ();=0D - }=0D -}=0D -=0D /** Initialize platform timer for current HART */=0D int Edk2OpensbiPlatformTimerInit (=0D BOOLEAN ColdBoot=0D @@ -301,61 +219,6 @@ VOID Edk2OpensbiPlatformTimerExit (VOID) }=0D }=0D =0D -/** Bringup the given hart */=0D -int Edk2OpensbiPlatformHartStart (=0D - UINT32 HartId,=0D - ulong Saddr=0D - )=0D -{=0D - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));=0D -=0D - if (platform_ops.hart_start) {=0D - return platform_ops.hart_start (HartId, Saddr);=0D - }=0D - return 0;=0D -}=0D -/**=0D - Stop the current hart from running. This call doesn't expect to=0D - return if success.=0D -**/=0D -int Edk2OpensbiPlatformHartStop (VOID)=0D -{=0D - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));=0D -=0D - if (platform_ops.hart_stop) {=0D - return platform_ops.hart_stop ();=0D - }=0D - return 0;=0D -}=0D -=0D -/**=0D - Check whether reset type and reason supported by the platform*=0D -=0D -**/=0D -int Edk2OpensbiPlatformSystemResetCheck (=0D - UINT32 ResetType,=0D - UINT32 ResetReason=0D - )=0D -{=0D - if (platform_ops.system_reset_check) {=0D - return platform_ops.system_reset_check (ResetType, ResetReason);=0D - }=0D - return 0;=0D -}=0D -=0D -/** Reset the platform */=0D -VOID Edk2OpensbiPlatformSystemReset (=0D - UINT32 ResetType,=0D - UINT32 ResetReason=0D - )=0D -{=0D - DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));=0D -=0D - if (platform_ops.system_reset) {=0D - return platform_ops.system_reset (ResetType, ResetReason);=0D - }=0D -}=0D -=0D /** platform specific SBI extension implementation probe function */=0D int Edk2OpensbiPlatformVendorExtCheck (=0D long ExtId=0D @@ -400,27 +263,15 @@ const struct sbi_platform_operations Edk2OpensbiPlatf= ormOps =3D { .final_exit =3D Edk2OpensbiPlatformFinalExit,=0D .misa_check_extension =3D Edk2OpensbiPlatforMMISACheckExtension,=0D .misa_get_xlen =3D Edk2OpensbiPlatforMMISAGetXLEN,=0D - .domains_root_regions =3D Edk2OpensbiPlatformGetMemRegions,=0D .domains_init =3D Edk2OpensbiPlatformDomainsInit,=0D - .console_putc =3D Edk2OpensbiPlatformSerialPutc,=0D - .console_getc =3D Edk2OpensbiPlatformSerialGetc,=0D .console_init =3D Edk2OpensbiPlatformSerialInit,=0D .irqchip_init =3D Edk2OpensbiPlatformIrqchipInit,=0D .irqchip_exit =3D Edk2OpensbiPlatformIrqchipExit,=0D - .ipi_send =3D Edk2OpensbiPlatformIpiSend,=0D - .ipi_clear =3D Edk2OpensbiPlatformIpiClear,=0D .ipi_init =3D Edk2OpensbiPlatformIpiInit,=0D .ipi_exit =3D Edk2OpensbiPlatformIpiExit,=0D .get_tlbr_flush_limit =3D Edk2OpensbiPlatformTlbrFlushLimit,=0D - .timer_value =3D Edk2OpensbiPlatformTimerValue,=0D - .timer_event_stop =3D Edk2OpensbiPlatformTimerEventStop,=0D - .timer_event_start =3D Edk2OpensbiPlatformTimerEventStart,=0D .timer_init =3D Edk2OpensbiPlatformTimerInit,=0D .timer_exit =3D Edk2OpensbiPlatformTimerExit,=0D - .hart_start =3D Edk2OpensbiPlatformHartStart,=0D - .hart_stop =3D Edk2OpensbiPlatformHartStop,=0D - .system_reset_check =3D Edk2OpensbiPlatformSystemResetCheck,=0D - .system_reset =3D Edk2OpensbiPlatformSystemReset,=0D .vendor_ext_check =3D Edk2OpensbiPlatformVendorExtCheck,=0D .vendor_ext_provider =3D Edk2OpensbiPlatformVendorExtProvider,=0D };=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.c index 93ff8a598d..3bc3690047 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c @@ -15,10 +15,12 @@ #include =0D #include =0D #include // Reference to header file in opensbi=0D +#include =0D #include // Reference to header file in opensbi=0D -#include // Reference to header file in opensbi=0D +#include // Reference to header file in opensbi=0D #include // Reference to header file in opensbi=0D #include // Reference to header file in opensbi=0D +#include // Reference to header file in opensbi=0D #include // Reference to header file in opensbi=0D #include // Reference to header file in opensbi=0D #include // Reference to header file in opensbi=0D @@ -31,8 +33,41 @@ extern struct sbi_platform_operations Edk2OpensbiPlatfor= mOps; atomic_t BootHartDone =3D ATOMIC_INITIALIZER(0);=0D atomic_t NonBootHartMessageLock =3D ATOMIC_INITIALIZER(0);=0D =0D +int sbi_domain_root_add_memregion(const struct sbi_domain_memregion *reg);= =0D +=0D typedef struct sbi_scratch *(*hartid2scratch)(ulong hartid, ulong hartinde= x);=0D =0D +struct sbi_domain_memregion fw_memregs;=0D +=0D +int SecSetEdk2FwMemoryRegions (VOID) {=0D + int Ret;=0D +=0D + Ret =3D 0;=0D +=0D + //=0D + // EDK2 PEI domain memory region=0D + //=0D + fw_memregs.order =3D log2roundup(FixedPcdGet32(PcdFirmwareDomainSize));= =0D + fw_memregs.base =3D FixedPcdGet32(PcdFirmwareDomainBaseAddress);=0D + fw_memregs.flags =3D SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREG= ION_READABLE;=0D + Ret =3D sbi_domain_root_add_memregion ((const struct sbi_domain_memregio= n *)&fw_memregs);=0D + if (Ret !=3D 0) {=0D + DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of FW Domain fail\n", _= _FUNCTION__));=0D + }=0D +=0D + //=0D + // EDK2 EFI Variable domain memory region=0D + //=0D + fw_memregs.order =3D log2roundup(FixedPcdGet32(PcdVariableFirmwareRegion= Size));=0D + fw_memregs.base =3D FixedPcdGet32(PcdVariableFirmwareRegionBaseAddress);= =0D + fw_memregs.flags =3D SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGIO= N_WRITEABLE;=0D + Ret =3D sbi_domain_root_add_memregion ((const struct sbi_domain_memregio= n *)&fw_memregs);=0D + if (Ret !=3D 0) {=0D + DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of variable FW Domain f= ail\n", __FUNCTION__));=0D + }=0D + return Ret;=0D +}=0D +=0D /**=0D Locates a section within a series of sections=0D with the specified section type.=0D @@ -405,6 +440,13 @@ SecPostOpenSbiPlatformEarlylInit( DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId));= =0D return 0;=0D }=0D + //=0D + // Setup firmware memory region.=0D + //=0D + if (SecSetEdk2FwMemoryRegions () !=3D 0) {=0D + ASSERT (FALSE);=0D + }=0D +=0D //=0D // Boot HART is already in the process of OpenSBI initialization.=0D // We can let other HART to keep booting.=0D @@ -477,7 +519,7 @@ SecPostOpenSbiPlatformFinalInit ( }=0D }=0D =0D - DEBUG((DEBUG_INFO, "%a: Jump to PEI Core with \n", __FUNCTION__));=0D + DEBUG((DEBUG_INFO, "%a: Will jump to PEI Core in OpenSBI with \n", __FUN= CTION__));=0D DEBUG((DEBUG_INFO, " sbi_scratch =3D %x\n", SbiScratch));=0D DEBUG((DEBUG_INFO, " sbi_platform =3D %x\n", SbiPlatform));=0D DEBUG((DEBUG_INFO, " FirmwareContext =3D %x\n", FirmwareContext));=0D @@ -793,7 +835,7 @@ VOID EFIAPI SecCoreStartUpWithStack( sbi_init(Scratch);=0D }=0D =0D -void OpensbiDebugPrint (char *debugstr, ...)=0D +VOID OpensbiDebugPrint (CHAR8 *debugstr, ...)=0D {=0D VA_LIST Marker;=0D =0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b= /Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S index dc410703e0..96087738a3 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S @@ -18,6 +18,12 @@ =0D #include =0D =0D +.macro MOV_3R __d0, __s0, __d1, __s1, __d2, __s2=0D + add \__d0, \__s0, zero=0D + add \__d1, \__s1, zero=0D + add \__d2, \__s2, zero=0D +.endm=0D +=0D .text=0D .align 3=0D =0D @@ -90,7 +96,11 @@ _scratch_init: la a4, _hartid_to_scratch=0D sd a4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp) /* Save _hartid_to_sc= ratch function in scratch buffer*/=0D sd zero, SBI_SCRATCH_TMP0_OFFSET(tp)=0D -=0D + /* Store trap-exit function address in scratch space */=0D + lla a4, _trap_exit=0D + sd a4, SBI_SCRATCH_TRAP_EXIT_OFFSET(tp)=0D + /* Clear tmp0 in scratch space */=0D + sd zero, SBI_SCRATCH_TMP0_OFFSET(tp)=0D #ifdef FW_OPTIONS=0D li a4, FW_OPTIONS=0D sd a4, SBI_SCRATCH_OPTIONS_OFFSET(tp)=0D @@ -322,160 +332,174 @@ _uninitialized_hart_wait: wfi=0D j _uninitialized_hart_wait=0D =0D - .align 3=0D - .section .entry, "ax", %progbits=0D - .align 3=0D - .globl _trap_handler=0D -_trap_handler:=0D -=0D +.macro TRAP_SAVE_AND_SETUP_SP_T0=0D /* Swap TP and MSCRATCH */=0D - csrrw tp, CSR_MSCRATCH, tp=0D + csrrw tp, CSR_MSCRATCH, tp=0D =0D /* Save T0 in scratch space */=0D - REG_S t0, SBI_SCRATCH_TMP0_OFFSET(tp)=0D + REG_S t0, SBI_SCRATCH_TMP0_OFFSET(tp)=0D =0D - /* Check which mode we came from */=0D - csrr t0, CSR_MSTATUS=0D - srl t0, t0, MSTATUS_MPP_SHIFT=0D - and t0, t0, PRV_M=0D - xori t0, t0, PRV_M=0D - beq t0, zero, _trap_handler_m_mode=0D -=0D - /* We came from S-mode or U-mode */=0D -_trap_handler_s_mode:=0D - /* Set T0 to original SP */=0D - add t0, sp, zero=0D -=0D - /* Setup exception stack */=0D - add sp, tp, -(SBI_TRAP_REGS_SIZE)=0D -=0D - /* Jump to code common for all modes */=0D - j _trap_handler_all_mode=0D -=0D - /* We came from M-mode */=0D -_trap_handler_m_mode:=0D - /* Set T0 to original SP */=0D - add t0, sp, zero=0D -=0D - /* Re-use current SP as exception stack */=0D - add sp, sp, -(SBI_TRAP_REGS_SIZE)=0D -=0D -_trap_handler_all_mode:=0D - /* Save original SP (from T0) on stack */=0D - REG_S t0, SBI_TRAP_REGS_OFFSET(sp)(sp)=0D + /*=0D + * Set T0 to appropriate exception stack=0D + *=0D + * Came_From_M_Mode =3D ((MSTATUS.MPP < PRV_M) ? 1 : 0) - 1;=0D + * Exception_Stack =3D TP ^ (Came_From_M_Mode & (SP ^ TP))=0D + *=0D + * Came_From_M_Mode =3D 0 =3D=3D> Exception_Stack =3D TP=0D + * Came_From_M_Mode =3D -1 =3D=3D> Exception_Stack =3D SP=0D + */=0D + csrr t0, CSR_MSTATUS=0D + srl t0, t0, MSTATUS_MPP_SHIFT=0D + and t0, t0, PRV_M=0D + slti t0, t0, PRV_M=0D + add t0, t0, -1=0D + xor sp, sp, tp=0D + and t0, t0, sp=0D + xor sp, sp, tp=0D + xor t0, tp, t0=0D +=0D + /* Save original SP on exception stack */=0D + REG_S sp, (SBI_TRAP_REGS_OFFSET(sp) - SBI_TRAP_REGS_SIZE)(t0)=0D +=0D + /* Set SP to exception stack and make room for trap registers */=0D + add sp, t0, -(SBI_TRAP_REGS_SIZE)=0D =0D /* Restore T0 from scratch space */=0D - REG_L t0, SBI_SCRATCH_TMP0_OFFSET(tp)=0D + REG_L t0, SBI_SCRATCH_TMP0_OFFSET(tp)=0D =0D /* Save T0 on stack */=0D - REG_S t0, SBI_TRAP_REGS_OFFSET(t0)(sp)=0D + REG_S t0, SBI_TRAP_REGS_OFFSET(t0)(sp)=0D =0D /* Swap TP and MSCRATCH */=0D - csrrw tp, CSR_MSCRATCH, tp=0D + csrrw tp, CSR_MSCRATCH, tp=0D +.endm=0D =0D +.macro TRAP_SAVE_MEPC_MSTATUS have_mstatush=0D /* Save MEPC and MSTATUS CSRs */=0D - csrr t0, CSR_MEPC=0D - REG_S t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)=0D - csrr t0, CSR_MSTATUS=0D - REG_S t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)=0D - REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)=0D -#if __riscv_xlen =3D=3D 32=0D - csrr t0, CSR_MISA=0D - srli t0, t0, ('H' - 'A')=0D - andi t0, t0, 0x1=0D - beq t0, zero, _skip_mstatush_save=0D - csrr t0, CSR_MSTATUSH=0D - REG_S t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)=0D -_skip_mstatush_save:=0D -#endif=0D + csrr t0, CSR_MEPC=0D + REG_S t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)=0D + csrr t0, CSR_MSTATUS=0D + REG_S t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)=0D +.if \have_mstatush=0D + csrr t0, CSR_MSTATUSH=0D + REG_S t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)=0D +.else=0D + REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)=0D +.endif=0D +.endm=0D +=0D +.macro TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0=0D + /* Save all general regisers except SP and T0 */=0D + REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp)=0D + REG_S ra, SBI_TRAP_REGS_OFFSET(ra)(sp)=0D + REG_S gp, SBI_TRAP_REGS_OFFSET(gp)(sp)=0D + REG_S tp, SBI_TRAP_REGS_OFFSET(tp)(sp)=0D + REG_S t1, SBI_TRAP_REGS_OFFSET(t1)(sp)=0D + REG_S t2, SBI_TRAP_REGS_OFFSET(t2)(sp)=0D + REG_S s0, SBI_TRAP_REGS_OFFSET(s0)(sp)=0D + REG_S s1, SBI_TRAP_REGS_OFFSET(s1)(sp)=0D + REG_S a0, SBI_TRAP_REGS_OFFSET(a0)(sp)=0D + REG_S a1, SBI_TRAP_REGS_OFFSET(a1)(sp)=0D + REG_S a2, SBI_TRAP_REGS_OFFSET(a2)(sp)=0D + REG_S a3, SBI_TRAP_REGS_OFFSET(a3)(sp)=0D + REG_S a4, SBI_TRAP_REGS_OFFSET(a4)(sp)=0D + REG_S a5, SBI_TRAP_REGS_OFFSET(a5)(sp)=0D + REG_S a6, SBI_TRAP_REGS_OFFSET(a6)(sp)=0D + REG_S a7, SBI_TRAP_REGS_OFFSET(a7)(sp)=0D + REG_S s2, SBI_TRAP_REGS_OFFSET(s2)(sp)=0D + REG_S s3, SBI_TRAP_REGS_OFFSET(s3)(sp)=0D + REG_S s4, SBI_TRAP_REGS_OFFSET(s4)(sp)=0D + REG_S s5, SBI_TRAP_REGS_OFFSET(s5)(sp)=0D + REG_S s6, SBI_TRAP_REGS_OFFSET(s6)(sp)=0D + REG_S s7, SBI_TRAP_REGS_OFFSET(s7)(sp)=0D + REG_S s8, SBI_TRAP_REGS_OFFSET(s8)(sp)=0D + REG_S s9, SBI_TRAP_REGS_OFFSET(s9)(sp)=0D + REG_S s10, SBI_TRAP_REGS_OFFSET(s10)(sp)=0D + REG_S s11, SBI_TRAP_REGS_OFFSET(s11)(sp)=0D + REG_S t3, SBI_TRAP_REGS_OFFSET(t3)(sp)=0D + REG_S t4, SBI_TRAP_REGS_OFFSET(t4)(sp)=0D + REG_S t5, SBI_TRAP_REGS_OFFSET(t5)(sp)=0D + REG_S t6, SBI_TRAP_REGS_OFFSET(t6)(sp)=0D +.endm=0D +=0D +.macro TRAP_CALL_C_ROUTINE=0D + /* Call C routine */=0D + add a0, sp, zero=0D + call sbi_trap_handler=0D +.endm=0D +=0D +.macro TRAP_RESTORE_GENERAL_REGS_EXCEPT_A0_T0=0D + /* Restore all general regisers except A0 and T0 */=0D + REG_L ra, SBI_TRAP_REGS_OFFSET(ra)(a0)=0D + REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(a0)=0D + REG_L gp, SBI_TRAP_REGS_OFFSET(gp)(a0)=0D + REG_L tp, SBI_TRAP_REGS_OFFSET(tp)(a0)=0D + REG_L t1, SBI_TRAP_REGS_OFFSET(t1)(a0)=0D + REG_L t2, SBI_TRAP_REGS_OFFSET(t2)(a0)=0D + REG_L s0, SBI_TRAP_REGS_OFFSET(s0)(a0)=0D + REG_L s1, SBI_TRAP_REGS_OFFSET(s1)(a0)=0D + REG_L a1, SBI_TRAP_REGS_OFFSET(a1)(a0)=0D + REG_L a2, SBI_TRAP_REGS_OFFSET(a2)(a0)=0D + REG_L a3, SBI_TRAP_REGS_OFFSET(a3)(a0)=0D + REG_L a4, SBI_TRAP_REGS_OFFSET(a4)(a0)=0D + REG_L a5, SBI_TRAP_REGS_OFFSET(a5)(a0)=0D + REG_L a6, SBI_TRAP_REGS_OFFSET(a6)(a0)=0D + REG_L a7, SBI_TRAP_REGS_OFFSET(a7)(a0)=0D + REG_L s2, SBI_TRAP_REGS_OFFSET(s2)(a0)=0D + REG_L s3, SBI_TRAP_REGS_OFFSET(s3)(a0)=0D + REG_L s4, SBI_TRAP_REGS_OFFSET(s4)(a0)=0D + REG_L s5, SBI_TRAP_REGS_OFFSET(s5)(a0)=0D + REG_L s6, SBI_TRAP_REGS_OFFSET(s6)(a0)=0D + REG_L s7, SBI_TRAP_REGS_OFFSET(s7)(a0)=0D + REG_L s8, SBI_TRAP_REGS_OFFSET(s8)(a0)=0D + REG_L s9, SBI_TRAP_REGS_OFFSET(s9)(a0)=0D + REG_L s10, SBI_TRAP_REGS_OFFSET(s10)(a0)=0D + REG_L s11, SBI_TRAP_REGS_OFFSET(s11)(a0)=0D + REG_L t3, SBI_TRAP_REGS_OFFSET(t3)(a0)=0D + REG_L t4, SBI_TRAP_REGS_OFFSET(t4)(a0)=0D + REG_L t5, SBI_TRAP_REGS_OFFSET(t5)(a0)=0D + REG_L t6, SBI_TRAP_REGS_OFFSET(t6)(a0)=0D +.endm=0D +=0D +.macro TRAP_RESTORE_MEPC_MSTATUS have_mstatush=0D + /* Restore MEPC and MSTATUS CSRs */=0D + REG_L t0, SBI_TRAP_REGS_OFFSET(mepc)(a0)=0D + csrw CSR_MEPC, t0=0D + REG_L t0, SBI_TRAP_REGS_OFFSET(mstatus)(a0)=0D + csrw CSR_MSTATUS, t0=0D +.if \have_mstatush=0D + REG_L t0, SBI_TRAP_REGS_OFFSET(mstatusH)(a0)=0D + csrw CSR_MSTATUSH, t0=0D +.endif=0D +.endm=0D +=0D +.macro TRAP_RESTORE_A0_T0=0D + /* Restore T0 */=0D + REG_L t0, SBI_TRAP_REGS_OFFSET(t0)(a0)=0D =0D - /* Save all general registers except SP and T0 */=0D - REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp)=0D - REG_S ra, SBI_TRAP_REGS_OFFSET(ra)(sp)=0D - REG_S gp, SBI_TRAP_REGS_OFFSET(gp)(sp)=0D - REG_S tp, SBI_TRAP_REGS_OFFSET(tp)(sp)=0D - REG_S t1, SBI_TRAP_REGS_OFFSET(t1)(sp)=0D - REG_S t2, SBI_TRAP_REGS_OFFSET(t2)(sp)=0D - REG_S s0, SBI_TRAP_REGS_OFFSET(s0)(sp)=0D - REG_S s1, SBI_TRAP_REGS_OFFSET(s1)(sp)=0D - REG_S a0, SBI_TRAP_REGS_OFFSET(a0)(sp)=0D - REG_S a1, SBI_TRAP_REGS_OFFSET(a1)(sp)=0D - REG_S a2, SBI_TRAP_REGS_OFFSET(a2)(sp)=0D - REG_S a3, SBI_TRAP_REGS_OFFSET(a3)(sp)=0D - REG_S a4, SBI_TRAP_REGS_OFFSET(a4)(sp)=0D - REG_S a5, SBI_TRAP_REGS_OFFSET(a5)(sp)=0D - REG_S a6, SBI_TRAP_REGS_OFFSET(a6)(sp)=0D - REG_S a7, SBI_TRAP_REGS_OFFSET(a7)(sp)=0D - REG_S s2, SBI_TRAP_REGS_OFFSET(s2)(sp)=0D - REG_S s3, SBI_TRAP_REGS_OFFSET(s3)(sp)=0D - REG_S s4, SBI_TRAP_REGS_OFFSET(s4)(sp)=0D - REG_S s5, SBI_TRAP_REGS_OFFSET(s5)(sp)=0D - REG_S s6, SBI_TRAP_REGS_OFFSET(s6)(sp)=0D - REG_S s7, SBI_TRAP_REGS_OFFSET(s7)(sp)=0D - REG_S s8, SBI_TRAP_REGS_OFFSET(s8)(sp)=0D - REG_S s9, SBI_TRAP_REGS_OFFSET(s9)(sp)=0D - REG_S s10, SBI_TRAP_REGS_OFFSET(s10)(sp)=0D - REG_S s11, SBI_TRAP_REGS_OFFSET(s11)(sp)=0D - REG_S t3, SBI_TRAP_REGS_OFFSET(t3)(sp)=0D - REG_S t4, SBI_TRAP_REGS_OFFSET(t4)(sp)=0D - REG_S t5, SBI_TRAP_REGS_OFFSET(t5)(sp)=0D - REG_S t6, SBI_TRAP_REGS_OFFSET(t6)(sp)=0D + /* Restore A0 */=0D + REG_L a0, SBI_TRAP_REGS_OFFSET(a0)(a0)=0D +.endm=0D =0D - /* Call C routine */=0D - add a0, sp, zero=0D - call sbi_trap_handler=0D -=0D - /* Restore all general registers except SP and T0 */=0D - REG_L ra, SBI_TRAP_REGS_OFFSET(ra)(sp)=0D - REG_L gp, SBI_TRAP_REGS_OFFSET(gp)(sp)=0D - REG_L tp, SBI_TRAP_REGS_OFFSET(tp)(sp)=0D - REG_L t1, SBI_TRAP_REGS_OFFSET(t1)(sp)=0D - REG_L t2, SBI_TRAP_REGS_OFFSET(t2)(sp)=0D - REG_L s0, SBI_TRAP_REGS_OFFSET(s0)(sp)=0D - REG_L s1, SBI_TRAP_REGS_OFFSET(s1)(sp)=0D - REG_L a0, SBI_TRAP_REGS_OFFSET(a0)(sp)=0D - REG_L a1, SBI_TRAP_REGS_OFFSET(a1)(sp)=0D - REG_L a2, SBI_TRAP_REGS_OFFSET(a2)(sp)=0D - REG_L a3, SBI_TRAP_REGS_OFFSET(a3)(sp)=0D - REG_L a4, SBI_TRAP_REGS_OFFSET(a4)(sp)=0D - REG_L a5, SBI_TRAP_REGS_OFFSET(a5)(sp)=0D - REG_L a6, SBI_TRAP_REGS_OFFSET(a6)(sp)=0D - REG_L a7, SBI_TRAP_REGS_OFFSET(a7)(sp)=0D - REG_L s2, SBI_TRAP_REGS_OFFSET(s2)(sp)=0D - REG_L s3, SBI_TRAP_REGS_OFFSET(s3)(sp)=0D - REG_L s4, SBI_TRAP_REGS_OFFSET(s4)(sp)=0D - REG_L s5, SBI_TRAP_REGS_OFFSET(s5)(sp)=0D - REG_L s6, SBI_TRAP_REGS_OFFSET(s6)(sp)=0D - REG_L s7, SBI_TRAP_REGS_OFFSET(s7)(sp)=0D - REG_L s8, SBI_TRAP_REGS_OFFSET(s8)(sp)=0D - REG_L s9, SBI_TRAP_REGS_OFFSET(s9)(sp)=0D - REG_L s10, SBI_TRAP_REGS_OFFSET(s10)(sp)=0D - REG_L s11, SBI_TRAP_REGS_OFFSET(s11)(sp)=0D - REG_L t3, SBI_TRAP_REGS_OFFSET(t3)(sp)=0D - REG_L t4, SBI_TRAP_REGS_OFFSET(t4)(sp)=0D - REG_L t5, SBI_TRAP_REGS_OFFSET(t5)(sp)=0D - REG_L t6, SBI_TRAP_REGS_OFFSET(t6)(sp)=0D + .section .entry, "ax", %progbits=0D + .align 3=0D + .globl _trap_handler=0D + .globl _trap_exit=0D +_trap_handler:=0D + TRAP_SAVE_AND_SETUP_SP_T0=0D =0D - /* Restore MEPC and MSTATUS CSRs */=0D - REG_L t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)=0D - csrw CSR_MEPC, t0=0D - REG_L t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)=0D - csrw CSR_MSTATUS, t0=0D -#if __riscv_xlen =3D=3D 32=0D - csrr t0, CSR_MISA=0D - srli t0, t0, ('H' - 'A')=0D - andi t0, t0, 0x1=0D - beq t0, zero, _skip_mstatush_restore=0D - REG_L t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)=0D - csrw CSR_MSTATUSH, t0=0D -_skip_mstatush_restore:=0D -#endif=0D + TRAP_SAVE_MEPC_MSTATUS 0=0D =0D - /* Restore T0 */=0D - REG_L t0, SBI_TRAP_REGS_OFFSET(t0)(sp)=0D + TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0=0D +=0D + TRAP_CALL_C_ROUTINE=0D +=0D +_trap_exit:=0D + TRAP_RESTORE_GENERAL_REGS_EXCEPT_A0_T0=0D +=0D + TRAP_RESTORE_MEPC_MSTATUS 0=0D =0D - /* Restore SP */=0D - REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(sp)=0D + TRAP_RESTORE_A0_T0=0D =0D mret=0D =0D --=20 2.31.1