* [edk2-platforms][PATCH 01/30] RISC-V/PlatformPkg: Update document
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 02/30] RISC-V: Add RISC-V PeiCoreEntryPoint library Abner Chang
` (30 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Update EDK2 RISC-V port architectural diagrams.
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
Platform/RISC-V/PlatformPkg/Readme.md | 132 +-
.../Documents/Media/RiscVEdk2BootProcess.svg | 1928 +++++++++++++++++
.../Documents/Media/RiscVEdk2FwDomain.svg | 1290 +++++++++++
3 files changed, 3336 insertions(+), 14 deletions(-)
create mode 100644 Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2BootProcess.svg
create mode 100644 Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2FwDomain.svg
diff --git a/Platform/RISC-V/PlatformPkg/Readme.md b/Platform/RISC-V/PlatformPkg/Readme.md
index 4b933a2e0f..66fba15544 100644
--- a/Platform/RISC-V/PlatformPkg/Readme.md
+++ b/Platform/RISC-V/PlatformPkg/Readme.md
@@ -2,6 +2,113 @@
## EDK2 RISC-V Platform Project
+### EDK2 RISC-V Design and the Boot Processes
+RISC-V edk2 port is designed base on edk2 boot phases and leverage [RISC-V OpenSBI](https://github.com/riscv/opensbi) (which is the implementation of [RISC-V SBI](https://github.com/riscv/riscv-sbi-doc)) as an edk2 library. The design concept is to leverage RISC-V SBI implementation, the basic RISC-V HARTs and the platform initialization. However, it still keeps the edk2 build mechanism and the boot processes. RISC-V OpenSBI is built as
+an library and linked with edk2 SEC module. The design diagram and the boot flow is shown in below figure,
+
+#### RISC-V EDK2 Port Design Diagrams
+
+
+#### SEC Phase
+As the most of edk2 platforms SEC implementations, RISC-V edk2 port SEC module initiates the fundamental platform
+boot environment. RISC-V edk2 SEC module linked with [RiscVOpensbiLib](#riscvopensbilib-library) that pulls in the OpenSBI core source files into the build as a library. SEC module invokes sbi_init() to execute through the OpenSBI
+initialization flow. Afterwards, SEC phase hands off to PEI phase via OpenSBI with the ***NextAddress*** and ***NextMode*** are configured.
+The entire SEC phase with ***RiscVOpensbiLib*** is executed in the Machine-mode (M-mode) which is the highest
+and the mandatory privilege mode of RISC-V HART. The SBI implementation is also executed in the M-mode that
+provides the Supervisor Binary Interface for the entities run in the Supervisor-mode (S-mode). The default
+privilege mode is configured to S-mode for the next phase after SEC, that says the PEI, DXE and BDS phases are
+default executed in S-mode unless the corresponding [PCDs](#risc-v-platform-pcd-settings) are configured
+differently from the default settings according to the OEM platform design.
+
+##### RiscVOpensbiLib Library
+[Indicated as #1 in the figure](#risc-v-edk2-port-design-diagrams)
+> ***RiscVOpensbiLib*** is a edk2 wrapper library of OpenSBI. SEC module is the only consumer of ***RiscVOpensbiLib*** across the entire edk2 boot processes. The sub-module under ***RiscVOpensbiLib*** is updated
+to align with OpenSBI project. As mentioned earlier, ***RiscVOpensbiLib*** provides the RISC-V SBI
+implementation and initialize the OpenSBI boot flow. SEC module is also linked with below libraries,
+- edk2 [OpenSbiPlatformLib](#OpenSbiPlatformLib-library) library that provides the generic RISC-V platform initialization code.
+- edk2 [RiscVSpecifialPlatformLib](#RiscVSpecifialPlatformLib-library) library which is provided by the RISC-V
+platform vendor for the platform-specific initialization. The underlying implementation of above two edk2 libraries
+are from OpenSBI project. edk2 libraries are introduced as the wrapper libraries that separates and organizes OpenSBI core and platform code based on edk2 framework and the the build mechanism for edk2 RISC-V platforms. ***RiscVOpensbiLib*** library is located under [RISC-V ProcessorPkg](https://github.com/tianocore/edk2-platforms/tree/master/Silicon/RISC-V/ProcessorPkg) while the platform code (e.g. OpenSbiPlatformLib) is located under [RISC-V PlatformPkg](https://github.com/tianocore/edk2-platforms/tree/master/Platform/RISC-V/PlatformPkg).
+- edk2 [RiscVSpecifialPlatformLib](#riscvspecifialplatformlib) library is provided by the platform vendor and located under edk2 RISC-V platform-specific folder.
+
+##### OpenSbiPlatformLib Library
+[Indicated as #2 in the figure](#risc-v-edk2-port-design-diagrams)
+> ***OpenSbiPlatformLib*** provides the generic RISC-V platform initialization code. Platform vendor can just utilize this library if they don't have additional requirements on the platform initialization.
+
+##### RiscVSpecifialPlatformLib Library
+[Indicated as #3 in the figure](#risc-v-edk2-port-design-diagrams)
+> The major use case of this library is to facilitate the interfaces for platform vendors to provide the special
+platform initialization based on the generic platform initialization library.
+
+##### Edk2OpensbiPlatformWrapperLib Library
+[Indicated as #4 in the figure](#risc-v-edk2-port-design-diagrams)
+> In order to providing the flexibility to edk2 RISC-V firmware solution, ***Edk2OpensbiPlatformWrapperLib*** is the wrapper library of [OpenSbiPlatformLib](#OpenSbiPlatformLib-library) to provide the interfaces for OEM. The ***platform_ops_address***in the generic platform structure is replaced with ***Edk2OpensbiplatformOps*** in SEC
+module. The platform function invoked by OpenSBI core is hooked to ***Edk2OpensbiPlatformWrapperLib***. This gives
+a change to OEM for implementing platform-specific initialization before and after the generic platform code. OEM
+can override this library under their platform folder on demand without touching ***RiscVOpensbiLib*** library
+source files and other common source files.
+
+##### Next Phase Address and Privilege Mode
+[Indicated as #5 in the figure](#risc-v-edk2-port-design-diagrams)
+> Once OpenSBI finishes the boot initialization, it will jump to the next phase with the default privilege set to
+S-mode. In order to facilitate the flexibility for a variant of platform demands. EDK2 RISC-V provides the [PCDs](#risc-v-platform-pcd-settings) as the configurable privilege for the next phase. Whether to have PEI or later
+phases executed in the default S-mode or to keep the RISC-V edk2 boot phase privilege in M-mode is at platform design discretion. The SEC module sets the next phase address to the PEI Core entry point with a configurable
+privilege according to the PCD.
+
+#### PEI Phase
+SEC module hands off the boot process to PEI core in the privilege configured by ***PcdPeiCorePrivilegeMode*** PCD *(TODO, currently the privilege is forced to S-mode)*. PEI and later phases are allowed to executed in M-mode
+if the platform doesn't require Hypervisor-extended Supervisor mode (HS-mode) for the virtualization. RISC-V edk2 port provides its own instance ***PeiCoreEntryPoint*** library [(indicated as #7 in the figure)](#risc-v-edk2-port-design-diagrams) and linked with [PlatformSecPpiLib](#platformsecppilib-library) in order to support the S-mode PEI phase. PEI core requires [RiscVFirmwareContextLib](#riscVfirmwarecontextlib-library) library to retrieve the information of RISC-V HARTs and platform (e.g. FDT) configurations that built up in SEC phase. ***PeiServicePointer*** is also maintained in the ***RISC-V OpenSBI FirmwareContext*** structure and the pointer is retrieved by [PeiServiceTablePointerOpensbi](#peiservicetablepointeropensbi-library) library.
+
+##### PlatformSecPpiLib Library
+[Indicated as #8 in the figure](#risc-v-edk2-port-design-diagrams)
+
+> Some platform has the PEI protocol interface (PPI) prepared in SEC phase and pass the PPI description to PEI phase for the installation. That means the PPI code resides in SEC module and executed in PEI phase. Due to the SEC
+(with OpenSBI) is protected by the RISC-V Physical Memory Protection (PMP) through [OpenSBI firmware domain](#edk2-opensbi-firmware-domain), the SEC can be only accessed and executed when RISC-V HART is operated in M-mode. The SEC PPI passed to PEI is not able to be executed by any PEI modules. Thus we have ***PlatformSecPpiLib*** library for the platforms that requires to install the PPI at the early stage of PEI core instead of installing PPI
+during PEI dispatcher that maybe too late for some platform use cases. ***PlatformSecPpiLib*** is currently
+executed in S-mode because we force to switch RISC-V boot HART to S-mode when SEC hands of boot process to PEI
+phase. ***PlatformSecPpiLib*** can also executed in M-mode once we have the full implementation of [***PcdPeiCorePrivilegeMode***.](#risc-v-platform-pcd-settings)
+
+##### RiscVFirmwareContextLib Library
+[Indicated as #9 in the figure](#risc-v-edk2-port-design-diagrams)
+
+> The ***OpenSBI FirmwareContext*** is a structure member in sbi_platform, that can carry the firmware
+solution-defined information to edk2 boot phases after SEC. edk2 defines its own ***FirmwareContext*** as below in
+the current implementation.
+
+ typedef struct {
+ UINT64 BootHartId;
+ VOID *PeiServiceTable; // PEI Service table
+ UINT64 FlattenedDeviceTree; // Pointer to Flattened Device tree
+ UINT64 SecPeiHandOffData; // This is EFI_SEC_PEI_HAND_OFF passed to PEI Core.
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_SUPPORTED];
+ } EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;
+
+> ***RiscVFirmwareContextLib*** library is used by PEI module for obtaining the ***FirmwareContext*** pointer.
+
+##### PeiServiceTablePointerOpensbi Library
+[Indicated as #10 in the figure](#risc-v-edk2-port-design-diagrams)
+
+> ***PeiServiceTablePointerOpensbi*** is the library that provides Get/Set PeiServiceTablePointer. ***RiscVFirmwareContextLib*** is the underlying library for the operations on PEI service table pointer.
+
+##### PEI OpenSBI PPI
+[Indicated as #11 in the figure](#risc-v-edk2-port-design-diagrams)
+
+> edk2 PEI OpenSBI PPI *(TODO)* provides the unified interface for all PEI drivers to invoke SBI services.
+
+#### DXE Phase
+DXE IPL PEI module hands off the boot process to DXE Core in the privilege configured by PcdDxeCorePrivilegeMode PCD *(TODO, currently is not implemented yet)*. edk2 DXE OpenSBI protocol *(TODO, indicated as #12 in the figure)* provides the unified interface for all DXE drivers to invoke SBI services.
+
+#### BDS Phase
+The implementation of RISC-V edk2 port in BDS phase is the same as it is in DXE phase which is executed in the
+privilege configured by PcdDxeCorePrivilegeMode PCD *(TODO, currently the privilege is forced to S-mode)*. The
+OpenSBI is also provided through edk2 DXE OpenSBI Protocol*(TODO, indicated as #12 in the figure)*. However, BDS must transits the privilege mode to S-mode before it handing off the boot process to S-mode OS, OS boot loader or EFI application.
+
+#### EDK2 OpenSBI Firmware Domain
+
+
+
+OpenSBI implements the firmware domain mechanism to protect the root firmware (which is the OpenSBI itself) as the M-mode only access and execute region. RISC-V edk2 port configures the root firmware domain via [PCDs](#risc-v-platform-pcd-settings) to protect SEC firmware volume, memory and OpenSBI stuff. The firmware region (non-root firmware) that accommodates PEI and DXE phase FV regions, while EFI variable region is reported as a separate firmware region as it shows in above figure.
+
### EDK2 Build Architecture for RISC-V
The edk2 build architecture which is supported and verified on edk2 code base for
RISC-V platforms is `RISCV64`.
@@ -49,18 +156,9 @@ Then you can build the edk2 firmware image for RISC-V platforms.
build -a RISCV64 -t GCC5 -p Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
```
-## RISC-V OpenSBI Library
-RISC-V [OpenSBI](https://github.com/riscv/opensbi) is the implementation of
-[RISC-V SBI (Supervisor Binary Interface) specification](https://github.com/riscv/riscv-sbi-doc).
-For EDK2 UEFI firmware solution, RISC-V OpenSBI is integrated as a library
-[(submoudule)](Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi) in EDK2
-RISC-V Processor Package. The RISC-V OpenSBI library is built in SEC driver without
-any modifications and provides the interfaces for supervisor mode execution environment
-to execute privileged operations.
-
## RISC-V Platform PCD settings
### EDK2 Firmware Volume Settings
-EDK2 Firmware volume related PCDs which declared in platform FDF file.
+EDK2 Firmware volume related PCDs which is declared in platform FDF file.
| **PCD name** |**Usage**|
|--------------|---------|
@@ -86,10 +184,14 @@ The PCD settings regard to EFI Variable
### RISC-V Physical Memory Protection (PMP) Region Settings
Below PCDs could be set in platform FDF file.
-| **PCD name** |**Usage**|
-|--------------|---------|
-|PcdFwStartAddress| The starting address of firmware region to protected by PMP|
-|PcdFwEndAddress| The ending address of firmware region to protected by PMP|
+| **PCD name** |**Usage**|**Access Permission in M-mode**|**Access Permission in S-mode**|
+|--------------|---------|---------|---------|
+|PcdRootFirmwareDomainBaseAddress| The starting address of root firmware domain protected by PMP|Full access|No Access|
+|PcdRootFirmwareDomainSize| The size of root firmware domain|-|-|
+|PcdFirmwareDomainBaseAddress| The starting address of firmware domain that can be accessed and executed in S-mode|Full access|Readable and Executable|
+|PcdFirmwareDomainSize| The size of firmware domain|-|-|
+|PcdVariableFirmwareRegionBaseAddress| The starting address of EFI variable region that can be accessed in S-mode|Full access|Readale and Writable|
+|PcdVariableFirmwareRegionSize| The size of EFI variable firmware region|-|-|
### RISC-V Processor HART Settings
@@ -98,6 +200,7 @@ Below PCDs could be set in platform FDF file.
|PcdHartCount| Number of RISC-V HARTs, the value is processor-implementation specific|
|PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and boot system to OS|
|PcdBootableHartNumber|The bootable HART number, which is incorporate with RISC-V OpenSBI platform hart_index2id value|
+|PcdBootableHartIndexToId| if PcdBootableHartNumber == 0, hart_index2id is built from Device Tree, otherwise this is an array of HART index to HART ID|
### RISC-V OpenSBI Settings
@@ -109,6 +212,7 @@ Below PCDs could be set in platform FDF file.
|PcdTemporaryRamBase| The base address of temporary memory for PEI phase|
|PcdTemporaryRamSize| The temporary memory size for PEI phase|
|PcdPeiCorePrivilegeMode|The target RISC-V privilege mode for edk2 PEI phase|
+|PcdDxeCorePrivilegeMode (TODO)|The target RISC-V privilege mode for edk2 DXE phase|
## Supported Operating Systems
Currently support boot to EFI Shell and Linux kernel.
diff --git a/Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2BootProcess.svg b/Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2BootProcess.svg
new file mode 100644
index 0000000000..dfd47a75b9
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+ <g id="shape245-184" v:mID="245" v:groupContext="shape" transform="translate(191.37,747.361) rotate(180)">
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+ <g id="shape249-187" v:mID="249" v:groupContext="shape" transform="translate(209.37,-320.49)">
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+ <desc>OEM can override this library instance to hook before/after e...</desc>
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+ <text x="6.57" y="459.31" class="st33" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>OEM can override this library <tspan
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+ <title>Directed line 1</title>
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+ <title>Link.256</title>
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+ <desc>DXE SBI Procotol</desc>
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+ <desc>SBI Implementation</desc>
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+ <desc>2</desc>
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+ <v:cp v:nameU="Duration" v:lbl="Duration" v:type="2" v:langID="1033"/>
+ <v:cp v:nameU="Resources" v:lbl="Resources" v:langID="1033"/>
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+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
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+ <title>Data process.344</title>
+ <desc>3</desc>
+ <v:custProps>
+ <v:cp v:nameU="Cost" v:lbl="Cost" v:type="7" v:format="@" v:langID="1033"/>
+ <v:cp v:nameU="Duration" v:lbl="Duration" v:type="2" v:langID="1033"/>
+ <v:cp v:nameU="Resources" v:lbl="Resources" v:langID="1033"/>
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+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
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+ <text x="4.88" y="497.61" class="st48" v:langID="1028"><v:paragraph v:horizAlign="1"/><v:tabList/>3</text> </g>
+ <g id="shape345-433" v:mID="345" v:groupContext="shape" v:layerMember="1" transform="translate(76.4658,-283.193)">
+ <title>Data process.345</title>
+ <desc>4</desc>
+ <v:custProps>
+ <v:cp v:nameU="Cost" v:lbl="Cost" v:type="7" v:format="@" v:langID="1033"/>
+ <v:cp v:nameU="Duration" v:lbl="Duration" v:type="2" v:langID="1033"/>
+ <v:cp v:nameU="Resources" v:lbl="Resources" v:langID="1033"/>
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+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
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+ <g id="shape347-436" v:mID="347" v:groupContext="shape" v:layerMember="1" transform="translate(299.062,-417.24)">
+ <title>Data process.347</title>
+ <desc>5</desc>
+ <v:custProps>
+ <v:cp v:nameU="Cost" v:lbl="Cost" v:type="7" v:format="@" v:langID="1033"/>
+ <v:cp v:nameU="Duration" v:lbl="Duration" v:type="2" v:langID="1033"/>
+ <v:cp v:nameU="Resources" v:lbl="Resources" v:langID="1033"/>
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+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
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+ <v:textBlock v:margins="rect(1,1,1,1)"/>
+ <v:textRect cx="6.90421" cy="495.206" width="13.81" height="13.8084"/>
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+ <g id="shape348-439" v:mID="348" v:groupContext="shape" v:layerMember="1" transform="translate(360.12,-367.586)">
+ <title>Data process.348</title>
+ <desc>6</desc>
+ <v:custProps>
+ <v:cp v:nameU="Cost" v:lbl="Cost" v:type="7" v:format="@" v:langID="1033"/>
+ <v:cp v:nameU="Duration" v:lbl="Duration" v:type="2" v:langID="1033"/>
+ <v:cp v:nameU="Resources" v:lbl="Resources" v:langID="1033"/>
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+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
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+ <v:textBlock v:margins="rect(1,1,1,1)"/>
+ <v:textRect cx="6.90421" cy="495.206" width="13.81" height="13.8084"/>
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+ <title>Data process.349</title>
+ <desc>7</desc>
+ <v:custProps>
+ <v:cp v:nameU="Cost" v:lbl="Cost" v:type="7" v:format="@" v:langID="1033"/>
+ <v:cp v:nameU="Duration" v:lbl="Duration" v:type="2" v:langID="1033"/>
+ <v:cp v:nameU="Resources" v:lbl="Resources" v:langID="1033"/>
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+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
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+ <title>Data process.350</title>
+ <desc>8</desc>
+ <v:custProps>
+ <v:cp v:nameU="Cost" v:lbl="Cost" v:type="7" v:format="@" v:langID="1033"/>
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+ <title>Data process.351</title>
+ <desc>9</desc>
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+ <desc>11</desc>
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+ <desc>12</desc>
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+ <g id="shape173-465" v:mID="173" v:groupContext="shape" transform="translate(56.37,-437.49)">
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+ <desc>SEC</desc>
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+ <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.057976973684212):1"/>
+ <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.057976973684212):1"/>
+ <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.057976973684212):1"/>
+ </v:userDefs>
+ <v:textBlock v:margins="rect(4,4,4,4)"/>
+ <v:textRect cx="39.6563" cy="297.308" width="79.32" height="23.625"/>
+ <path d="M4.17 309.12 L75.14 309.12 A4.17427 4.17427 -180 0 0 79.31 304.95 L79.31 289.67 A4.17427 4.17427 -180 0
+ 0 75.14 285.5 L4.17 285.5 A4.17427 4.17427 -180 0 0 0 289.67 L0 304.95 A4.17427 4.17427 -180 0 0 4.17
+ 309.12 Z" class="st2"/>
+ <text x="19.79" y="300.31" class="st3" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>PEI Driver</text> </g>
+ <g id="shape397-185" v:mID="397" v:groupContext="shape" transform="translate(109.065,-17.88)">
+ <title>Rounded Rectangle.397</title>
+ <desc>PEI Drivers</desc>
+ <v:userDefs>
+ <v:ud v:nameU="CTypeTopLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+ <v:ud v:nameU="CTypeTopRightSnip" v:prompt="" v:val="VT0(0):5"/>
+ <v:ud v:nameU="CTypeBotLeftSnip" v:prompt="" v:val="VT0(0):5"/>
+ <v:ud v:nameU="CTypeBotRightSnip" v:prompt="" v:val="VT0(0):5"/>
+ <v:ud v:nameU="CornerLockHoriz" v:prompt="" v:val="VT0(1):5"/>
+ <v:ud v:nameU="CornerLockVert" v:prompt="" v:val="VT0(1):5"/>
+ <v:ud v:nameU="CornerLockDiag" v:prompt="" v:val="VT0(0):5"/>
+ <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.15):1"/>
+ <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.15):1"/>
+ <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.15):1"/>
+ <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.15):1"/>
+ <v:ud v:nameU="visVersion" v:prompt="" v:val="VT0(15):26"/>
+ <v:ud v:nameU="TopLeftOffset" v:prompt="" v:val="VT0(0.057976973684212):1"/>
+ <v:ud v:nameU="TopRightOffset" v:prompt="" v:val="VT0(0.057976973684212):1"/>
+ <v:ud v:nameU="BotLeftOffset" v:prompt="" v:val="VT0(0.057976973684212):1"/>
+ <v:ud v:nameU="BotRightOffset" v:prompt="" v:val="VT0(0.057976973684212):1"/>
+ </v:userDefs>
+ <v:textBlock v:margins="rect(4,4,4,4)"/>
+ <v:textRect cx="39.6563" cy="297.308" width="79.32" height="23.625"/>
+ <path d="M4.17 309.12 L75.14 309.12 A4.17427 4.17427 -180 0 0 79.31 304.95 L79.31 289.67 A4.17427 4.17427 -180 0
+ 0 75.14 285.5 L4.17 285.5 A4.17427 4.17427 -180 0 0 0 289.67 L0 304.95 A4.17427 4.17427 -180 0 0 4.17
+ 309.12 Z" class="st2"/>
+ <text x="17.83" y="300.31" class="st3" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>PEI Drivers</text> </g>
+ <g id="shape398-188" v:mID="398" v:groupContext="shape" transform="translate(15.63,-18.3225)">
+ <title>Sheet.398</title>
+ <desc>PEI Core</desc>
+ <v:textBlock v:margins="rect(4,4,4,4)"/>
+ <v:textRect cx="39.6563" cy="289.151" width="79.32" height="39.9375"/>
+ <rect x="0" y="269.183" width="79.3125" height="39.9375" class="st4"/>
+ <text x="17.62" y="292.4" class="st5" v:langID="1033"><v:paragraph v:spLine="-1" v:horizAlign="1"/><v:tabList/>PEI Core</text> </g>
+ <g id="shape399-191" v:mID="399" v:groupContext="shape" transform="translate(15.63,-71.88)">
+ <title>Sheet.399</title>
+ <desc>DXE Core</desc>
+ <v:textBlock v:margins="rect(4,4,4,4)"/>
+ <v:textRect cx="39.6563" cy="289.151" width="79.32" height="39.9375"/>
+ <rect x="0" y="269.183" width="79.3125" height="39.9375" class="st4"/>
+ <text x="15.25" y="292.4" class="st5" v:langID="1033"><v:paragraph v:spLine="-1" v:horizAlign="1"/><v:tabList/>DXE Core</text> </g>
+ </g>
+ <g id="shape433-194" v:mID="433" v:groupContext="shape" transform="translate(568.808,-70.5)">
+ <title>Rectangle.433</title>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
+ <g id="shadow433-195" v:groupContext="shadow" v:shadowOffsetX="7.2E-008" v:shadowOffsetY="0" v:shadowType="1"
+ v:shadowScale="1.02" transform="matrix(1.02,0,0,1.02,-2.41312,-4.7424)" class="st6">
+ <rect x="0" y="165.12" width="241.313" height="144" class="st7"/>
+ </g>
+ <rect x="0" y="165.12" width="241.313" height="144" class="st20"/>
+ </g>
+ <g id="shape441-199" v:mID="441" v:groupContext="shape" transform="translate(568.808,-214.5)">
+ <title>Rectangle.441</title>
+ <desc>EFI Variable</desc>
+ <v:userDefs>
+ <v:ud v:nameU="visVersion" v:val="VT0(15):26"/>
+ </v:userDefs>
+ <v:textBlock v:margins="rect(4,4,4,4)"/>
+ <v:textRect cx="120.656" cy="293.37" width="241.32" height="31.5"/>
+ <rect x="0" y="277.62" width="241.313" height="31.5" class="st9"/>
+ <text x="86.32" y="297.57" class="st10" v:langID="1033"><v:paragraph v:horizAlign="1"/><v:tabList/>EFI Variable</text> </g>
+ <g id="shape442-202" v:mID="442" v:groupContext="shape" transform="translate(594.99,36.3224) rotate(90)">
+ <title>Sheet.442</title>
+ <path d="M0 309.12 L233.8 309.12" class="st14"/>
+ </g>
+ <g id="shape443-205" v:mID="443" v:groupContext="shape" transform="translate(869.49,36.3224) rotate(90)">
+ <title>Sheet.443</title>
+ <path d="M0 309.12 L233.8 309.12" class="st14"/>
+ </g>
+ <g id="shape444-208" v:mID="444" v:groupContext="shape" transform="translate(1130.49,33.87) rotate(90)">
+ <title>Sheet.444</title>
+ <path d="M0 309.12 L233.8 309.12" class="st14"/>
+ </g>
+ </g>
+</svg>
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 02/30] RISC-V: Add RISC-V PeiCoreEntryPoint library
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 01/30] RISC-V/PlatformPkg: Update document Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 03/30] RISC-V: Create opensbi firmware domains Abner Chang
` (29 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
- Add RISC-V PeiCoreEntryPoint library that incorporates with
opensbi next phase switching mechanism.
- Use RiscVFirmwareContext library to get the pointer of
opensbi FirmwareContext.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 7 +-
.../PeiCoreEntryPoint/PeiCoreEntryPoint.inf | 36 +++++++
.../PeiCoreEntryPoint/PeiCoreEntryPoint.c | 97 +++++++++++++++++++
.../PeiCoreEntryPoint/PeiCoreEntryPoint.uni | 14 +++
4 files changed, 153 insertions(+), 1 deletion(-)
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.uni
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
index 5d9674a965..8eec09549f 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
@@ -1,7 +1,7 @@
#/** @file
# RISC-V platform package.
#
-# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -58,6 +58,10 @@
TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+[LibraryClasses.common.PEI_CORE]
+ # RISC-V platform PEI core entry point.
+ PeiCoreEntryPoint|Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+
[LibraryClasses.common.PEIM]
FirmwareContextProcessorSpecificLib|Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
@@ -77,6 +81,7 @@
Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
+ Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
[Components.common.SEC]
Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
new file mode 100644
index 0000000000..e16a974636
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
@@ -0,0 +1,36 @@
+## @file
+# Module entry point library for PEI core on RISC-V with RISC-V OpenSBI.
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiCoreEntryPoint
+ MODULE_UNI_FILE = PeiCoreEntryPoint.uni
+ FILE_GUID = 2EBF4D2C-99B2-4A09-8C5C-318FB0EF7250
+ MODULE_TYPE = PEI_CORE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PeiCoreEntryPoint|PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ PeiCoreEntryPoint.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ RiscVFirmwareContextLib
+
diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
new file mode 100644
index 0000000000..2fd0f2315b
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
@@ -0,0 +1,97 @@
+/** @file
+ Entry point to a the PEI Core on RISC-V platform with RISC-V OpenSBI.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include <PiPei.h>
+#include <IndustryStandard/RiscVOpensbi.h>
+//
+// The Library classes this module produced
+//
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiCoreEntryPoint.h>
+#include <Library/RiscVFirmwareContextLib.h>
+
+/**
+ The entry point of PE/COFF Image for the PEI Core.
+
+ This function is the entry point for the PEI Foundation, which allows the SEC phase
+ to pass information about the stack, temporary RAM and the Boot Firmware Volume.
+ In addition, it also allows the SEC phase to pass services and data forward for use
+ during the PEI phase in the form of one or more PPIs.
+ There is no limit to the number of additional PPIs that can be passed from SEC into
+ the PEI Foundation. As part of its initialization phase, the PEI Foundation will add
+ these SEC-hosted PPIs to its PPI database such that both the PEI Foundation and any
+ modules can leverage the associated service calls and/or code in these early PPIs.
+ This function is required to call ProcessModuleEntryPointList() with the Context
+ parameter set to NULL. ProcessModuleEntryPoint() is never expected to return.
+ The PEI Core is responsible for calling ProcessLibraryConstructorList() as soon as
+ the PEI Services Table and the file handle for the PEI Core itself have been established.
+ If ProcessModuleEntryPointList() returns, then ASSERT() and halt the system.
+
+ @param SecCoreData This is actually the RISC-V boot HART ID passed in a0 register.
+
+ @param PpiList This is actually the EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT passed
+ in a1 register.
+
+**/
+VOID
+EFIAPI
+_ModuleEntryPoint(
+ IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList
+)
+{
+ EFI_SEC_PEI_HAND_OFF *ThisSecCoreData;
+ EFI_PEI_PPI_DESCRIPTOR *ThisPpiList;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+
+ FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)PpiList;
+ SetFirmwareContextPointer (FirmwareContext);
+ ThisSecCoreData = (EFI_SEC_PEI_HAND_OFF *)FirmwareContext->SecPeiHandOffData;
+ ThisPpiList = (EFI_PEI_PPI_DESCRIPTOR *)FirmwareContext->SecPeiHandoffPpi;
+ ProcessModuleEntryPointList (ThisSecCoreData, ThisPpiList, NULL);
+
+ //
+ // Should never return
+ //
+ ASSERT(FALSE);
+ CpuDeadLoop ();
+}
+
+
+/**
+ Required by the EBC compiler and identical in functionality to _ModuleEntryPoint().
+
+ This function is required to call _ModuleEntryPoint() passing in SecCoreData and PpiList.
+
+ @param SecCoreData Points to a data structure containing information about the PEI core's
+ operating environment, such as the size and location of temporary RAM,
+ the stack location and the BFV location.
+
+ @param PpiList Points to a list of one or more PPI descriptors to be installed
+ initially by the PEI core. An empty PPI list consists of
+ a single descriptor with the end-tag
+ EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST.
+ As part of its initialization phase, the PEI Foundation will
+ add these SEC-hosted PPIs to its PPI database, such that both
+ the PEI Foundationand any modules can leverage the associated
+ service calls and/or code in these early PPIs.
+
+**/
+VOID
+EFIAPI
+EfiMain (
+ IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList
+ )
+{
+ _ModuleEntryPoint (SecCoreData, PpiList);
+}
diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.uni b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.uni
new file mode 100644
index 0000000000..1955b7a05b
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.uni
@@ -0,0 +1,14 @@
+// /** @file
+// Module entry point library for PEI core on RISC-V with RISC-V OpenSBI.
+//
+// Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "RISC-V module entry point library for PEI core"
+
+#string STR_MODULE_DESCRIPTION #language en-US "RISC-V module entry point library for PEI core."
+
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 03/30] RISC-V: Create opensbi firmware domains
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 01/30] RISC-V/PlatformPkg: Update document Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 02/30] RISC-V: Add RISC-V PeiCoreEntryPoint library Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 04/30] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
` (28 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
Incorporate with opensbi to create three firmware domains,
- Boot firmware domain, which built with opensbi library as
M-mode access only region.
- Firmware domain which includes PEI and DXE regions, the
PMP attribute is readable, wriable and executable.
- EFI Variable region which is readable and writable.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 40 ++++-----
.../U540.fdf.inc | 80 +++++++++++++-----
.../VarStore.fdf.inc | 8 +-
.../OpensbiPlatformLib/OpensbiPlatformLib.inf | 9 +-
.../PlatformPkg/Universal/Sec/SecMain.inf | 6 +-
.../Library/OpensbiPlatformLib/Platform.c | 84 ++++++++++++++++---
.../PlatformPkg/Universal/Sec/SecMain.c | 53 +++++-------
.../Universal/Sec/Riscv64/SecEntry.S | 7 +-
8 files changed, 188 insertions(+), 99 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
index ad15a155fe..7e41e7bdb2 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
@@ -1,7 +1,7 @@
## @file RiscVPlatformPkg.dec
# This Package provides UEFI RISC-V platform modules and libraries.
#
-# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -31,33 +31,33 @@
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize|0x0|UINT32|0x00001003
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|0x0|UINT32|0x00001004
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize|0x0|UINT32|0x00001005
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase|0x0|UINT32|0x00001016
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvSize|0x0|UINT32|0x00001017
-
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase|0x0|UINT32|0x00001006
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvSize|0x0|UINT32|0x00001007
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress|0x0|UINT32|0x00001008
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize|0x0|UINT32|0x00001009
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress|0x0|UINT32|0x0000100a
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize|0x0|UINT32|0x0000100b
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress|0x0|UINT32|0x0000100c
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize|0x0|UINT32|0x0000100d
#
# Definition of EFI Variable region
#
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x00001010
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x00001011
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x00001012
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|0|UINT32|0x00001013
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBase|0|UINT32|0x00001014
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|0|UINT32|0x00001015
-#
-# Firmware region which is protected by PMP.
-#
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwBlockSize|0|UINT32|0x00001020
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress|0|UINT32|0x00001021
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress|0|UINT32|0x00001022
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x00001040
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x00001041
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x00001042
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|0|UINT32|0x00001043
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBase|0|UINT32|0x00001044
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|0|UINT32|0x00001045
+
#
# Definition of RISC-V Hart
#
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001023
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001024
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001083
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001084
#
# The bootable hart core number, which is incorporate with OpenSBI platform hart_index2id value.
#
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber|0|UINT32|0x00001025
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber|0|UINT32|0x00001085
#
# Definitions for OpenSbi
#
@@ -73,7 +73,7 @@
[PcdsPatchableInModule]
[PcdsFeatureFlag]
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|0x00001006
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|0x00001200
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
index 8e7afc2d82..f708f4d8be 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
@@ -1,7 +1,7 @@
## @file
# Definitions of Flash definition file on SiFive Freedom U540 HiFive Unleashed RISC-V platform
#
-# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -10,37 +10,77 @@
DEFINE BLOCK_SIZE = 0x1000
DEFINE FW_BASE_ADDRESS = 0x80000000
-DEFINE FW_SIZE = 0x00820000
-DEFINE FW_BLOCKS = 0x820
+DEFINE FW_SIZE = 0x00900000
+DEFINE FW_BLOCKS = 0x900
#
# 0x000000-0x7DFFFF code
# 0x7E0000-0x800000 variables
#
DEFINE CODE_BASE_ADDRESS = 0x80000000
-DEFINE CODE_SIZE = 0x007E0000
-DEFINE CODE_BLOCKS = 0x7E0
+DEFINE CODE_SIZE = 0x00800000
+DEFINE CODE_BLOCKS = 0x800
DEFINE VARS_BLOCKS = 0x20
-DEFINE SECFV_OFFSET = 0x00000000
-DEFINE SECFV_SIZE = 0x00030000
-DEFINE PEIFV_OFFSET = 0x00030000
-DEFINE PEIFV_SIZE = 0x00080000
-DEFINE SCRATCH_OFFSET = 0x000b0000
-DEFINE SCRATCH_SIZE = 0x00010000
-DEFINE FVMAIN_OFFSET = 0x00100000 # Must be power of 2 for PMP setting
-DEFINE FVMAIN_SIZE = 0x0018C000
-DEFINE VARS_OFFSET = 0x007E0000
-DEFINE VARS_SIZE = 0x00020000
-DEFINE DTB_OFFSET = 0x00800000
-DEFINE DTB_SIZE = 0x00002000
+#
+# SEC + opensbi library is the root FW domain.
+# The base address must be round up to log2.
+#
+DEFINE SECFV_OFFSET = 0x00000000
+DEFINE SECFV_SIZE = 0x00040000
+DEFINE ROOT_FW_DOMAIN_SIZE = $(SECFV_SIZE)
+
+#
+# Other FV regions are in the second FW domain.
+# The size of memory region must be power of 2.
+# The base address must be aligned with the size.
+#
+# FW memory region
+#
+DEFINE PEIFV_OFFSET = 0x00400000
+DEFINE PEIFV_SIZE = 0x00180000
+DEFINE FVMAIN_OFFSET = 0x00580000
+DEFINE FVMAIN_SIZE = 0x00280000
+
+#
+# EFI Variable memory region.
+# The total size of EFI Variable FD must include
+# all of sub regions of EFI Variable
+#
+DEFINE VARS_OFFSET = 0x00800000
+DEFINE VARS_SIZE = 0x00007000
+DEFINE VARS_FTW_WORKING_OFFSET = 0x00807000
+DEFINE VARS_FTW_WORKING_SIZE = 0x00001000
+DEFINE VARS_FTW_SPARE_OFFSET = 0x00808000
+DEFINE VARS_FTW_SPARE_SIZE = 0x00018000
+
+#
+# Device Tree memory region
+#
+DEFINE DTB_OFFSET = 0x00840000
+DEFINE DTB_SIZE = 0x00002000
+
+#
+# Scratch area memory region
+#
+DEFINE SCRATCH_OFFSET = 0x00880000
+DEFINE SCRATCH_SIZE = 0x00010000
+
+
+DEFINE FW_DOMAIN_SIZE = $(FVMAIN_OFFSET) + $(FVMAIN_SIZE) - $(PEIFV_OFFSET)
+DEFINE VARIABLE_FW_SIZE = $(VARS_FTW_SPARE_OFFSET) + $(VARS_FTW_SPARE_SIZE) - $(VARS_OFFSET)
+
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress = $(CODE_BASE_ADDRESS) + $(SECFV_OFFSET)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize = $(ROOT_FW_DOMAIN_SIZE)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress = $(CODE_BASE_ADDRESS) + $(PEIFV_OFFSET)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize = $(FW_DOMAIN_SIZE)
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress = $(FW_BASE_ADDRESS) + $(VARS_OFFSET)
-SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize = $(VARS_SIZE)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize = $(VARS_SIZE) + $(VARS_FTW_WORKING_SIZE) + $(VARS_FTW_SPARE_SIZE)
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize = $(BLOCK_SIZE)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress = $(CODE_BASE_ADDRESS) + $(VARS_OFFSET)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize = $(VARIABLE_FW_SIZE)
-SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress = $(CODE_BASE_ADDRESS)
-SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress = $(CODE_BASE_ADDRESS) + $(SECFV_SIZE) + $(PEIFV_SIZE) + $(SCRATCH_SIZE) + $(DTB_SIZE)
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize = 8192
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase = $(CODE_BASE_ADDRESS) + $(SCRATCH_OFFSET)
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize = $(SCRATCH_SIZE)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/VarStore.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/VarStore.fdf.inc
index c287bb4336..04bddfaa44 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/VarStore.fdf.inc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/VarStore.fdf.inc
@@ -1,7 +1,7 @@
## @file
# FDF include file with Layout Regions that define an empty variable store.
#
-# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
# Copyright (C) 2014, Red Hat, Inc.
# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
#
@@ -9,7 +9,7 @@
#
##
-$(VARS_OFFSET)|0x00007000
+$(VARS_OFFSET)|$(VARS_SIZE)
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
#
# NV_VARIABLE_STORE
@@ -56,7 +56,7 @@ DATA = {
0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}
-0x007e7000|0x00001000
+$(VARS_FTW_WORKING_OFFSET)|$(VARS_FTW_WORKING_SIZE)
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
#
#NV_FTW_WROK
@@ -72,7 +72,7 @@ DATA = {
0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}
-0x007e8000|0x00018000
+$(VARS_FTW_SPARE_OFFSET)|$(VARS_FTW_SPARE_SIZE)
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
#
#NV_FTW_SPARE
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
index f9f2073a5b..a408737961 100644
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
@@ -3,7 +3,7 @@
# This is the the library which provides platform
# level opensbi functions follow RISC-V OpenSBI implementation.
#
-# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -54,3 +54,10 @@
gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase
gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock
+
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
index 78bd75e3ac..bcb8b9f908 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
@@ -1,7 +1,7 @@
## @file
# RISC-V SEC module.
#
-# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -64,8 +64,8 @@
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
index c4cf6782bd..4fbb201895 100644
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
@@ -1,7 +1,7 @@
/*
* SPDX-License-Identifier: BSD-2-Clause
*
- * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
*
* Authors:
* Anup Patel <anup.patel@wdc.com>
@@ -10,6 +10,7 @@
#include <libfdt.h>
#include <PlatformOverride.h>
#include <sbi/riscv_asm.h>
+#include <sbi/sbi_domain.h>
#include <sbi/sbi_hartmask.h>
#include <sbi/sbi_platform.h>
#include <sbi/sbi_string.h>
@@ -185,20 +186,77 @@ static u64 generic_tlbr_flush_limit(void)
return SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT;
}
+static int generic_system_reset_check(u32 reset_type, u32 reset_reason)
+{
+ if (generic_plat && generic_plat->system_reset_check)
+ return generic_plat->system_reset_check(reset_type,
+ reset_reason,
+ generic_plat_match);
+ return fdt_system_reset_check(reset_type, reset_reason);
+}
+
+static void generic_system_reset(u32 reset_type, u32 reset_reason)
+{
+ if (generic_plat && generic_plat->system_reset) {
+ generic_plat->system_reset(reset_type, reset_reason,
+ generic_plat_match);
+ return;
+ }
+
+ fdt_system_reset(reset_type, reset_reason);
+}
+
+#define EDK2_ROOT_FW_REGION 0
+#define EDK2_FW_REGION 1
+#define EDK2_VARIABLE_REGION 2
+#define EDK2_ALL_REGION 3
+#define EDK2_END_REGION 4
+static struct sbi_domain_memregion root_memregs[EDK2_END_REGION + 1] = { 0 };
+
+struct sbi_domain_memregion *get_mem_regions(void) {
+ /* EDK2 root firmware domain memory region */
+ root_memregs[EDK2_ROOT_FW_REGION].order = log2roundup(FixedPcdGet32(PcdRootFirmwareDomainSize));
+ root_memregs[EDK2_ROOT_FW_REGION].base = FixedPcdGet32(PcdRootFirmwareDomainBaseAddress);
+ root_memregs[EDK2_ROOT_FW_REGION].flags = 0;
+
+ /*EDK2 firmware domain memory region */
+ root_memregs[EDK2_FW_REGION].order = log2roundup(FixedPcdGet32(PcdFirmwareDomainSize));
+ root_memregs[EDK2_FW_REGION].base = FixedPcdGet32(PcdFirmwareDomainBaseAddress);
+ root_memregs[EDK2_FW_REGION].flags = SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREGION_READABLE;
+
+ /*EDK2 firmware domain memory region */
+ root_memregs[EDK2_VARIABLE_REGION].order = log2roundup(FixedPcdGet32(PcdVariableFirmwareRegionSize));
+ root_memregs[EDK2_VARIABLE_REGION].base = FixedPcdGet32(PcdVariableFirmwareRegionBaseAddress);
+ root_memregs[EDK2_VARIABLE_REGION].flags = SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGION_WRITEABLE;
+
+ /* EDK2 domain allow everything memory region */
+ root_memregs[EDK2_ALL_REGION].order = __riscv_xlen;
+ root_memregs[EDK2_ALL_REGION].base = 0;
+ root_memregs[EDK2_ALL_REGION].flags = (SBI_DOMAIN_MEMREGION_READABLE |
+ SBI_DOMAIN_MEMREGION_WRITEABLE |
+ SBI_DOMAIN_MEMREGION_EXECUTABLE);
+
+ /* EDK2 domain memory region end */
+ root_memregs[EDK2_END_REGION].order = 0;
+
+ return root_memregs;
+}
+
const struct sbi_platform_operations platform_ops = {
- .early_init = generic_early_init,
- .final_init = generic_final_init,
- .early_exit = generic_early_exit,
- .final_exit = generic_final_exit,
- .domains_init = generic_domains_init,
- .console_init = fdt_serial_init,
- .irqchip_init = fdt_irqchip_init,
- .irqchip_exit = fdt_irqchip_exit,
- .ipi_init = fdt_ipi_init,
- .ipi_exit = fdt_ipi_exit,
+ .early_init = generic_early_init,
+ .final_init = generic_final_init,
+ .early_exit = generic_early_exit,
+ .final_exit = generic_final_exit,
+ .domains_root_regions = get_mem_regions,
+ .domains_init = generic_domains_init,
+ .console_init = fdt_serial_init,
+ .irqchip_init = fdt_irqchip_init,
+ .irqchip_exit = fdt_irqchip_exit,
+ .ipi_init = fdt_ipi_init,
+ .ipi_exit = fdt_ipi_exit,
.get_tlbr_flush_limit = generic_tlbr_flush_limit,
- .timer_init = fdt_timer_init,
- .timer_exit = fdt_timer_exit,
+ .timer_init = fdt_timer_init,
+ .timer_exit = fdt_timer_exit,
};
#if FixedPcdGet32(PcdBootableHartNumber) == 4
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index e9f030f352..e88a7b8e80 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -1,7 +1,7 @@
/** @file
RISC-V SEC phase module.
- Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -336,7 +336,7 @@ FindAndReportEntryPoints (
**/
VOID
-DebutPrintFirmwareContext (
+DebugPrintFirmwareContext (
EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext
)
{
@@ -398,7 +398,7 @@ TemporaryRamMigration (
//
FirmwareContext->PeiServiceTable += (unsigned long)((UINTN)NewStack - (UINTN)OldStack);
DEBUG ((DEBUG_INFO, "%a: OpenSBI Firmware Context is relocated to 0x%x\n", __FUNCTION__, FirmwareContext));
- DebutPrintFirmwareContext ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)FirmwareContext);
+ DebugPrintFirmwareContext ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)FirmwareContext);
register uintptr_t a0 asm ("a0") = (uintptr_t)((UINTN)NewStack - (UINTN)OldStack);
asm volatile ("add sp, sp, a0"::"r"(a0):);
@@ -496,12 +496,12 @@ RegisterFirmwareSbiExtension (
This function transits to S-mode PEI phase from M-mode SEC phase.
@param[in] BootHartId Hardware thread ID of boot hart.
- @param[in] FuncArg1 Arg1 delivered from previous phase.
+ @param[in] Scratch Pointer to sbi_scratch structure.
**/
VOID EFIAPI PeiCore (
- IN UINTN BootHartId,
- IN UINTN FuncArg1
+ IN UINTN BootHartId,
+ IN struct sbi_scratch *Scratch
)
{
EFI_SEC_PEI_HAND_OFF SecCoreData;
@@ -529,7 +529,7 @@ VOID EFIAPI PeiCore (
//
DEBUG ((DEBUG_INFO, "%a: OpenSBI scratch address for each hart:\n", __FUNCTION__));
for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
- SbiGetMscratchHartid (HartId, &ScratchSpace);
+ ScratchSpace = sbi_hartid_to_scratch (HartId);
if(ScratchSpace != NULL) {
DEBUG((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, ScratchSpace));
}
@@ -540,9 +540,8 @@ VOID EFIAPI PeiCore (
// Firmware context residents in stack and will be switched to memory when
// temporary RAM migration.
//
- SbiGetMscratchHartid (BootHartId, &ScratchSpace);
ZeroMem ((VOID *)&FirmwareContext, sizeof (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT));
- ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(ScratchSpace);
+ ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(Scratch);
if (ThisSbiPlatform->opensbi_version > OPENSBI_VERSION) {
DEBUG ((DEBUG_ERROR, "%a: OpenSBI platform table version 0x%x is newer than OpenSBI version 0x%x.\n"
"There maybe be some backward compatable issues.\n",
@@ -562,13 +561,13 @@ VOID EFIAPI PeiCore (
//
// Save Flattened Device tree in firmware context
//
- FirmwareContext.FlattenedDeviceTree = FuncArg1;
+ FirmwareContext.FlattenedDeviceTree = Scratch->next_arg1;
//
// Set firmware context Hart-specific pointer
//
for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
- SbiGetMscratchHartid (HartId, &ScratchSpace);
+ ScratchSpace = sbi_hartid_to_scratch (HartId);
if (ScratchSpace != NULL) {
FirmwareContext.HartSpecific[HartId] =
(EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)ScratchSpace - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE);
@@ -588,6 +587,10 @@ VOID EFIAPI PeiCore (
//
// Transfer the control to the PEI core
//
+ Scratch->next_addr = (UINTN)(*PeiCoreEntryPoint);
+ Scratch->next_mode = PRV_S;
+ DEBUG ((DEBUG_INFO, "%a: Initializing OpenSBI library for booting hart %d\n", __FUNCTION__, BootHartId));
+ sbi_init(Scratch);
(*PeiCoreEntryPoint) (&SecCoreData, (EFI_PEI_PPI_DESCRIPTOR *)&mPrivateDispatchTable);
}
@@ -598,34 +601,19 @@ VOID EFIAPI PeiCore (
To register the SBI extension we stay in M-Mode and then transition here,
rather than before in sbi_init.
- @param[in] ThisHartId Hardware thread ID.
- @param[in] FuncArg1 Arg1 delivered from previous phase.
+ @param[in] ThisHartId Hardware thread ID.
+ @param[in] Scratch Pointer to sbi_scratch structure.
**/
VOID
EFIAPI
LaunchPeiCore (
IN UINTN ThisHartId,
- IN UINTN FuncArg1
+ IN struct sbi_scratch *Scratch
)
{
- UINT32 PeiCoreMode;
-
- DEBUG ((DEBUG_INFO, "%a: Set boot hart done.\n", __FUNCTION__));
- atomic_write (&BootHartDone, (UINT64)TRUE);
RegisterFirmwareSbiExtension ();
-
- PeiCoreMode = FixedPcdGet32 (PcdPeiCorePrivilegeMode);
- if (PeiCoreMode == PRV_S) {
- DEBUG ((DEBUG_INFO, "%a: Switch to S-Mode for PeiCore.\n", __FUNCTION__));
- sbi_hart_switch_mode (ThisHartId, FuncArg1, (UINTN)PeiCore, PRV_S, FALSE);
- } else if (PeiCoreMode == PRV_M) {
- DEBUG ((DEBUG_INFO, "%a: Switch to M-Mode for PeiCore.\n", __FUNCTION__));
- PeiCore (ThisHartId, FuncArg1);
- } else {
- DEBUG ((DEBUG_INFO, "%a: The privilege mode specified in PcdPeiCorePrivilegeMode is not supported.\n", __FUNCTION__));
- while (TRUE);
- }
+ PeiCore (ThisHartId, Scratch);
}
/**
@@ -750,10 +738,7 @@ VOID EFIAPI SecCoreStartUpWithStack(
HartFirmwareContext->HartSwitchMode = RiscVOpenSbiHartSwitchMode;
if (HartId == FixedPcdGet32(PcdBootHartId)) {
- Scratch->next_addr = (UINTN)LaunchPeiCore;
- Scratch->next_mode = PRV_M;
- DEBUG ((DEBUG_INFO, "%a: Initializing OpenSBI library for booting hart %d\n", __FUNCTION__, HartId));
- sbi_init(Scratch);
+ LaunchPeiCore (HartId, Scratch);
}
//
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
index a8157c896e..0a69c50065 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 , Hewlett Packard Enterprise Development LP. All rights reserved.
+ * Copyright (c) 2021 , Hewlett Packard Enterprise Development LP. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause
*
@@ -71,9 +71,8 @@ _scratch_init:
/* Initialize scratch space */
/* Firmware range and size */
- li a4, FixedPcdGet32 (PcdFwStartAddress)
- li a5, FixedPcdGet32 (PcdFwEndAddress)
- sub a5, a5, a4
+ li a4, FixedPcdGet32 (PcdRootFirmwareDomainBaseAddress)
+ li a5, FixedPcdGet32 (PcdRootFirmwareDomainSize)
sd a4, SBI_SCRATCH_FW_START_OFFSET(tp)
sd a5, SBI_SCRATCH_FW_SIZE_OFFSET(tp)
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 04/30] RISC-V: Use RISC-V PeiCoreEntryPoint library
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (2 preceding siblings ...)
2021-10-19 8:09 ` [edk2-platforms][PATCH 03/30] RISC-V: Create opensbi firmware domains Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 05/30] Platform/RISC-V: Add library to get PPI descriptor Abner Chang
` (27 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
1. Use RISC-V PeiCoreEntryPoint library instance for opensbi
to switch to the next phase with arg0 as HART Id and arg1
as the SEC to PEI handoff data.
2. Introduce EDK2 opensbi platform operation functions.
With this, OEM can has its won platform initialization code
before and/or after opensbi vendor platform functions.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../FreedomU540HiFiveUnleashedBoard/U540.dsc | 3 +-
.../PlatformPkg/Universal/Sec/SecMain.inf | 2 +
.../PlatformPkg/Universal/Sec/SecMain.h | 10 +
.../Include/IndustryStandard/RiscVOpensbi.h | 8 +-
.../Universal/Sec/Edk2OpenSbiPlatform.c | 426 ++++++++++++++++++
.../PlatformPkg/Universal/Sec/SecMain.c | 152 +++++--
6 files changed, 547 insertions(+), 54 deletions(-)
create mode 100644 Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
index 5d2ccafaca..be23fc39fd 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
@@ -181,7 +181,6 @@
RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
- PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
@@ -191,6 +190,8 @@
DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
!endif
PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ # RISC-V platform PEI core entry point.
+ PeiCoreEntryPoint|Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
[LibraryClasses.common.PEIM]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
index bcb8b9f908..4207c83413 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
@@ -23,11 +23,13 @@
[Sources]
SecMain.c
+ Edk2OpenSbiPlatform.c
[Sources.RISCV64]
Riscv64/SecEntry.S
[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
index 94ea46263c..c04ddbad7f 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
@@ -28,6 +28,16 @@
#include <Ppi/TemporaryRamDone.h>
#include <Ppi/TemporaryRamSupport.h>
+int
+SecPostOpenSbiPlatformEarlylInit(
+ IN BOOLEAN ColdBoot
+ );
+
+int
+SecPostOpenSbiPlatformFinalInit (
+ IN BOOLEAN ColdBoot
+ );
+
VOID
SecMachineModeTrapHandler (
IN VOID
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
index e7ac6d26ee..d639429306 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscVOpensbi.h
@@ -1,7 +1,7 @@
/** @file
SBI inline function calls.
- Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -46,8 +46,10 @@ typedef struct {
// structure. Referred by both C code and assembly code.
typedef struct {
- VOID *PeiServiceTable; // PEI Service table
- UINT64 FlattenedDeviceTree; // Pointer to Flattened Device tree
+ UINT64 BootHartId;
+ VOID *PeiServiceTable; // PEI Service table
+ UINT64 FlattenedDeviceTree; // Pointer to Flattened Device tree
+ UINT64 SecPeiHandOffData; // This is EFI_SEC_PEI_HAND_OFF passed to PEI Core.
EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_SUPPORTED];
} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c
new file mode 100644
index 0000000000..79b2f33675
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c
@@ -0,0 +1,426 @@
+/*
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ */
+
+#include <Library/DebugAgentLib.h>
+#include <Library/DebugLib.h>
+
+#include <libfdt.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_domain.h>
+#include <sbi/sbi_hartmask.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_string.h>
+#include <sbi/sbi_math.h>
+#include <sbi_utils/fdt/fdt_domain.h>
+#include <sbi_utils/fdt/fdt_fixup.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/irqchip/fdt_irqchip.h>
+#include <sbi_utils/serial/fdt_serial.h>
+#include <sbi_utils/timer/fdt_timer.h>
+#include <sbi_utils/ipi/fdt_ipi.h>
+#include <sbi_utils/reset/fdt_reset.h>
+
+#include "SecMain.h"
+
+extern struct sbi_platform_operations platform_ops;
+
+int Edk2OpensbiPlatformEarlyInit (
+ BOOLEAN ColdBoot
+ )
+{
+ int ReturnCode;
+
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.early_init) {
+ ReturnCode = platform_ops.early_init (ColdBoot);
+ if (ReturnCode) {
+ return ReturnCode;
+ }
+ }
+ if (ColdBoot == TRUE) {
+ return SecPostOpenSbiPlatformEarlylInit(ColdBoot);
+ }
+ return 0;
+}
+
+int Edk2OpensbiPlatformFinalInit (
+ BOOLEAN ColdBoot
+ )
+{
+ int ReturnCode;
+
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.final_init) {
+ ReturnCode = platform_ops.final_init (ColdBoot);
+ if (ReturnCode) {
+ return ReturnCode;
+ }
+ }
+ if (ColdBoot == TRUE) {
+ return SecPostOpenSbiPlatformFinalInit(ColdBoot);
+ }
+ return 0;
+}
+
+VOID Edk2OpensbiPlatformEarlyExit (
+ VOID
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.early_exit) {
+ return platform_ops.early_exit ();
+ }
+}
+
+/** Platform final exit */
+VOID Edk2OpensbiPlatformFinalExit (
+ VOID
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.early_exit) {
+ return platform_ops.early_exit ();
+ }
+}
+
+/**
+ For platforms that do not implement misa, non-standard
+ methods are needed to determine cpu extension.
+**/
+int Edk2OpensbiPlatforMMISACheckExtension (
+ CHAR8 Extension
+ )
+{
+ if (platform_ops.misa_check_extension) {
+ return platform_ops.misa_check_extension (Extension);
+ }
+ return 0;
+}
+
+/**
+ For platforms that do not implement misa, non-standard
+ methods are needed to get MXL field of misa.
+**/
+int Edk2OpensbiPlatforMMISAGetXLEN (VOID)
+{
+ if (platform_ops.misa_get_xlen) {
+ return platform_ops.misa_get_xlen ();
+ }
+ return 0;
+}
+
+/** Get platform specific root domain memory regions */
+struct sbi_domain_memregion *
+Edk2OpensbiPlatformGetMemRegions (VOID)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.domains_root_regions) {
+ return platform_ops.domains_root_regions ();
+ }
+ return 0;
+}
+
+/** Initialize (or populate) domains for the platform */
+int Edk2OpensbiPlatformDomainsInit (VOID)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.domains_init) {
+ return platform_ops.domains_init ();
+ }
+ return 0;
+}
+
+/** Write a character to the platform console output */
+VOID Edk2OpensbiPlatformSerialPutc (
+ CHAR8 Ch
+ )
+{
+ if (platform_ops.console_putc) {
+ return platform_ops.console_putc (Ch);
+ }
+}
+
+/** Read a character from the platform console input */
+int Edk2OpensbiPlatformSerialGetc (VOID)
+{
+ if (platform_ops.console_getc) {
+ return platform_ops.console_getc ();
+ }
+ return 0;
+}
+
+/** Initialize the platform console */
+int Edk2OpensbiPlatformSerialInit (VOID)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.console_init) {
+ return platform_ops.console_init ();
+ }
+ return 0;
+}
+
+/** Initialize the platform interrupt controller for current HART */
+int Edk2OpensbiPlatformIrqchipInit (
+ BOOLEAN ColdBoot
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.irqchip_init) {
+ return platform_ops.irqchip_init (ColdBoot);
+ }
+ return 0;
+}
+
+/** Exit the platform interrupt controller for current HART */
+VOID Edk2OpensbiPlatformIrqchipExit (VOID)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.irqchip_exit) {
+ return platform_ops.irqchip_exit ();
+ }
+}
+
+/** Send IPI to a target HART */
+VOID Edk2OpensbiPlatformIpiSend (
+ UINT32 TargetHart
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.ipi_send) {
+ return platform_ops.ipi_send (TargetHart);
+ }
+}
+
+/** Clear IPI for a target HART */
+VOID Edk2OpensbiPlatformIpiClear (
+ UINT32 TargetHart
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.ipi_clear) {
+ return platform_ops.ipi_clear (TargetHart);
+ }
+}
+
+/** Initialize IPI for current HART */
+int Edk2OpensbiPlatformIpiInit (
+ BOOLEAN ColdBoot
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.ipi_init) {
+ return platform_ops.ipi_init (ColdBoot);
+ }
+ return 0;
+}
+
+/** Exit IPI for current HART */
+VOID Edk2OpensbiPlatformIpiExit (VOID)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.ipi_exit) {
+ return platform_ops.ipi_exit ();
+ }
+}
+
+/** Get tlb flush limit value **/
+UINT64 Edk2OpensbiPlatformTlbrFlushLimit (VOID)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.get_tlbr_flush_limit) {
+ return platform_ops.get_tlbr_flush_limit ();
+ }
+ return 0;
+}
+
+/** Get platform timer value */
+UINT64 Edk2OpensbiPlatformTimerValue (VOID)
+{
+ if (platform_ops.timer_value) {
+ return platform_ops.timer_value ();
+ }
+ return 0;
+}
+
+/** Start platform timer event for current HART */
+VOID Edk2OpensbiPlatformTimerEventStart (
+ UINT64 NextEvent
+ )
+{
+ if (platform_ops.timer_event_start) {
+ return platform_ops.timer_event_start (NextEvent);
+ }
+}
+
+/** Stop platform timer event for current HART */
+VOID Edk2OpensbiPlatformTimerEventStop (VOID)
+{
+ if (platform_ops.timer_event_stop) {
+ return platform_ops.timer_event_stop ();
+ }
+}
+
+/** Initialize platform timer for current HART */
+int Edk2OpensbiPlatformTimerInit (
+ BOOLEAN ColdBoot
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.timer_init) {
+ return platform_ops.timer_init (ColdBoot);
+ }
+ return 0;
+}
+
+/** Exit platform timer for current HART */
+VOID Edk2OpensbiPlatformTimerExit (VOID)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.timer_exit) {
+ return platform_ops.timer_exit ();
+ }
+}
+
+/** Bringup the given hart */
+int Edk2OpensbiPlatformHartStart (
+ UINT32 HartId,
+ ulong Saddr
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.hart_start) {
+ return platform_ops.hart_start (HartId, Saddr);
+ }
+ return 0;
+}
+/**
+ Stop the current hart from running. This call doesn't expect to
+ return if success.
+**/
+int Edk2OpensbiPlatformHartStop (VOID)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.hart_stop) {
+ return platform_ops.hart_stop ();
+ }
+ return 0;
+}
+
+/**
+ Check whether reset type and reason supported by the platform*
+
+**/
+int Edk2OpensbiPlatformSystemResetCheck (
+ UINT32 ResetType,
+ UINT32 ResetReason
+ )
+{
+ if (platform_ops.system_reset_check) {
+ return platform_ops.system_reset_check (ResetType, ResetReason);
+ }
+ return 0;
+}
+
+/** Reset the platform */
+VOID Edk2OpensbiPlatformSystemReset (
+ UINT32 ResetType,
+ UINT32 ResetReason
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.system_reset) {
+ return platform_ops.system_reset (ResetType, ResetReason);
+ }
+}
+
+/** platform specific SBI extension implementation probe function */
+int Edk2OpensbiPlatformVendorExtCheck (
+ long ExtId
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.vendor_ext_check) {
+ return platform_ops.vendor_ext_check (ExtId);
+ }
+ return 0;
+}
+
+
+/** platform specific SBI extension implementation provider */
+int Edk2OpensbiPlatformVendorExtProvider (
+ long ExtId,
+ long FuncId,
+ const struct sbi_trap_regs *Regs,
+ unsigned long *OutValue,
+ struct sbi_trap_info *OutTrap
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.vendor_ext_provider) {
+ return platform_ops.vendor_ext_provider (
+ ExtId,
+ FuncId,
+ Regs,
+ OutValue,
+ OutTrap
+ );
+ }
+ return 0;
+}
+
+const struct sbi_platform_operations Edk2OpensbiPlatformOps = {
+ .early_init = Edk2OpensbiPlatformEarlyInit,
+ .final_init = Edk2OpensbiPlatformFinalInit,
+ .early_exit = Edk2OpensbiPlatformEarlyExit,
+ .final_exit = Edk2OpensbiPlatformFinalExit,
+ .misa_check_extension = Edk2OpensbiPlatforMMISACheckExtension,
+ .misa_get_xlen = Edk2OpensbiPlatforMMISAGetXLEN,
+ .domains_root_regions = Edk2OpensbiPlatformGetMemRegions,
+ .domains_init = Edk2OpensbiPlatformDomainsInit,
+ .console_putc = Edk2OpensbiPlatformSerialPutc,
+ .console_getc = Edk2OpensbiPlatformSerialGetc,
+ .console_init = Edk2OpensbiPlatformSerialInit,
+ .irqchip_init = Edk2OpensbiPlatformIrqchipInit,
+ .irqchip_exit = Edk2OpensbiPlatformIrqchipExit,
+ .ipi_send = Edk2OpensbiPlatformIpiSend,
+ .ipi_clear = Edk2OpensbiPlatformIpiClear,
+ .ipi_init = Edk2OpensbiPlatformIpiInit,
+ .ipi_exit = Edk2OpensbiPlatformIpiExit,
+ .get_tlbr_flush_limit = Edk2OpensbiPlatformTlbrFlushLimit,
+ .timer_value = Edk2OpensbiPlatformTimerValue,
+ .timer_event_stop = Edk2OpensbiPlatformTimerEventStop,
+ .timer_event_start = Edk2OpensbiPlatformTimerEventStart,
+ .timer_init = Edk2OpensbiPlatformTimerInit,
+ .timer_exit = Edk2OpensbiPlatformTimerExit,
+ .hart_start = Edk2OpensbiPlatformHartStart,
+ .hart_stop = Edk2OpensbiPlatformHartStop,
+ .system_reset_check = Edk2OpensbiPlatformSystemResetCheck,
+ .system_reset = Edk2OpensbiPlatformSystemReset,
+ .vendor_ext_check = Edk2OpensbiPlatformVendorExtCheck,
+ .vendor_ext_provider = Edk2OpensbiPlatformVendorExtProvider,
+};
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index e88a7b8e80..44984b0078 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -23,6 +23,8 @@
#include <sbi/sbi_ecall.h> // Reference to header file in opensbi
#include <sbi/sbi_trap.h> // Reference to header file in opensbi
+extern struct sbi_platform_operations Edk2OpensbiPlatformOps;
+
//
// Indicates the boot hart (PcdBootHartId) OpenSBI initialization is done.
//
@@ -31,27 +33,6 @@ atomic_t NonBootHartMessageLock = ATOMIC_INITIALIZER(0);
typedef struct sbi_scratch *(*hartid2scratch)(ulong hartid, ulong hartindex);
-STATIC EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = {
- TemporaryRamMigration
-};
-
-STATIC EFI_PEI_TEMPORARY_RAM_DONE_PPI mTemporaryRamDonePpi = {
- TemporaryRamDone
-};
-
-STATIC EFI_PEI_PPI_DESCRIPTOR mPrivateDispatchTable[] = {
- {
- EFI_PEI_PPI_DESCRIPTOR_PPI,
- &gEfiTemporaryRamSupportPpiGuid,
- &mTemporaryRamSupportPpi
- },
- {
- (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
- &gEfiTemporaryRamDonePpiGuid,
- &mTemporaryRamDonePpi
- },
-};
-
/**
Locates a section within a series of sections
with the specified section type.
@@ -491,6 +472,91 @@ RegisterFirmwareSbiExtension (
return EFI_SUCCESS;
}
+
+/**
+ OpenSBI platform early init hook.
+
+**/
+int
+SecPostOpenSbiPlatformEarlylInit(
+ IN BOOLEAN ColdBoot
+ )
+{
+ //
+ // Boot HART is already in the process of OpenSBI initialization.
+ // We can let other HART to keep booting.
+ //
+ DEBUG ((DEBUG_INFO, "%a: Set boot hart done.\n", __FUNCTION__));
+ atomic_write (&BootHartDone, (UINT64)TRUE);
+ return 0;
+}
+
+/**
+ OpenSBI platform final init hook.
+ We restore the next_arg1 to the pointer of EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT.
+
+**/
+int
+SecPostOpenSbiPlatformFinalInit (
+ IN BOOLEAN ColdBoot
+ )
+{
+ UINT32 HartId;
+ struct sbi_scratch *SbiScratch;
+ struct sbi_scratch *ScratchSpace;
+ struct sbi_platform *SbiPlatform;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+
+ DEBUG((DEBUG_INFO, "%a: Entry, preparing to jump to PEI Core\n\n", __FUNCTION__));
+
+ SbiScratch = sbi_scratch_thishart_ptr();
+ SbiPlatform = (struct sbi_platform *)sbi_platform_ptr(SbiScratch);
+ FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)SbiPlatform->firmware_context;
+
+ //
+ // Print out scratch address of each hart
+ //
+ DEBUG ((DEBUG_INFO, "%a: OpenSBI scratch address for each hart:\n", __FUNCTION__));
+ for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
+ if (sbi_platform_hart_invalid(SbiPlatform, HartId)) {
+ continue;
+ }
+ ScratchSpace = sbi_hartid_to_scratch (HartId);
+ if(ScratchSpace != NULL) {
+ DEBUG((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, ScratchSpace));
+ } else {
+ DEBUG((DEBUG_INFO, " Hart %d not initialized yet\n", HartId));
+ }
+ }
+
+ //
+ // Set firmware context Hart-specific pointer
+ //
+ for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
+ if (sbi_platform_hart_invalid(SbiPlatform, HartId)) {
+ continue;
+ }
+ ScratchSpace = sbi_hartid_to_scratch (HartId);
+ if (ScratchSpace != NULL) {
+ FirmwareContext->HartSpecific[HartId] =
+ (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)ScratchSpace - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE);
+ DEBUG ((DEBUG_INFO, "%a: OpenSBI Hart %d Firmware Context Hart-specific at address: 0x%x\n",
+ __FUNCTION__,
+ HartId,
+ FirmwareContext->HartSpecific [HartId]
+ ));
+ }
+ }
+
+ DEBUG((DEBUG_INFO, "%a: Jump to PEI Core with \n", __FUNCTION__));
+ DEBUG((DEBUG_INFO, " sbi_scratch = %x\n", SbiScratch));
+ DEBUG((DEBUG_INFO, " sbi_platform = %x\n", SbiPlatform));
+ DEBUG((DEBUG_INFO, " FirmwareContext = %x\n", FirmwareContext));
+ SbiScratch->next_arg1 = (unsigned long)FirmwareContext;
+
+ return 0;
+}
+
/** Transion from SEC phase to PEI phase.
This function transits to S-mode PEI phase from M-mode SEC phase.
@@ -508,9 +574,7 @@ VOID EFIAPI PeiCore (
EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint;
EFI_FIRMWARE_VOLUME_HEADER *BootFv = (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32(PcdRiscVPeiFvBase);
EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT FirmwareContext;
- struct sbi_scratch *ScratchSpace;
struct sbi_platform *ThisSbiPlatform;
- UINT32 HartId;
FindAndReportEntryPoints (&BootFv, &PeiCoreEntryPoint);
@@ -524,17 +588,6 @@ VOID EFIAPI PeiCore (
SecCoreData.StackBase = (UINT8 *)SecCoreData.TemporaryRamBase + (SecCoreData.TemporaryRamSize >> 1);
SecCoreData.StackSize = SecCoreData.TemporaryRamSize >> 1;
- //
- // Print out scratch address of each hart
- //
- DEBUG ((DEBUG_INFO, "%a: OpenSBI scratch address for each hart:\n", __FUNCTION__));
- for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
- ScratchSpace = sbi_hartid_to_scratch (HartId);
- if(ScratchSpace != NULL) {
- DEBUG((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, ScratchSpace));
- }
- }
-
//
// Set up OpepSBI firmware context pointer on boot hart OpenSbi scratch.
// Firmware context residents in stack and will be switched to memory when
@@ -564,20 +617,10 @@ VOID EFIAPI PeiCore (
FirmwareContext.FlattenedDeviceTree = Scratch->next_arg1;
//
- // Set firmware context Hart-specific pointer
+ // Transfer the control to the PEI core
//
- for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
- ScratchSpace = sbi_hartid_to_scratch (HartId);
- if (ScratchSpace != NULL) {
- FirmwareContext.HartSpecific[HartId] =
- (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)ScratchSpace - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE);
- DEBUG ((DEBUG_INFO, "%a: OpenSBI Hart %d Firmware Context Hart-specific at address: 0x%x\n",
- __FUNCTION__,
- HartId,
- FirmwareContext.HartSpecific [HartId]
- ));
- }
- }
+ FirmwareContext.SecPeiHandOffData = (UINT64)&SecCoreData;
+
//
// Set supervisor translation mode to Bare mode
//
@@ -585,13 +628,12 @@ VOID EFIAPI PeiCore (
RiscVSetSupervisorAddressTranslationRegister ((UINT64)RISCV_SATP_MODE_OFF << RISCV_SATP_MODE_BIT_POSITION);
//
- // Transfer the control to the PEI core
+ // Scratch->next_arg1 is the device tree.
//
- Scratch->next_addr = (UINTN)(*PeiCoreEntryPoint);
+ Scratch->next_addr = (UINTN)(PeiCoreEntryPoint);
Scratch->next_mode = PRV_S;
DEBUG ((DEBUG_INFO, "%a: Initializing OpenSBI library for booting hart %d\n", __FUNCTION__, BootHartId));
sbi_init(Scratch);
- (*PeiCoreEntryPoint) (&SecCoreData, (EFI_PEI_PPI_DESCRIPTOR *)&mPrivateDispatchTable);
}
/**
@@ -715,6 +757,7 @@ VOID EFIAPI SecCoreStartUpWithStack(
{
UINT64 BootHartDoneSbiInit;
UINT64 NonBootHartMessageLockValue;
+ struct sbi_platform *ThisSbiPlatform;
EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartFirmwareContext;
Scratch->next_arg1 = (unsigned long)GetDeviceTreeAddress ();
@@ -737,6 +780,14 @@ VOID EFIAPI SecCoreStartUpWithStack(
HartFirmwareContext->MachineImplId.Value64_H = 0;
HartFirmwareContext->HartSwitchMode = RiscVOpenSbiHartSwitchMode;
+ //
+ // Hook platorm_ops with EDK2 one. Thus we can have interface
+ // call out to OEM EDK2 platform code in M-mode before switching
+ // to S-mode in opensbo init.
+ //
+ ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(Scratch);
+ ThisSbiPlatform->platform_ops_addr = (unsigned long)&Edk2OpensbiPlatformOps;
+
if (HartId == FixedPcdGet32(PcdBootHartId)) {
LaunchPeiCore (HartId, Scratch);
}
@@ -768,6 +819,7 @@ VOID EFIAPI SecCoreStartUpWithStack(
// Non boot hart wiil be halted waiting for SBI_HART_STARTING.
// Use HSM ecall to start non boot hart (SBI_EXT_HSM_HART_START) later on,
//
+ Scratch->next_mode = PRV_S;
sbi_init(Scratch);
}
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 05/30] Platform/RISC-V: Add library to get PPI descriptor
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (3 preceding siblings ...)
2021-10-19 8:09 ` [edk2-platforms][PATCH 04/30] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 06/30] Platform/U540: Provide PlatormSecPpiLib Abner Chang
` (26 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
The library to provide the platform PPI descriptors in
PEI core entry before executing PEI core.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 2 ++
.../PlatformSecPpiLibNull.inf | 36 +++++++++++++++++++
.../Include/Library/PlatformSecPpiLib.h | 24 +++++++++++++
.../PlatformSecPpiLibNull/PlatformSecPpiLib.c | 28 +++++++++++++++
4 files changed, 90 insertions(+)
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/PlatformSecPpiLib.h
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
index 8eec09549f..b96324e961 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
@@ -61,6 +61,7 @@
[LibraryClasses.common.PEI_CORE]
# RISC-V platform PEI core entry point.
PeiCoreEntryPoint|Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ PlatformSecPpiLib|Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
[LibraryClasses.common.PEIM]
FirmwareContextProcessorSpecificLib|Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
@@ -82,6 +83,7 @@
Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
[Components.common.SEC]
Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf b/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
new file mode 100644
index 0000000000..22f5751655
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
@@ -0,0 +1,36 @@
+## @file
+# Library instance to to provide PPI before PEI Core
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PlatformSecPpiLib
+ FILE_GUID = A2CDDADC-CB65-4EED-9CAE-192B0BDD6C84
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformSecPpiLib|PEI_CORE
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ PlatformSecPpiLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+ #Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ #BaseLib
+ #PrintLib
+
diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/PlatformSecPpiLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/PlatformSecPpiLib.h
new file mode 100644
index 0000000000..88468e660b
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Include/Library/PlatformSecPpiLib.h
@@ -0,0 +1,24 @@
+/** @file
+ RISC-V platform SEC PPI before PEI Core.
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef RISCV_PLATFORM_SEC_PPI_H_
+#define RISCV_PLATFORM_SEC_PPI_H_
+
+#include <PiPei.h>
+
+/** Return platform SEC PPI before PEI Core
+
+ @param[in,out] ThisPpiList Pointer to retrieve EFI_PEI_PPI_DESCRIPTOR.
+
+**/
+EFI_STATUS
+GetPlatformPrePeiCorePpiDescriptor (
+ IN OUT EFI_PEI_PPI_DESCRIPTOR **ThisPpiList
+);
+
+#endif
diff --git a/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c b/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c
new file mode 100644
index 0000000000..d5c089b02d
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c
@@ -0,0 +1,28 @@
+/**@file
+ NULL library instance of PlatformSecPpiLib
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+/** Return platform SEC PPI before PEI Core
+
+ @param[in,out] ThisPpiList Pointer to retrieve EFI_PEI_PPI_DESCRIPTOR.
+
+**/
+EFI_STATUS
+GetPlatformPrePeiCorePpiDescriptor (
+ IN OUT EFI_PEI_PPI_DESCRIPTOR **ThisPpiList
+)
+{
+ *ThisPpiList = NULL;
+ return EFI_NOT_FOUND;
+}
+
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 06/30] Platform/U540: Provide PlatormSecPpiLib
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (4 preceding siblings ...)
2021-10-19 8:09 ` [edk2-platforms][PATCH 05/30] Platform/RISC-V: Add library to get PPI descriptor Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 07/30] Platform/RISC-V: Use PlatformSecPpiLib Abner Chang
` (25 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
Provide PlatormSecPpiLib instance for U540
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../FreedomU540HiFiveUnleashedBoard/U540.dsc | 1 +
.../PlatformSecPpiLib/PlatformSecPpiLib.inf | 43 +++++
.../PlatformSecPpiLib/PlatformSecPpiLib.c | 148 ++++++++++++++++++
3 files changed, 192 insertions(+)
create mode 100644 Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.inf
create mode 100644 Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.c
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
index be23fc39fd..d12af19825 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
@@ -192,6 +192,7 @@
PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
# RISC-V platform PEI core entry point.
PeiCoreEntryPoint|Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ PlatformSecPpiLib|Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.inf
[LibraryClasses.common.PEIM]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
diff --git a/Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.inf b/Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.inf
new file mode 100644
index 0000000000..7e9e1a5e20
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.inf
@@ -0,0 +1,43 @@
+## @file
+# Library instance to to provide PPI before PEI Core
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PlatformSecPpiLib
+ FILE_GUID = 8F8E049E-F193-427C-998E-1E8FE2612D94
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformSecPpiLib|PEI_CORE
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ PlatformSecPpiLib.c
+
+[Ppis]
+[Ppis]
+ gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED
+ gEfiTemporaryRamDonePpiGuid # PPI ALWAYS_PRODUCED
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ MemoryAllocationLib
+ PrintLib
+ RiscVFirmwareContextLib
diff --git a/Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.c b/Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.c
new file mode 100644
index 0000000000..ef84e8c1bc
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.c
@@ -0,0 +1,148 @@
+/**@file
+ Library to install platform PPI before PEI Core
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+#include <IndustryStandard/RiscVOpensbi.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <Library/PlatformSecPpiLib.h>
+#include <Library/PrintLib.h>
+#include <Library/RiscVFirmwareContextLib.h>
+
+#include <Ppi/TemporaryRamDone.h>
+#include <Ppi/TemporaryRamSupport.h>
+
+EFI_STATUS
+EFIAPI
+TemporaryRamMigration (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
+ IN UINTN CopySize
+ );
+
+EFI_STATUS
+EFIAPI
+TemporaryRamDone (
+ VOID
+ );
+
+STATIC EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = {
+ TemporaryRamMigration
+};
+
+STATIC EFI_PEI_TEMPORARY_RAM_DONE_PPI mTemporaryRamDonePpi = {
+ TemporaryRamDone
+};
+
+STATIC EFI_PEI_PPI_DESCRIPTOR mPrivateDispatchTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gEfiTemporaryRamSupportPpiGuid,
+ &mTemporaryRamSupportPpi
+ },
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiTemporaryRamDonePpiGuid,
+ &mTemporaryRamDonePpi
+ },
+};
+
+/** Temporary RAM migration function.
+
+ This function migrates the data from temporary RAM to permanent
+ memory.
+
+ @param[in] PeiServices PEI service
+ @param[in] TemporaryMemoryBase Temporary memory base address
+ @param[in] PermanentMemoryBase Permanent memory base address
+ @param[in] CopySize Size to copy
+
+**/
+EFI_STATUS
+EFIAPI
+TemporaryRamMigration (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
+ IN UINTN CopySize
+ )
+{
+ VOID *OldHeap;
+ VOID *NewHeap;
+ VOID *OldStack;
+ VOID *NewStack;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+
+ DEBUG ((DEBUG_INFO,
+ "%a: Temp Mem Base:0x%Lx, Permanent Mem Base:0x%Lx, CopySize:0x%Lx\n",
+ __FUNCTION__,
+ TemporaryMemoryBase,
+ PermanentMemoryBase,
+ (UINT64)CopySize
+ ));
+
+ OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;
+ NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize >> 1));
+
+ OldStack = (VOID*)((UINTN)TemporaryMemoryBase + (CopySize >> 1));
+ NewStack = (VOID*)(UINTN)PermanentMemoryBase;
+
+ CopyMem (NewHeap, OldHeap, CopySize >> 1); // Migrate Heap
+ CopyMem (NewStack, OldStack, CopySize >> 1); // Migrate Stack
+
+ //
+ // Reset firmware context pointer
+ //
+ GetFirmwareContextPointer (&FirmwareContext);
+ FirmwareContext = (VOID *)FirmwareContext + (unsigned long)((UINTN)NewStack - (UINTN)OldStack);
+ SetFirmwareContextPointer (FirmwareContext);
+
+ //
+ // Relocate PEI Service **
+ //
+ FirmwareContext->PeiServiceTable += (unsigned long)((UINTN)NewStack - (UINTN)OldStack);
+ DEBUG ((DEBUG_INFO, "%a: OpenSBI Firmware Context is relocated to 0x%x\n", __FUNCTION__, FirmwareContext));
+ DEBUG ((DEBUG_INFO, "OpenSBI Firmware Context at 0x%x\n", FirmwareContext));
+ DEBUG ((DEBUG_INFO, " PEI Service at 0x%x\n\n", FirmwareContext->PeiServiceTable));
+
+ register uintptr_t a0 asm ("a0") = (uintptr_t)((UINTN)NewStack - (UINTN)OldStack);
+ asm volatile ("add sp, sp, a0"::"r"(a0):);
+ return EFI_SUCCESS;
+}
+
+/** Temprary RAM done function.
+
+**/
+EFI_STATUS EFIAPI TemporaryRamDone (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "%a: 2nd time PEI core, temporary ram done.\n", __FUNCTION__));
+ return EFI_SUCCESS;
+}
+/** Return platform SEC PPI before PEI Core
+
+ @param[in,out] ThisPpiList Pointer to retrieve EFI_PEI_PPI_DESCRIPTOR.
+
+**/
+EFI_STATUS
+GetPlatformPrePeiCorePpiDescriptor (
+ IN OUT EFI_PEI_PPI_DESCRIPTOR **ThisPpiList
+)
+{
+ *ThisPpiList = mPrivateDispatchTable;
+ return EFI_SUCCESS;
+}
+
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 07/30] Platform/RISC-V: Use PlatformSecPpiLib
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (5 preceding siblings ...)
2021-10-19 8:09 ` [edk2-platforms][PATCH 06/30] Platform/U540: Provide PlatormSecPpiLib Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 08/30] Platform/SiFive: CoreInfoHob uses RiscVFirmwareContextLib Abner Chang
` (24 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
Use PlatformSecPpiLib to get PPI descriptor and
remove PPI descriptor related code from SEC.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../PeiCoreEntryPoint/PeiCoreEntryPoint.inf | 1 +
.../PlatformPkg/Universal/Sec/SecMain.inf | 4 -
.../PlatformPkg/Universal/Sec/SecMain.h | 17 ----
.../PeiCoreEntryPoint/PeiCoreEntryPoint.c | 15 +++-
.../PlatformPkg/Universal/Sec/SecMain.c | 84 -------------------
5 files changed, 14 insertions(+), 107 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
index e16a974636..4f3af27bcf 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
@@ -32,5 +32,6 @@
[LibraryClasses]
BaseLib
DebugLib
+ PlatformSecPpiLib
RiscVFirmwareContextLib
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
index 4207c83413..9736277fa1 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
@@ -52,10 +52,6 @@
RiscVOpensbiPlatformLib
RiscVEdk2SbiLib
-[Ppis]
- gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED
- gEfiTemporaryRamDonePpiGuid # PPI ALWAYS_PRODUCED
-
[FixedPcd]
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
index c04ddbad7f..496799efc0 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
@@ -25,8 +25,6 @@
#include <Library/PeCoffLib.h>
#include <Library/PeiServicesLib.h>
#include <Library/RiscVCpuLib.h>
-#include <Ppi/TemporaryRamDone.h>
-#include <Ppi/TemporaryRamSupport.h>
int
SecPostOpenSbiPlatformEarlylInit(
@@ -49,19 +47,4 @@ SecStartupPhase2 (
IN VOID *Context
);
-EFI_STATUS
-EFIAPI
-TemporaryRamMigration (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
- IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
- IN UINTN CopySize
- );
-
-EFI_STATUS
-EFIAPI
-TemporaryRamDone (
- VOID
- );
-
#endif // _SECMAIN_H_
diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
index 2fd0f2315b..16488b7bc9 100644
--- a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
+++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
@@ -17,6 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/PeiCoreEntryPoint.h>
+#include <Library/PlatformSecPpiLib.h>
#include <Library/RiscVFirmwareContextLib.h>
/**
@@ -49,15 +50,25 @@ _ModuleEntryPoint(
IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList
)
{
+ EFI_STATUS Status;
EFI_SEC_PEI_HAND_OFF *ThisSecCoreData;
EFI_PEI_PPI_DESCRIPTOR *ThisPpiList;
EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)PpiList;
SetFirmwareContextPointer (FirmwareContext);
+ FirmwareContext->BootHartId = (UINT64)SecCoreData;
+
ThisSecCoreData = (EFI_SEC_PEI_HAND_OFF *)FirmwareContext->SecPeiHandOffData;
- ThisPpiList = (EFI_PEI_PPI_DESCRIPTOR *)FirmwareContext->SecPeiHandoffPpi;
- ProcessModuleEntryPointList (ThisSecCoreData, ThisPpiList, NULL);
+ Status = GetPlatformPrePeiCorePpiDescriptor (&ThisPpiList);
+ if (EFI_ERROR (Status)) {
+ ThisPpiList = NULL;
+ }
+
+ //
+ // Invoke PEI Core entry point.
+ //
+ ProcessModuleEntryPointList(ThisSecCoreData, ThisPpiList, NULL);
//
// Should never return
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index 44984b0078..fb0adbca54 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -312,90 +312,6 @@ FindAndReportEntryPoints (
return;
}
-/*
- Print out the content of firmware context.
-
-**/
-VOID
-DebugPrintFirmwareContext (
- EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext
- )
-{
- DEBUG ((DEBUG_INFO, "%a: OpenSBI Firmware Context at 0x%x\n", __FUNCTION__, FirmwareContext));
- DEBUG ((DEBUG_INFO, "%a: PEI Service at 0x%x\n\n", __FUNCTION__, FirmwareContext->PeiServiceTable));
-}
-/** Temporary RAM migration function.
-
- This function migrates the data from temporary RAM to permanent
- memory.
-
- @param[in] PeiServices PEI service
- @param[in] TemporaryMemoryBase Temporary memory base address
- @param[in] PermanentMemoryBase Permanent memory base address
- @param[in] CopySize Size to copy
-
-**/
-EFI_STATUS
-EFIAPI
-TemporaryRamMigration (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
- IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
- IN UINTN CopySize
- )
-{
- VOID *OldHeap;
- VOID *NewHeap;
- VOID *OldStack;
- VOID *NewStack;
- EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
-
- DEBUG ((DEBUG_INFO,
- "%a: Temp Mem Base:0x%Lx, Permanent Mem Base:0x%Lx, CopySize:0x%Lx\n",
- __FUNCTION__,
- TemporaryMemoryBase,
- PermanentMemoryBase,
- (UINT64)CopySize
- ));
-
- OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;
- NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize >> 1));
-
- OldStack = (VOID*)((UINTN)TemporaryMemoryBase + (CopySize >> 1));
- NewStack = (VOID*)(UINTN)PermanentMemoryBase;
-
- CopyMem (NewHeap, OldHeap, CopySize >> 1); // Migrate Heap
- CopyMem (NewStack, OldStack, CopySize >> 1); // Migrate Stack
-
- //
- // Reset firmware context pointer
- //
- SbiGetFirmwareContext (&FirmwareContext);
- FirmwareContext = (VOID *)FirmwareContext + (unsigned long)((UINTN)NewStack - (UINTN)OldStack);
- SbiSetFirmwareContext (FirmwareContext);
-
- //
- // Relocate PEI Service **
- //
- FirmwareContext->PeiServiceTable += (unsigned long)((UINTN)NewStack - (UINTN)OldStack);
- DEBUG ((DEBUG_INFO, "%a: OpenSBI Firmware Context is relocated to 0x%x\n", __FUNCTION__, FirmwareContext));
- DebugPrintFirmwareContext ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)FirmwareContext);
-
- register uintptr_t a0 asm ("a0") = (uintptr_t)((UINTN)NewStack - (UINTN)OldStack);
- asm volatile ("add sp, sp, a0"::"r"(a0):);
- return EFI_SUCCESS;
-}
-
-/** Temprary RAM done function.
-
-**/
-EFI_STATUS EFIAPI TemporaryRamDone (
- VOID
- )
-{
- DEBUG ((DEBUG_INFO, "%a: 2nd time PEI core, temporary ram done.\n", __FUNCTION__));
- return EFI_SUCCESS;
-}
/**
Handles SBI calls of EDK2's SBI FW extension.
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 08/30] Platform/SiFive: CoreInfoHob uses RiscVFirmwareContextLib
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (6 preceding siblings ...)
2021-10-19 8:09 ` [edk2-platforms][PATCH 07/30] Platform/RISC-V: Use PlatformSecPpiLib Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 09/30] SiFive/U5SeriesPkg: Add CLINT to Device Tree Abner Chang
` (23 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
CoreInfoHob uses RiscVFirmwareContextLib to get the
pointer of FirmwareContext.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 3 ++-
Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 6 +++---
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
index d741f04747..4fe7827313 100644
--- a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
+++ b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
@@ -34,9 +34,10 @@
[LibraryClasses]
BaseLib
- PcdLib
MemoryAllocationLib
+ PcdLib
PrintLib
+ RiscVFirmwareContextLib
SiliconSiFiveU54CoreInfoLib
[Guids]
diff --git a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
index 326c4525bb..37363a0028 100644
--- a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
+++ b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -1,7 +1,7 @@
/**@file
Build up platform processor information of SiFive U54 core.
- Copyright (c) 2019 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2019 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -17,7 +17,7 @@
#include <Library/FirmwareContextProcessorSpecificLib.h>
#include <Library/HobLib.h>
#include <Library/PcdLib.h>
-#include <Library/RiscVEdk2SbiLib.h>
+#include <Library/RiscVFirmwareContextLib.h>
#include <RiscVImpl.h>
#include <sbi/sbi_hart.h>
@@ -63,7 +63,7 @@ CreateU54E51CoreProcessorSpecificDataHob (
return EFI_INVALID_PARAMETER;
}
- SbiGetFirmwareContext (&FirmwareContext);
+ GetFirmwareContextPointer (&FirmwareContext);
ASSERT (FirmwareContext != NULL);
if (FirmwareContext == NULL) {
DEBUG ((DEBUG_ERROR, "Failed to get the pointer of EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT of hart %d\n", HartId));
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 09/30] SiFive/U5SeriesPkg: Add CLINT to Device Tree
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (7 preceding siblings ...)
2021-10-19 8:09 ` [edk2-platforms][PATCH 08/30] Platform/SiFive: CoreInfoHob uses RiscVFirmwareContextLib Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 10/30] Platform/RISC-V: Add NULL library instance of RiscVSpecialPlatformLib Abner Chang
` (22 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
Add CLINT to Device Tree on U540 platform for
M-mode timer and IPI.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../DeviceTree/fu540-c000.dtsi | 591 +++++++++---------
1 file changed, 304 insertions(+), 287 deletions(-)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/fu540-c000.dtsi b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/fu540-c000.dtsi
index e44b6f7c56..1d8518cfb7 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/fu540-c000.dtsi
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTree/fu540-c000.dtsi
@@ -1,287 +1,304 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2018-2019 SiFive, Inc */
-
-/dts-v1/;
-
-/*#include <dt-bindings/clock/sifive-fu540-prci.h>*/
-#include "sifive-fu540-prci.h"
-
-/ {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "sifive,fu540-c000", "sifive,fu540";
-
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- ethernet0 = ð0;
- };
-
- chosen {
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu0: cpu@0 {
- compatible = "sifive,e51", "sifive,rocket0", "riscv";
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <128>;
- i-cache-size = <16384>;
- reg = <0>;
- riscv,isa = "rv64imac";
- status = "disabled";
- cpu0_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- cpu1: cpu@1 {
- compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- reg = <1>;
- riscv,isa = "rv64imafdc";
- tlb-split;
- next-level-cache = <&l2cache>;
- cpu1_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- cpu2: cpu@2 {
- compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- reg = <2>;
- riscv,isa = "rv64imafdc";
- tlb-split;
- next-level-cache = <&l2cache>;
- cpu2_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- cpu3: cpu@3 {
- compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- reg = <3>;
- riscv,isa = "rv64imafdc";
- tlb-split;
- next-level-cache = <&l2cache>;
- cpu3_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- cpu4: cpu@4 {
- compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- reg = <4>;
- riscv,isa = "rv64imafdc";
- tlb-split;
- next-level-cache = <&l2cache>;
- cpu4_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- };
- soc {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
- ranges;
- plic0: interrupt-controller@c000000 {
- #interrupt-cells = <1>;
- compatible = "sifive,plic-1.0.0";
- reg = <0x0 0xc000000 0x0 0x4000000>;
- riscv,ndev = <53>;
- interrupt-controller;
- interrupts-extended = <
- &cpu0_intc 0xffffffff
- &cpu1_intc 0xffffffff &cpu1_intc 9
- &cpu2_intc 0xffffffff &cpu2_intc 9
- &cpu3_intc 0xffffffff &cpu3_intc 9
- &cpu4_intc 0xffffffff &cpu4_intc 9>;
- };
- prci: clock-controller@10000000 {
- compatible = "sifive,fu540-c000-prci";
- reg = <0x0 0x10000000 0x0 0x1000>;
- clocks = <&hfclk>, <&rtcclk>;
- #clock-cells = <1>;
- };
- uart0: serial@10010000 {
- compatible = "sifive,fu540-c000-uart", "sifive,uart0";
- reg = <0x0 0x10010000 0x0 0x1000>;
- interrupt-parent = <&plic0>;
- interrupts = <4>;
- clocks = <&prci PRCI_CLK_TLCLK>;
- status = "disabled";
- };
- dma: dma@3000000 {
- compatible = "sifive,fu540-c000-pdma";
- reg = <0x0 0x3000000 0x0 0x8000>;
- interrupt-parent = <&plic0>;
- interrupts = <23 24 25 26 27 28 29 30>;
- #dma-cells = <1>;
- };
- uart1: serial@10011000 {
- compatible = "sifive,fu540-c000-uart", "sifive,uart0";
- reg = <0x0 0x10011000 0x0 0x1000>;
- interrupt-parent = <&plic0>;
- interrupts = <5>;
- clocks = <&prci PRCI_CLK_TLCLK>;
- status = "disabled";
- };
- i2c0: i2c@10030000 {
- compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
- reg = <0x0 0x10030000 0x0 0x1000>;
- interrupt-parent = <&plic0>;
- interrupts = <50>;
- clocks = <&prci PRCI_CLK_TLCLK>;
- reg-shift = <2>;
- reg-io-width = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- qspi0: spi@10040000 {
- compatible = "sifive,fu540-c000-spi", "sifive,spi0";
- reg = <0x0 0x10040000 0x0 0x1000
- 0x0 0x20000000 0x0 0x10000000>;
- interrupt-parent = <&plic0>;
- interrupts = <51>;
- clocks = <&prci PRCI_CLK_TLCLK>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- qspi1: spi@10041000 {
- compatible = "sifive,fu540-c000-spi", "sifive,spi0";
- reg = <0x0 0x10041000 0x0 0x1000
- 0x0 0x30000000 0x0 0x10000000>;
- interrupt-parent = <&plic0>;
- interrupts = <52>;
- clocks = <&prci PRCI_CLK_TLCLK>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- qspi2: spi@10050000 {
- compatible = "sifive,fu540-c000-spi", "sifive,spi0";
- reg = <0x0 0x10050000 0x0 0x1000>;
- interrupt-parent = <&plic0>;
- interrupts = <6>;
- clocks = <&prci PRCI_CLK_TLCLK>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- eth0: ethernet@10090000 {
- compatible = "sifive,fu540-c000-gem";
- interrupt-parent = <&plic0>;
- interrupts = <53>;
- reg = <0x0 0x10090000 0x0 0x2000
- 0x0 0x100a0000 0x0 0x1000>;
- local-mac-address = [00 00 00 00 00 00];
- clock-names = "pclk", "hclk";
- clocks = <&prci PRCI_CLK_GEMGXLPLL>,
- <&prci PRCI_CLK_GEMGXLPLL>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- pwm0: pwm@10020000 {
- compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
- reg = <0x0 0x10020000 0x0 0x1000>;
- interrupt-parent = <&plic0>;
- interrupts = <42 43 44 45>;
- clocks = <&prci PRCI_CLK_TLCLK>;
- #pwm-cells = <3>;
- status = "disabled";
- };
- pwm1: pwm@10021000 {
- compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
- reg = <0x0 0x10021000 0x0 0x1000>;
- interrupt-parent = <&plic0>;
- interrupts = <46 47 48 49>;
- clocks = <&prci PRCI_CLK_TLCLK>;
- #pwm-cells = <3>;
- status = "disabled";
- };
- l2cache: cache-controller@2010000 {
- compatible = "sifive,fu540-c000-ccache", "cache";
- cache-block-size = <64>;
- cache-level = <2>;
- cache-sets = <1024>;
- cache-size = <2097152>;
- cache-unified;
- interrupt-parent = <&plic0>;
- interrupts = <1 2 3>;
- reg = <0x0 0x2010000 0x0 0x1000>;
- };
- gpio: gpio@10060000 {
- compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
- interrupt-parent = <&plic0>;
- interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>,
- <14>, <15>, <16>, <17>, <18>, <19>, <20>,
- <21>, <22>;
- reg = <0x0 0x10060000 0x0 0x1000>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&prci PRCI_CLK_TLCLK>;
- status = "disabled";
- };
- };
-};
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2018-2019 SiFive, Inc */
+
+/dts-v1/;
+
+/**@file
+ SiFive U540 platform Device Tree
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "sifive-fu540-prci.h"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,fu540-c000", "sifive,fu540";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ ethernet0 = ð0;
+ };
+
+ chosen {
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu0: cpu@0 {
+ compatible = "sifive,e51", "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu1: cpu@1 {
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ next-level-cache = <&l2cache>;
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu2: cpu@2 {
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <2>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ next-level-cache = <&l2cache>;
+ cpu2_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu3: cpu@3 {
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <3>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ next-level-cache = <&l2cache>;
+ cpu3_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu4: cpu@4 {
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <4>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ next-level-cache = <&l2cache>;
+ cpu4_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
+ ranges;
+ plic0: interrupt-controller@c000000 {
+ #interrupt-cells = <1>;
+ compatible = "sifive,plic-1.0.0";
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ riscv,ndev = <53>;
+ interrupt-controller;
+ interrupts-extended = <
+ &cpu0_intc 0xffffffff
+ &cpu1_intc 0xffffffff &cpu1_intc 9
+ &cpu2_intc 0xffffffff &cpu2_intc 9
+ &cpu3_intc 0xffffffff &cpu3_intc 9
+ &cpu4_intc 0xffffffff &cpu4_intc 9>;
+ };
+ prci: clock-controller@10000000 {
+ compatible = "sifive,fu540-c000-prci";
+ reg = <0x0 0x10000000 0x0 0x1000>;
+ clocks = <&hfclk>, <&rtcclk>;
+ #clock-cells = <1>;
+ };
+ uart0: serial@10010000 {
+ compatible = "sifive,fu540-c000-uart", "sifive,uart0";
+ reg = <0x0 0x10010000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <4>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ status = "disabled";
+ };
+ dma: dma@3000000 {
+ compatible = "sifive,fu540-c000-pdma";
+ reg = <0x0 0x3000000 0x0 0x8000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <23 24 25 26 27 28 29 30>;
+ #dma-cells = <1>;
+ };
+ uart1: serial@10011000 {
+ compatible = "sifive,fu540-c000-uart", "sifive,uart0";
+ reg = <0x0 0x10011000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <5>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ status = "disabled";
+ };
+ i2c0: i2c@10030000 {
+ compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
+ reg = <0x0 0x10030000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <50>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ reg-shift = <2>;
+ reg-io-width = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ qspi0: spi@10040000 {
+ compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10040000 0x0 0x1000
+ 0x0 0x20000000 0x0 0x10000000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <51>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ qspi1: spi@10041000 {
+ compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10041000 0x0 0x1000
+ 0x0 0x30000000 0x0 0x10000000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <52>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ qspi2: spi@10050000 {
+ compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10050000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <6>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ eth0: ethernet@10090000 {
+ compatible = "sifive,fu540-c000-gem";
+ interrupt-parent = <&plic0>;
+ interrupts = <53>;
+ reg = <0x0 0x10090000 0x0 0x2000
+ 0x0 0x100a0000 0x0 0x1000>;
+ local-mac-address = [00 00 00 00 00 00];
+ clock-names = "pclk", "hclk";
+ clocks = <&prci PRCI_CLK_GEMGXLPLL>,
+ <&prci PRCI_CLK_GEMGXLPLL>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ pwm0: pwm@10020000 {
+ compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
+ reg = <0x0 0x10020000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <42 43 44 45>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+ pwm1: pwm@10021000 {
+ compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
+ reg = <0x0 0x10021000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <46 47 48 49>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+ l2cache: cache-controller@2010000 {
+ compatible = "sifive,fu540-c000-ccache", "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <1024>;
+ cache-size = <2097152>;
+ cache-unified;
+ interrupt-parent = <&plic0>;
+ interrupts = <1 2 3>;
+ reg = <0x0 0x2010000 0x0 0x1000>;
+ };
+ gpio: gpio@10060000 {
+ compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
+ interrupt-parent = <&plic0>;
+ interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>,
+ <14>, <15>, <16>, <17>, <18>, <19>, <20>,
+ <21>, <22>;
+ reg = <0x0 0x10060000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ status = "disabled";
+ };
+ clint: clint@2000000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
+ &cpu1_intc 3 &cpu1_intc 7
+ &cpu2_intc 3 &cpu2_intc 7
+ &cpu3_intc 3 &cpu3_intc 7
+ &cpu4_intc 3 &cpu4_intc 7>;
+ reg = <0x0 0x2000000 0x0 0xc0000>;
+ };
+ };
+};
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 10/30] Platform/RISC-V: Add NULL library instance of RiscVSpecialPlatformLib
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (8 preceding siblings ...)
2021-10-19 8:09 ` [edk2-platforms][PATCH 09/30] SiFive/U5SeriesPkg: Add CLINT to Device Tree Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 11/30] SiFive/U540: RiscVSpecialPlatformLib instance of U540 Abner Chang
` (21 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
This is the library instance to provide platform_override for the
special RISC-V platform. This module incorporates with
OpensbiPlatformLib and RISC-V Opensbi library.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 1 +
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 2 ++
.../RiscVSpecialPlatformLib.inf | 36 +++++++++++++++++++
.../Include/Library/RiscVSpecialPlatformLib.h | 20 +++++++++++
.../RiscVSpecialPlatformLib.c | 19 ++++++++++
5 files changed, 78 insertions(+)
create mode 100644 Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/RiscVSpecialPlatformLib.h
create mode 100644 Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.c
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
index 08279a97b1..9c8b57cce3 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
@@ -19,6 +19,7 @@
Include/Library
Library/RiscVOpensbiLib/opensbi # OpenSBI header file reference ("include/sbi/...")
Library/RiscVOpensbiLib/opensbi/include # Header file reference from opensbi files, ("sbi/...")
+ Library/RiscVOpensbiLib/opensbi/platform/generic/include # Header file reference from opensbi files, ("sbi/...")
[LibraryClasses]
RiscVPlatformDxeIplLib|Include/Library/RiscVPlatformDxeIpl.h
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
index b96324e961..ec8875be14 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
@@ -71,6 +71,7 @@
[LibraryClasses.common.SEC]
ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
+ RiscVSpecialPlatformLib|Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
[LibraryClasses.common.DXE_DRIVER]
PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -84,6 +85,7 @@
Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
+ Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
[Components.common.SEC]
Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
diff --git a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
new file mode 100644
index 0000000000..567eeee56d
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
@@ -0,0 +1,36 @@
+## @file
+# Null library instance to provide platform_override for the
+# special RISC-V platform. This module incorporates with
+# OpensbiPlatformLib and RISC-V Opensbi library.
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVSpecialPlatformLib
+ FILE_GUID = 79361802-18B6-458A-8C79-DA6256DEF776
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVSpecialPlatformLib|SEC
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ RiscVSpecialPlatformLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ BaseLib
diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/RiscVSpecialPlatformLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/RiscVSpecialPlatformLib.h
new file mode 100644
index 0000000000..644bb08ebf
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Include/Library/RiscVSpecialPlatformLib.h
@@ -0,0 +1,20 @@
+/** @file
+ library definition to provide platform_override of special platforms.
+ This library incorporates with OpensbiPlatformLib and RISC-V Opensbi library
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef RISCV_SPECIAL_PLATFORM_LIB_
+#define RISCV_SPECIAL_PLATFORM_LIB_
+
+#include <PiPei.h>
+
+//
+// This is declared under Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi/platform/generic/include/
+//
+#include <platform_override.h>
+
+#endif
diff --git a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.c b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.c
new file mode 100644
index 0000000000..3a77ff6b17
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.c
@@ -0,0 +1,19 @@
+/**@file
+ Library to provide platform_override for the special
+ RISC-V platform. This module incorporates with
+ OpensbiPlatformLib and RISC-V Opensbi library.
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <Library/RiscVSpecialPlatformLib.h>
+
+const struct platform_override *SpecialPlatformArray = NULL;
+INTN NumberOfPlaformsInArray;
+
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 11/30] SiFive/U540: RiscVSpecialPlatformLib instance of U540
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (9 preceding siblings ...)
2021-10-19 8:09 ` [edk2-platforms][PATCH 10/30] Platform/RISC-V: Add NULL library instance of RiscVSpecialPlatformLib Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 12/30] Platform/RISC-V: Remove platform dependency from this library Abner Chang
` (20 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
Provide platform_override of U540 platform.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../FreedomU540HiFiveUnleashedBoard/U540.dsc | 1 +
.../RiscVSpecialPlatformLib.inf | 36 ++++++++++++
.../RiscVSpecialPlatformLib/SifiveFu540.c | 56 +++++++++++++++++++
3 files changed, 93 insertions(+)
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/RiscVSpecialPlatformLib/SifiveFu540.c
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
index d12af19825..71dbca0e96 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
@@ -163,6 +163,7 @@
ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
+ RiscVSpecialPlatformLib|Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
!ifdef $(SOURCE_DEBUG_ENABLE)
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
new file mode 100644
index 0000000000..26f475ca45
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
@@ -0,0 +1,36 @@
+## @file
+# Null library instance to provide platform_override for the
+# special RISC-V platform. This module incorporates with
+# OpensbiPlatformLib and RISC-V Opensbi library.
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVSpecialPlatformLib
+ FILE_GUID = FE0AE3E6-90A4-421D-851D-E092CBEEE645
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVSpecialPlatformLib|SEC
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ SifiveFu540.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ BaseLib
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/RiscVSpecialPlatformLib/SifiveFu540.c b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/RiscVSpecialPlatformLib/SifiveFu540.c
new file mode 100644
index 0000000000..e89403f7ff
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/RiscVSpecialPlatformLib/SifiveFu540.c
@@ -0,0 +1,56 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ * Anup Patel <anup.patel@wdc.com>
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+ */
+
+#include <Library/RiscVSpecialPlatformLib.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+#include <sbi_utils/fdt/fdt_fixup.h>
+
+static u64 sifive_fu540_tlbr_flush_limit(const struct fdt_match *match)
+{
+ /*
+ * The sfence.vma by virtual address does not work on
+ * SiFive FU540 so we return remote TLB flush limit as zero.
+ */
+ return 0;
+}
+
+static int sifive_fu540_fdt_fixup(void *fdt, const struct fdt_match *match)
+{
+ /*
+ * SiFive Freedom U540 has an erratum that prevents S-mode software
+ * to access a PMP protected region using 1GB page table mapping, so
+ * always add the no-map attribute on this platform.
+ */
+ fdt_reserved_memory_nomap_fixup(fdt);
+
+ return 0;
+}
+
+static const struct fdt_match sifive_fu540_match[] = {
+ { .compatible = "sifive,fu540" },
+ { .compatible = "sifive,fu540g" },
+ { .compatible = "sifive,fu540-c000" },
+ { .compatible = "sifive,hifive-unleashed-a00" },
+ { },
+};
+
+const struct platform_override sifive_fu540 = {
+ .match_table = sifive_fu540_match,
+ .tlbr_flush_limit = sifive_fu540_tlbr_flush_limit,
+ .fdt_fixup = sifive_fu540_fdt_fixup,
+};
+
+const struct platform_override *special_platforms[] = {
+ &sifive_fu540,
+};
+INTN NumberOfPlaformsInArray = array_size(special_platforms);
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 12/30] Platform/RISC-V: Remove platform dependency from this library
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (10 preceding siblings ...)
2021-10-19 8:09 ` [edk2-platforms][PATCH 11/30] SiFive/U540: RiscVSpecialPlatformLib instance of U540 Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 13/30] Platform/RISC-V: Remove Null instance of OpensbilatformLibNull Abner Chang
` (19 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
This is the generic library for all RISC-V platforms. Remove
the dependencies of SiFive U540 platform.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../OpensbiPlatformLib/OpensbiPlatformLib.inf | 3 +-
.../OpensbiPlatformLib/PlatformOverride.h | 30 ------------
.../Library/OpensbiPlatformLib/Platform.c | 25 +++++++---
.../Library/OpensbiPlatformLib/SifiveFu540.c | 47 -------------------
4 files changed, 19 insertions(+), 86 deletions(-)
delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/PlatformOverride.h
delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/SifiveFu540.c
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
index a408737961..909fbffa8d 100644
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
@@ -25,8 +25,6 @@
[Sources]
Platform.c
- SifiveFu540.c
- PlatformOverride.h
[Packages]
EmbeddedPkg/EmbeddedPkg.dec
@@ -45,6 +43,7 @@
PcdLib
PrintLib
RiscVCpuLib
+ RiscVSpecialPlatformLib
[FixedPcd]
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/PlatformOverride.h b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/PlatformOverride.h
deleted file mode 100644
index 467ebbd4b8..0000000000
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/PlatformOverride.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2020 Western Digital Corporation or its affiliates.
- *
- * Authors:
- * Anup Patel <anup.patel@wdc.com>
- */
-
-#ifndef __PLATFORM_OVERRIDE_H__
-#define __PLATFORM_OVERRIDE_H__
-
-#include <sbi/sbi_types.h>
-
-struct platform_override {
- const struct fdt_match *match_table;
- u64 (*features)(const struct fdt_match *match);
- u64 (*tlbr_flush_limit)(const struct fdt_match *match);
- int (*early_init)(bool cold_boot, const struct fdt_match *match);
- int (*final_init)(bool cold_boot, const struct fdt_match *match);
- void (*early_exit)(const struct fdt_match *match);
- void (*final_exit)(const struct fdt_match *match);
- int (*system_reset_check)(u32 reset_type, u32 reset_reason,
- const struct fdt_match *match);
- void (*system_reset)(u32 reset_type, u32 reset_reason,
- const struct fdt_match *match);
- int (*fdt_fixup)(void *fdt, const struct fdt_match *match);
-};
-
-#endif
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
index 4fbb201895..06cd1a299f 100644
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
@@ -5,10 +5,16 @@
*
* Authors:
* Anup Patel <anup.patel@wdc.com>
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
*/
#include <libfdt.h>
-#include <PlatformOverride.h>
+#include <Library/RiscVSpecialPlatformLib.h>
+
#include <sbi/riscv_asm.h>
#include <sbi/sbi_domain.h>
#include <sbi/sbi_hartmask.h>
@@ -24,11 +30,12 @@
#include <sbi_utils/ipi/fdt_ipi.h>
#include <sbi_utils/reset/fdt_reset.h>
-extern const struct platform_override sifive_fu540;
-
-static const struct platform_override *special_platforms[] = {
- &sifive_fu540,
-};
+//
+// SpecialPlatformArray and NumberOfSpecialPlatform are
+// provided by RiscVSpecialPlatformLib library.
+//
+extern const struct platform_override *special_platforms[];
+extern INTN NumberOfPlaformsInArray;
static const struct platform_override *generic_plat = NULL;
static const struct fdt_match *generic_plat_match = NULL;
@@ -39,7 +46,11 @@ static void fw_platform_lookup_special(void *fdt, int root_offset)
const struct platform_override *plat;
const struct fdt_match *match;
- for (pos = 0; pos < array_size(special_platforms); pos++) {
+ if (special_platforms == NULL || NumberOfPlaformsInArray == 0) {
+ return;
+ }
+
+ for (pos = 0; pos < (int)NumberOfPlaformsInArray; pos++) {
plat = special_platforms[pos];
if (!plat->match_table)
continue;
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/SifiveFu540.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/SifiveFu540.c
deleted file mode 100644
index 748b058840..0000000000
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/SifiveFu540.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2020 Western Digital Corporation or its affiliates.
- *
- * Authors:
- * Anup Patel <anup.patel@wdc.com>
- */
-
-#include <PlatformOverride.h>
-#include <sbi_utils/fdt/fdt_helper.h>
-#include <sbi_utils/fdt/fdt_fixup.h>
-
-static u64 sifive_fu540_tlbr_flush_limit(const struct fdt_match *match)
-{
- /*
- * The sfence.vma by virtual address does not work on
- * SiFive FU540 so we return remote TLB flush limit as zero.
- */
- return 0;
-}
-
-static int sifive_fu540_fdt_fixup(void *fdt, const struct fdt_match *match)
-{
- /*
- * SiFive Freedom U540 has an erratum that prevents S-mode software
- * to access a PMP protected region using 1GB page table mapping, so
- * always add the no-map attribute on this platform.
- */
- fdt_reserved_memory_nomap_fixup(fdt);
-
- return 0;
-}
-
-static const struct fdt_match sifive_fu540_match[] = {
- { .compatible = "sifive,fu540" },
- { .compatible = "sifive,fu540g" },
- { .compatible = "sifive,fu540-c000" },
- { .compatible = "sifive,hifive-unleashed-a00" },
- { },
-};
-
-const struct platform_override sifive_fu540 = {
- .match_table = sifive_fu540_match,
- .tlbr_flush_limit = sifive_fu540_tlbr_flush_limit,
- .fdt_fixup = sifive_fu540_fdt_fixup,
-};
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 13/30] Platform/RISC-V: Remove Null instance of OpensbilatformLibNull
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (11 preceding siblings ...)
2021-10-19 8:09 ` [edk2-platforms][PATCH 12/30] Platform/RISC-V: Remove platform dependency from this library Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 14/30] RiscVPlatformPkg/Sec: Initial hart_index2Id array Abner Chang
` (18 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
Remove Null instance of OpensbilatformLibNull,
OpensbilatformLib is the generic one for RsicVPlatformPkg.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 2 +-
.../OpensbiPlatformLibNull.inf | 38 --------------
.../Library/OpensbiPlatformLibNull/Platform.c | 51 -------------------
3 files changed, 1 insertion(+), 90 deletions(-)
delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
index ec8875be14..93b3cd8de9 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
@@ -77,7 +77,7 @@
PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
[Components.common]
- Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
+ Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
deleted file mode 100644
index 125a1220bc..0000000000
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
+++ /dev/null
@@ -1,38 +0,0 @@
-## @file
-# RISC-V OpenSbi Platform NULL Library
-#
-# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-[Defines]
- INF_VERSION = 0x0001001b
- BASE_NAME = RiscVOpensbiPlatformLibNull
- FILE_GUID = 9424ED54-EBDA-4FB5-8FF6-8291B07BB151
- MODULE_TYPE = SEC
- VERSION_STRING = 1.0
- LIBRARY_CLASS = RiscVOpensbiPlatformLib
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = RISCV64
-#
-
-[Sources]
- Platform.c
-
-[Packages]
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
-
-[LibraryClasses]
- BaseLib
- BaseMemoryLib
- DebugLib
- DebugAgentLib
-
-
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c
deleted file mode 100644
index b7e39d19c1..0000000000
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- *
- * Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
- *
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2019 Western Digital Corporation or its affiliates.
- *
- * Authors:
- * Atish Patra <atish.patra@wdc.com>
- */
-
-#include <sbi/sbi_const.h>
-#include <sbi/sbi_platform.h>
-
-const struct sbi_platform_operations platform_ops = {
- .early_init = NULL,
- .final_init = NULL,
- .early_exit = NULL,
- .final_exit = NULL,
- .domains_root_regions = NULL,
- .domains_init = NULL,
- .console_putc = NULL,
- .console_getc = NULL,
- .console_init = NULL,
- .irqchip_init = NULL,
- .irqchip_exit = NULL,
- .ipi_send = NULL,
- .ipi_clear = NULL,
- .ipi_init = NULL,
- .ipi_exit = NULL,
- .get_tlbr_flush_limit = NULL,
- .timer_value = NULL,
- .timer_event_stop = NULL,
- .timer_event_start = NULL,
- .timer_init = NULL,
- .timer_exit = NULL,
- .system_reset_check = NULL,
- .system_reset = NULL,
-};
-
-struct sbi_platform platform = {
- .opensbi_version = OPENSBI_VERSION,
- .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
- .name = "NULL Platform",
- .features = 0,
- .hart_count = 0,
- .hart_index2id = 0,
- .hart_stack_size = 0,
- .platform_ops_addr = 0,
-};
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 14/30] RiscVPlatformPkg/Sec: Initial hart_index2Id array
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (12 preceding siblings ...)
2021-10-19 8:09 ` [edk2-platforms][PATCH 13/30] Platform/RISC-V: Remove Null instance of OpensbilatformLibNull Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 15/30] RiscVPlatformPkg/OpensbiPlatformLib: Remove platform code Abner Chang
` (17 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
Initial hart index to Id array by invoking OpenSBI
fw_platform_init function.
Introduce PcdBootableHartIndexToId PCD which could be
used to overwrite the hart_index2Id arrary built
from Devie tree according to platform demand.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 13 +++-
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 3 +-
.../PlatformPkg/Universal/Sec/SecMain.inf | 2 +
.../PlatformPkg/Universal/Sec/SecMain.c | 62 ++++++++++++++++---
.../Universal/Sec/Riscv64/SecEntry.S | 29 ++++++++-
5 files changed, 96 insertions(+), 13 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
index 7e41e7bdb2..947ae40e20 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
@@ -55,10 +55,21 @@
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001083
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001084
#
-# The bootable hart core number, which is incorporate with OpenSBI platform hart_index2id value.
+# The bootable hart core number, which incorporates with OpenSBI platform hart_index2id value.
+# PcdBootableHartNumber = 0 means the number of bootable hart comes from Device Tree.
+# Otherwise the number assigned in PcdBootableHartNumber overwrite it.
#
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber|0|UINT32|0x00001085
#
+# PcdBootableHartIndexToId is valid if PcdBootableHartNumber != 0.
+# If PcdBootableHartNumber != 0, then PcdBootableHartIndexToId is an array of
+# bootable hart ID.
+# For example,
+# if PcdBootableHartNumber == 3 then PcdBootableHartIndexToId could be defined
+# as {0x1, 0x2, 0x3}.
+#
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId|NULL|VOID*|0x00001086
+#
# Definitions for OpenSbi
#
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase|0|UINT32|0x00001100
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
index 93b3cd8de9..97d5dd08a0 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
@@ -39,7 +39,8 @@
!include MdePkg/MdeLibs.dsc.inc
[LibraryClasses.common]
- RiscVOpensbiPlatformLib|Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+ RiscVOpensbiPlatformLib|Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
index 9736277fa1..1cfbef961f 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
@@ -41,6 +41,7 @@
DebugAgentLib
DebugLib
ExtractGuidedSectionLib
+ FdtLib
IoLib
PcdLib
PeCoffLib
@@ -62,6 +63,7 @@
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index fb0adbca54..51d9edfe75 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -615,16 +615,17 @@ GetDeviceTreeAddress (
EFI_COMMON_SECTION_HEADER *FoundSection;
if (FixedPcdGet32 (PcdDeviceTreeAddress)) {
+ DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddress.\n"));
return (VOID *)*((unsigned long *)FixedPcdGet32 (PcdDeviceTreeAddress));
} else if (FixedPcdGet32 (PcdRiscVDtbFvBase)) {
+ DEBUG ((DEBUG_INFO, "Use DBT FV\n"));
Status = FindFfsFileAndSection (
(EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32 (PcdRiscVDtbFvBase),
EFI_FV_FILETYPE_FREEFORM,
EFI_SECTION_RAW,
&FoundSection
- );
+ );
if (EFI_ERROR(Status)) {
- DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found from FV.\n"));
return NULL;
}
FoundSection ++;
@@ -635,6 +636,35 @@ GetDeviceTreeAddress (
}
return NULL;
}
+/**
+ Overwrite hart_index2id array if platform would like to use the
+ bootable harts other than those declared in Device Tree
+
+ @param[in] SbiPlatform Pointer to SBI platform
+ @retval hart_index2id Index to ID value may be overwrote.
+ @retval hart_count Index to ID value may be overwrote.
+
+**/
+VOID
+Edk2PlatformHartIndex2Id (
+ IN struct sbi_platform *SbiPlatform
+ )
+{
+ UINT32 Index;
+ UINT32 *HartIndexToId;
+ UINT32 BootableHartCount;
+ UINT8 *PlatformHartIndex2IdArray;
+
+ BootableHartCount = FixedPcdGet32(PcdBootableHartNumber);
+ if (BootableHartCount != 0) {
+ HartIndexToId = (UINT32 *)SbiPlatform->hart_index2id;
+ PlatformHartIndex2IdArray = (UINT8 *)FixedPcdGetPtr (PcdBootableHartIndexToId);
+ for (Index = 0; Index < BootableHartCount; Index++) {
+ *(HartIndexToId + Index) = (UINT32)(*(PlatformHartIndex2IdArray + Index));
+ }
+ SbiPlatform->hart_count = BootableHartCount;
+ }
+}
/**
This function initilizes hart specific information and SBI.
@@ -671,17 +701,13 @@ VOID EFIAPI SecCoreStartUpWithStack(
IN struct sbi_scratch *Scratch
)
{
+ UINT32 HardIndex;
UINT64 BootHartDoneSbiInit;
UINT64 NonBootHartMessageLockValue;
struct sbi_platform *ThisSbiPlatform;
EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartFirmwareContext;
- Scratch->next_arg1 = (unsigned long)GetDeviceTreeAddress ();
- if (Scratch->next_arg1 == (unsigned long)NULL) {
- DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n"));
- ASSERT (FALSE);
- }
- DEBUG ((DEBUG_INFO, "DTB address: 0x%08x\n", Scratch->next_arg1));
+ DEBUG ((DEBUG_INFO, "HART ID: 0x%x enter SecCoreStartUpWithStack\n", HartId));
//
// Setup EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC for each hart.
@@ -705,6 +731,18 @@ VOID EFIAPI SecCoreStartUpWithStack(
ThisSbiPlatform->platform_ops_addr = (unsigned long)&Edk2OpensbiPlatformOps;
if (HartId == FixedPcdGet32(PcdBootHartId)) {
+
+ Scratch->next_arg1 = (unsigned long)GetDeviceTreeAddress ();
+ if (Scratch->next_arg1 == (unsigned long)NULL) {
+ DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n"));
+ ASSERT (FALSE);
+ }
+
+ DEBUG ((DEBUG_INFO, "HART number: 0x%x\n", ThisSbiPlatform->hart_count));
+ DEBUG ((DEBUG_INFO, "HART index to HART ID:\n"));
+ for (HardIndex = 0; HardIndex < ThisSbiPlatform->hart_count; HardIndex ++) {
+ DEBUG ((DEBUG_INFO, " Index: %d -> Hard ID: %x\n", HardIndex, ThisSbiPlatform->hart_index2id [HardIndex]));
+ }
LaunchPeiCore (HartId, Scratch);
}
@@ -739,3 +777,11 @@ VOID EFIAPI SecCoreStartUpWithStack(
sbi_init(Scratch);
}
+void xxxx (char *debugstr, ...)
+{
+ VA_LIST Marker;
+
+ VA_START (Marker, debugstr);
+ DebugVPrint (DEBUG_INFO, debugstr, Marker);
+ VA_END (Marker);
+}
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
index 0a69c50065..dc410703e0 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
@@ -101,16 +101,35 @@ _scratch_init:
/* Loop to next hart */
blt t1, s7, _scratch_init
- /* Fill-out temporary memory with 55aa*/
+ li a4, FixedPcdGet32 (PcdTemporaryRamBase)
+ li a5, FixedPcdGet32 (PcdTemporaryRamSize)
+
+ /* Use Temp memory as the stack for calling to C code */
+ add sp, a4, a5
+ /* Get the address of device tree and call generic fw_platform_init */
+ call GetDeviceTreeAddress /* a0 return the device tree address */
+ beqz a0, skip_fw_init
+ add a1, a0, 0 /* a1 is device tree */
+ csrr a0, CSR_MHARTID /* a0 is hart ID */
+ call fw_platform_init
+skip_fw_init:
+
+ /* Zero out temporary memory */
li a4, FixedPcdGet32 (PcdTemporaryRamBase)
li a5, FixedPcdGet32 (PcdTemporaryRamSize)
add a5, a4, a5
1:
- li a3, 0x5AA55AA55AA55AA5
+ li a3, 0x0
sd a3, (a4)
add a4, a4, __SIZEOF_POINTER__
blt a4, a5, 1b
+ /* Overwrite hart_index2id array of
+ platform would like to use the bootable hart
+ other than it defined in Device Tree */
+ la a0, platform
+ call Edk2PlatformHartIndex2Id
+
/* Update boot hart flag */
la a4, _boot_hart_done
li a5, 1
@@ -136,6 +155,10 @@ _start_warm:
csrw CSR_MIP, zero
li s7, FixedPcdGet32 (PcdBootableHartNumber)
+ bnez s7, 1f
+ la a4, platform
+ REG_L s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
+1:
li s8, FixedPcdGet32 (PcdOpenSbiStackSize)
la a4, platform
@@ -205,7 +228,7 @@ _start_warm:
/* Setup stack */
add sp, tp, zero
- /* Setup stack for the Hart executing EFI to top of temporary ram*/
+ /* Setup stack for the boot hart executing EFI to top of temporary ram*/
csrr a6, CSR_MHARTID
li a5, FixedPcdGet32 (PcdBootHartId)
bne a6, a5, 1f
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 15/30] RiscVPlatformPkg/OpensbiPlatformLib: Remove platform code
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (13 preceding siblings ...)
2021-10-19 8:09 ` [edk2-platforms][PATCH 14/30] RiscVPlatformPkg/Sec: Initial hart_index2Id array Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 16/30] RiscVPlatformPkg/U540: Only use four harts on U540 Abner Chang
` (16 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
Remove platform code from generic OpensbiPlatfomLib.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../Library/OpensbiPlatformLib/Platform.c | 25 ++++++-------------
1 file changed, 7 insertions(+), 18 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
index 06cd1a299f..b477b81d74 100644
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
@@ -270,24 +270,13 @@ const struct sbi_platform_operations platform_ops = {
.timer_exit = fdt_timer_exit,
};
-#if FixedPcdGet32(PcdBootableHartNumber) == 4
-#define U540_BOOTABLE_HART_COUNT FixedPcdGet32(PcdBootableHartNumber)
-static u32 U540_hart_index2id[U540_BOOTABLE_HART_COUNT] = {1, 2, 3, 4};
-#endif
-
struct sbi_platform platform = {
- .opensbi_version = OPENSBI_VERSION,
- .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
- .name = "Generic",
- .features = SBI_PLATFORM_DEFAULT_FEATURES,
- .hart_count = SBI_HARTMASK_MAX_BITS,
-// TODO: Workaround for U540. Not sure why we need this. OpenSBI doesn't need it.
-#if FixedPcdGet32(PcdBootableHartNumber) == 4
- .hart_index2id = U540_hart_index2id,
-#else
- .hart_index2id = generic_hart_index2id,
-#endif
- // TODO: Any reason why it shouldn't just be SBI_PLATFORM_DEFAULT_HART_STACK_SIZE?
- .hart_stack_size = FixedPcdGet32(PcdOpenSbiStackSize),
+ .opensbi_version = OPENSBI_VERSION,
+ .platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
+ .name = "Generic",
+ .features = SBI_PLATFORM_DEFAULT_FEATURES,
+ .hart_count = SBI_HARTMASK_MAX_BITS,
+ .hart_index2id = generic_hart_index2id,
+ .hart_stack_size = FixedPcdGet32(PcdOpenSbiStackSize), // The stack given by SEC for each hart
.platform_ops_addr = (unsigned long)&platform_ops
};
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 16/30] RiscVPlatformPkg/U540: Only use four harts on U540
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (14 preceding siblings ...)
2021-10-19 8:09 ` [edk2-platforms][PATCH 15/30] RiscVPlatformPkg/OpensbiPlatformLib: Remove platform code Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 17/30] U5SeriesPkg/PeiCoreInfoHob: Remove hart count check Abner Chang
` (15 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
Only use four harts on U540 reference code. This
overwrites the bootable harts declared in Device Tree.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../FreedomU540HiFiveUnleashedBoard/U540.fdf.inc | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
index f708f4d8be..1a525dc874 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
@@ -92,9 +92,16 @@ SET gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz = 1000000
SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock = 1000000000 # 1GHz system clock
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount = 5 # Total cores on U540 platform
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId = 1 # Boot hart ID
-SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber = 4 # The bootable hart core number.
- # Which is incorporate with OpenSBI
- # platform hart_index2id value.
+
+#
+# The bootable hart number the platform would like to use during boot.
+#
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber = 4
+#
+# Only use hart ID 1, 2, 3, 4
+#
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId = {0x1,0x2,0x3,0x4}
+ # during boot
SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdNumberofU5Cores = 4 # Total U5 cores enabled on U540 platform
SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdE5MCSupported = True # E51 MC exists.
SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase = 0x10010000 # Serial port base address
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 17/30] U5SeriesPkg/PeiCoreInfoHob: Remove hart count check
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (15 preceding siblings ...)
2021-10-19 8:09 ` [edk2-platforms][PATCH 16/30] RiscVPlatformPkg/U540: Only use four harts on U540 Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 18/30] RiscVPlatformPkg/RiscVSpecialPlatformLib: Rename module name Abner Chang
` (14 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
Remove hart count check because the bootable hart count
may be varied according to the harts declared in Device
tree and PcdBootableHartNumber PCD.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 9 +--------
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
index bc1b252946..c147028add 100644
--- a/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
+++ b/Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -75,14 +75,7 @@ CreateU5MCCoreplexProcessorSpecificDataHob (
}
DEBUG ((DEBUG_INFO, "Support %d U5 application cores on U5 platform\n", HartIdNumber - (UINT32)MCSupport));
- if (HartIdNumber != FixedPcdGet32 (PcdHartCount)) {
- DEBUG ((DEBUG_ERROR, "Improper core settings...\n"));
- DEBUG ((DEBUG_ERROR, " PcdHartCount\n"));
- DEBUG ((DEBUG_ERROR, " PcdNumberofU5Cores\n"));
- DEBUG ((DEBUG_ERROR, " PcdE5MCSupported\n\n"));
- ASSERT (FALSE);
- }
- return Status;
+ return EFI_SUCCESS;
}
/**
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 18/30] RiscVPlatformPkg/RiscVSpecialPlatformLib: Rename module name
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (16 preceding siblings ...)
2021-10-19 8:09 ` [edk2-platforms][PATCH 17/30] U5SeriesPkg/PeiCoreInfoHob: Remove hart count check Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 19/30] RiscVPlatformPkg/U540: Add SortLib Abner Chang
` (13 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
Rename RiscVSpecialPlatformLib to RiscVSpecialPlatformLibNull
because this is the NULL instance for RiscVPlatformPkg.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 4 ++--
.../RiscVSpecialPlatformLibNull.inf} | 0
.../RiscVSpecialPlatformLib.c | 3 ++-
3 files changed, 4 insertions(+), 3 deletions(-)
rename Platform/RISC-V/PlatformPkg/Library/{RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf => RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf} (100%)
rename Platform/RISC-V/PlatformPkg/Library/{RiscVSpecialPlatformLib => RiscVSpecialPlatformLibNull}/RiscVSpecialPlatformLib.c (76%)
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
index 97d5dd08a0..bbb043f9ed 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
@@ -72,7 +72,7 @@
[LibraryClasses.common.SEC]
ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
- RiscVSpecialPlatformLib|Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
+ RiscVSpecialPlatformLib|Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf
[LibraryClasses.common.DXE_DRIVER]
PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -86,7 +86,7 @@
Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
- Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
+ Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf
[Components.common.SEC]
Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
diff --git a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf
similarity index 100%
rename from Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
rename to Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf
diff --git a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.c b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
similarity index 76%
rename from Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.c
rename to Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
index 3a77ff6b17..18c152001c 100644
--- a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.c
+++ b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
@@ -14,6 +14,7 @@
//
#include <Library/RiscVSpecialPlatformLib.h>
-const struct platform_override *SpecialPlatformArray = NULL;
+const struct platform_override *special_platforms = NULL;
+const struct platform_override *SpecialPlatformArray = NULL;
INTN NumberOfPlaformsInArray;
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 19/30] RiscVPlatformPkg/U540: Add SortLib
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (17 preceding siblings ...)
2021-10-19 8:09 ` [edk2-platforms][PATCH 18/30] RiscVPlatformPkg/RiscVSpecialPlatformLib: Rename module name Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 20/30] ProcessorPkg/opensbi: Update opensbi library Abner Chang
` (12 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Add SortLib to run ram disk. Need to override generic library.
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
.../U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
index 71dbca0e96..4d16adfc82 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
@@ -532,6 +532,9 @@
OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.inf {
<PcdsFixedAtBuild>
gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ <LibraryClasses>
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
}
ShellPkg/Application/Shell/Shell.inf {
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 20/30] ProcessorPkg/opensbi: Update opensbi library
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (18 preceding siblings ...)
2021-10-19 8:09 ` [edk2-platforms][PATCH 19/30] RiscVPlatformPkg/U540: Add SortLib Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 21/30] RiscVPlatformPkg/Sec: Check Cold/Warm hart Abner Chang
` (11 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Update opensbi library to a731c7e36988c3308e1978ecde491f2f6182d490,
which is based on v0.9.
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com>
---
Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi b/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi
index 937caee083..a731c7e369 160000
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/opensbi
@@ -1 +1 @@
-Subproject commit 937caee0833115f69d697ca190001ba0aa5c7368
+Subproject commit a731c7e36988c3308e1978ecde491f2f6182d490
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 21/30] RiscVPlatformPkg/Sec: Check Cold/Warm hart
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (19 preceding siblings ...)
2021-10-19 8:09 ` [edk2-platforms][PATCH 20/30] ProcessorPkg/opensbi: Update opensbi library Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 22/30] RiscVPlatformPkg/Sec: Add more comments to Secmain.c Abner Chang
` (10 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
Check Coldboot or Warmboot hart in SEC OpenSBI platform function.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../RISC-V/PlatformPkg/Universal/Sec/SecMain.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index 51d9edfe75..9b162fb3b6 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -398,6 +398,13 @@ SecPostOpenSbiPlatformEarlylInit(
IN BOOLEAN ColdBoot
)
{
+ UINT32 HartId;
+
+ if (!ColdBoot) {
+ HartId = current_hartid();
+ DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId));
+ return 0;
+ }
//
// Boot HART is already in the process of OpenSBI initialization.
// We can let other HART to keep booting.
@@ -423,6 +430,12 @@ SecPostOpenSbiPlatformFinalInit (
struct sbi_platform *SbiPlatform;
EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+ if (!ColdBoot) {
+ HartId = current_hartid();
+ DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId));
+ return 0;
+ }
+
DEBUG((DEBUG_INFO, "%a: Entry, preparing to jump to PEI Core\n\n", __FUNCTION__));
SbiScratch = sbi_scratch_thishart_ptr();
@@ -777,7 +790,7 @@ VOID EFIAPI SecCoreStartUpWithStack(
sbi_init(Scratch);
}
-void xxxx (char *debugstr, ...)
+void OpensbiDebugPrint (char *debugstr, ...)
{
VA_LIST Marker;
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 22/30] RiscVPlatformPkg/Sec: Add more comments to Secmain.c
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (20 preceding siblings ...)
2021-10-19 8:09 ` [edk2-platforms][PATCH 21/30] RiscVPlatformPkg/Sec: Check Cold/Warm hart Abner Chang
@ 2021-10-19 8:09 ` Abner Chang
2021-10-19 8:10 ` [edk2-platforms][PATCH 23/30] RiscV/ProcessorPkg: Create read mtime CSR library instances Abner Chang
` (9 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:09 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
Add more comments to SecMain.c
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index 9b162fb3b6..93ff8a598d 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -628,7 +628,10 @@ GetDeviceTreeAddress (
EFI_COMMON_SECTION_HEADER *FoundSection;
if (FixedPcdGet32 (PcdDeviceTreeAddress)) {
- DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddress.\n"));
+ DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddress 0x%x.\n", FixedPcdGet32 (PcdDeviceTreeAddress)));
+ //
+ // Device tree address is pointed by PcdDeviceTreeAddress.
+ //
return (VOID *)*((unsigned long *)FixedPcdGet32 (PcdDeviceTreeAddress));
} else if (FixedPcdGet32 (PcdRiscVDtbFvBase)) {
DEBUG ((DEBUG_INFO, "Use DBT FV\n"));
@@ -720,7 +723,7 @@ VOID EFIAPI SecCoreStartUpWithStack(
struct sbi_platform *ThisSbiPlatform;
EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartFirmwareContext;
- DEBUG ((DEBUG_INFO, "HART ID: 0x%x enter SecCoreStartUpWithStack\n", HartId));
+ //DEBUG ((DEBUG_INFO, "HART ID: 0x%x enter SecCoreStartUpWithStack\n", HartId));
//
// Setup EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC for each hart.
@@ -750,7 +753,7 @@ VOID EFIAPI SecCoreStartUpWithStack(
DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n"));
ASSERT (FALSE);
}
-
+ DEBUG ((DEBUG_INFO, "Device Tree at 0x%x\n", Scratch->next_arg1));
DEBUG ((DEBUG_INFO, "HART number: 0x%x\n", ThisSbiPlatform->hart_count));
DEBUG ((DEBUG_INFO, "HART index to HART ID:\n"));
for (HardIndex = 0; HardIndex < ThisSbiPlatform->hart_count; HardIndex ++) {
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 23/30] RiscV/ProcessorPkg: Create read mtime CSR library instances
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (21 preceding siblings ...)
2021-10-19 8:09 ` [edk2-platforms][PATCH 22/30] RiscVPlatformPkg/Sec: Add more comments to Secmain.c Abner Chang
@ 2021-10-19 8:10 ` Abner Chang
2021-10-19 8:10 ` [edk2-platforms][PATCH 24/30] RiscV/ProcessorPkg: Use mtime CSR library Abner Chang
` (8 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
Create library instances of reading Machine mode timer.
- MacineModeTimerLib is used to read mtime CSR through
platfrom library.
- EmulatedMacineModeTimerLib is used to read mtime CSR
through shadow CSR.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 2 +
.../EmulatedMachineModeTimerLib.inf | 34 +++++++++++++++++
.../MachineModeTimerLib.inf | 38 +++++++++++++++++++
.../Include/IndustryStandard/RiscV.h | 5 +++
.../Include/Library/RiscVCpuLib.h | 3 ++
.../EmulatedMachineModeTimerLib.S | 24 ++++++++++++
.../MachineModeTimerLib/MachineModeTimerLib.S | 25 ++++++++++++
7 files changed, 131 insertions(+)
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
index 531319322c..3b5738957d 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
@@ -44,6 +44,8 @@
RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
TimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
+ #MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
new file mode 100644
index 0000000000..369028a9a6
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
@@ -0,0 +1,34 @@
+## @file
+# Library to read Machine Mode Timer.
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = EmulatedMachineModeTimerLib
+ FILE_GUID = 81B82615-D85C-4377-8BFF-7442322E2835
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = MachineModeTimerLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+
+[Sources.RISCV64]
+ EmulatedMachineModeTimerLib.S
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
new file mode 100644
index 0000000000..71d4315445
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
@@ -0,0 +1,38 @@
+## @file
+# Library to read Machine Mode Timer.
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = MachineModeTimerLib
+ FILE_GUID = 6390D8AA-E0E6-4625-A515-9BB2DC7BBCAB
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = MachineModeTimerLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+
+[Sources.RISCV64]
+ MachineModeTimerLib.S
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ RiscVCpuLib
+ RiscVPlatformTimerLib
+
+
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
index f6726bda24..c9715a2ee2 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
@@ -154,4 +154,9 @@
#define RISCV_CSR_MTOHOST 0x780
#define RISCV_CSR_MFROMHOST 0x781
+//
+// User mode CSR
+//
+#define RISCV_CSR_CYCLE 0xc00
+#define RISCV_CSR_TIME 0xc01
#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
index f70723567e..8d51152fa9 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVCpuLib.h
@@ -32,6 +32,9 @@ RiscVGetMachineTrapCause (VOID);
UINT64
RiscVReadMachineTimer (VOID);
+UINT64
+RiscVReadMachineTimerInterface (VOID);
+
VOID
RiscVSetMachineTimerCmp (UINT64);
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S
new file mode 100644
index 0000000000..1acd0ab062
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S
@@ -0,0 +1,24 @@
+//------------------------------------------------------------------------------
+//
+// Read Machine mode timer using shadow CSR.
+//
+// Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <IndustryStandard/RiscV.h>
+
+.data
+
+.text
+.align 3
+
+.global ASM_PFX(RiscVReadMachineTimerInterface)
+//
+// Read machine mode timer CSR through shadow CSR.
+// @retval a0 : 64-bit machine timer.
+//
+ASM_PFX (RiscVReadMachineTimerInterface):
+ csrr a0, RISCV_CSR_TIME
+ ret
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S
new file mode 100644
index 0000000000..16f8bdd70a
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S
@@ -0,0 +1,25 @@
+//------------------------------------------------------------------------------
+//
+// Read mtimer through platform library.
+//
+// Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <RiscVImpl.h>
+
+.data
+
+.text
+.align 3
+
+.global ASM_PFX(RiscVReadMachineTimerInterface)
+//
+// Read machine mode timer CSR.
+// @retval a0 : 64-bit machine timer.
+//
+ASM_PFX (RiscVReadMachineTimerInterface):
+ call RiscVReadMachineTimer
+ ret
+
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 24/30] RiscV/ProcessorPkg: Use mtime CSR library
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (22 preceding siblings ...)
2021-10-19 8:10 ` [edk2-platforms][PATCH 23/30] RiscV/ProcessorPkg: Create read mtime CSR library instances Abner Chang
@ 2021-10-19 8:10 ` Abner Chang
2021-10-19 8:10 ` [edk2-platforms][PATCH 25/30] Silicon/SiFive: " Abner Chang
` (7 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
Use mtime CSR library interface to access mtime
CSR.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../Library/RiscVTimerLib/BaseRiscVTimerLib.inf | 3 ++-
Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf | 1 +
.../ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c | 6 +++---
Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c | 2 +-
4 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
index c914d3b4b6..3c61149da8 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
@@ -30,5 +30,6 @@
BaseLib
PcdLib
RiscVCpuLib
- RiscVPlatformTimerLib
+ MachineModeTimerLib
+
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
index 29cc4413bd..a422c12e32 100644
--- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
@@ -26,6 +26,7 @@
CpuLib
CpuExceptionHandlerLib
DebugLib
+ MachineModeTimerLib
RiscVCpuLib
TimerLib
UefiBootServicesTableLib
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
index 97fe2aef4b..54ca99787e 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib/RiscVTimerLib.c
@@ -36,9 +36,9 @@ InternalRiscVTimerDelay (
//
// The target timer count is calculated here
//
- Ticks = RiscVReadMachineTimer () + Delay;
+ Ticks = RiscVReadMachineTimerInterface () + Delay;
Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
- while (((Ticks - RiscVReadMachineTimer ()) & ( 1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
+ while (((Ticks - RiscVReadMachineTimerInterface ()) & ( 1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
CpuPause ();
}
} while (Times-- > 0);
@@ -118,7 +118,7 @@ GetPerformanceCounter (
VOID
)
{
- return (UINT64)RiscVReadMachineTimer ();
+ return (UINT64)RiscVReadMachineTimerInterface ();
}
/**return
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
index b8b8e91a6c..3104c6d2de 100644
--- a/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.c
@@ -223,7 +223,7 @@ CpuGetTimerValue (
return EFI_INVALID_PARAMETER;
}
- *TimerValue = (UINT64)RiscVReadMachineTimer ();
+ *TimerValue = (UINT64)RiscVReadMachineTimerInterface ();
if (TimerPeriod != NULL) {
*TimerPeriod = DivU64x32 (
1000000000000000u,
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 25/30] Silicon/SiFive: Use mtime CSR library
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (23 preceding siblings ...)
2021-10-19 8:10 ` [edk2-platforms][PATCH 24/30] RiscV/ProcessorPkg: Use mtime CSR library Abner Chang
@ 2021-10-19 8:10 ` Abner Chang
2021-10-19 8:10 ` [edk2-platforms][PATCH 26/30] SiFive/SerialPortLib: Remove global variable Abner Chang
` (6 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
Use mtime CSR library interface to access mtime
CSR in Timer DXE driver.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../FreedomU540HiFiveUnleashedBoard/U540.dsc | 2 ++
.../Universal/Dxe/TimerDxe/TimerDxe.inf | 1 +
.../U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c | 14 +++++---------
3 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
index 4d16adfc82..c29b36e9bb 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
@@ -148,6 +148,8 @@
RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
RiscVPlatformTimerLib|Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf
+ #MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
+ MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
CpuExceptionHandlerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
diff --git a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf
index 25cb3bb8b4..4571621a2e 100644
--- a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf
+++ b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/TimerDxe.inf
@@ -30,6 +30,7 @@
BaseLib
DebugLib
IoLib
+ MachineModeTimerLib
RiscVCpuLib
RiscVEdk2SbiLib
UefiBootServicesTableLib
diff --git a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c
index 065ecdda86..deb5799277 100644
--- a/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c
+++ b/Platform/SiFive/U5SeriesPkg/Universal/Dxe/TimerDxe/Timer.c
@@ -15,9 +15,6 @@
#include <sbi/riscv_atomic.h>
#include <U5Clint.h>
-STATIC volatile VOID * const p_mtime = (VOID *)CLINT_REG_MTIME;
-#define MTIME (*p_mtime)
-#define MTIMECMP(i) (p_mtimecmp[i])
BOOLEAN TimerHandlerReentry = FALSE;
//
@@ -73,7 +70,7 @@ TimerInterruptHandler (
// MMode timer occurred when processing
// SMode timer handler.
//
- RiscvTimer = readq_relaxed(p_mtime);
+ RiscvTimer = RiscVReadMachineTimerInterface();
SbiSetTimer (RiscvTimer += mTimerPeriod);
csr_clear(CSR_SIP, MIP_STIP);
return;
@@ -91,7 +88,7 @@ TimerInterruptHandler (
if (mTimerNotifyFunction != NULL) {
mTimerNotifyFunction (mTimerPeriod);
}
- RiscvTimer = readq_relaxed(p_mtime);
+ RiscvTimer = RiscVReadMachineTimerInterface();
SbiSetTimer (RiscvTimer += mTimerPeriod);
gBS->RestoreTPL (OriginalTPL);
csr_set(CSR_SIE, MIP_STIP); // enable SMode timer int
@@ -185,10 +182,9 @@ TimerDriverSetTimerPeriod (
return EFI_SUCCESS;
}
- mTimerPeriod = TimerPeriod / 10; // convert unit from 100ns to 1us
-
- RiscvTimer = readq_relaxed(p_mtime);
- SbiSetTimer(RiscvTimer + mTimerPeriod);
+ mTimerPeriod = TimerPeriod; // convert unit from 100ns to 1us
+ RiscvTimer = RiscVReadMachineTimerInterface();
+ SbiSetTimer(RiscvTimer + mTimerPeriod / 10);
mCpu->EnableInterrupt(mCpu);
csr_set(CSR_SIE, MIP_STIP); // enable timer int
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 26/30] SiFive/SerialPortLib: Remove global variable
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (24 preceding siblings ...)
2021-10-19 8:10 ` [edk2-platforms][PATCH 25/30] Silicon/SiFive: " Abner Chang
@ 2021-10-19 8:10 ` Abner Chang
2021-10-19 8:10 ` [edk2-platforms][PATCH 27/30] RISC-V/PlatformPkg: Updates for the latest OpenSBI Abner Chang
` (5 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
Remove global variable from SerialPortLib because this
module is not necessarily executed in memory.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../SiFive/U5SeriesPkg/Include/SifiveU5Uart.h | 1 +
.../Library/SerialIoLib/SerialPortLib.c | 58 +++++++++++++++----
2 files changed, 49 insertions(+), 10 deletions(-)
diff --git a/Platform/SiFive/U5SeriesPkg/Include/SifiveU5Uart.h b/Platform/SiFive/U5SeriesPkg/Include/SifiveU5Uart.h
index 0ccb98e874..be8dce8c96 100644
--- a/Platform/SiFive/U5SeriesPkg/Include/SifiveU5Uart.h
+++ b/Platform/SiFive/U5SeriesPkg/Include/SifiveU5Uart.h
@@ -10,6 +10,7 @@
#ifndef SIFIVE_U5_SERIES_UART_H_
#define SIFIVE_U5_SERIES_UART_H_
+#include <include/sbi/riscv_io.h>
#include <include/sbi_utils/serial/sifive-uart.h>
#endif
diff --git a/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialPortLib.c b/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialPortLib.c
index 7bc73a0b82..42e5aa7b76 100644
--- a/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialPortLib.c
+++ b/Platform/SiFive/U5SeriesPkg/Library/SerialIoLib/SerialPortLib.c
@@ -8,6 +8,7 @@
**/
#include <Base.h>
+#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/SerialPortLib.h>
#include <Include/SifiveU5Uart.h>
@@ -41,7 +42,7 @@
#define UART_BAUDRATE 115200
#define SYS_CLK FixedPcdGet32(PcdU5PlatformSystemClock)
-BOOLEAN Initiated = FALSE;
+BOOLEAN Initiated = TRUE;
/**
Get value from serial port register.
@@ -55,7 +56,9 @@ UINT32 GetReg (
IN UINT32 RegIndex
)
{
- return MmioRead32 (FixedPcdGet32(PcdU5UartBase) + (RegIndex * 0x4));
+ STATIC volatile UINT32 * const uart = (UINT32 *)FixedPcdGet32(PcdU5UartBase);
+
+ return readl ((volatile void *)(uart + RegIndex));
}
/**
@@ -70,7 +73,9 @@ VOID SetReg (
IN UINT32 Value
)
{
- MmioWrite32 (Value, FixedPcdGet32(PcdU5UartBase) + (RegIndex * 0x4));
+ STATIC volatile UINT32 * const uart = (UINT32 *)FixedPcdGet32(PcdU5UartBase);
+
+ writel (Value, (volatile void *)(uart + RegIndex));
}
/**
@@ -104,7 +109,36 @@ UINT32 SifiveUartGetChar (VOID)
}
return -1;
}
+/**
+ Find minimum divisor divides in_freq to max_target_hz;
+ Based on uart driver n SiFive FSBL.
+
+ f_baud = f_in / (div + 1) => div = (f_in / f_baud) - 1
+ The nearest integer solution requires rounding up as to not exceed max_target_hz.
+ div = ceil(f_in / f_baud) - 1
+ = floor((f_in - 1 + f_baud) / f_baud) - 1
+ This should not overflow as long as (f_in - 1 + f_baud) does not exceed
+ 2^32 - 1, which is unlikely since we represent frequencies in kHz.
+
+ @param Freq The given clock to UART.
+ @param MaxTargetHZ Target baudrate.
+**/
+UINT32
+UartMinClkDivisor (
+ IN UINT64 Freq,
+ IN UINT64 MaxTargetHZ
+ )
+{
+ UINT64 Quotient;
+
+ Quotient = (Freq + MaxTargetHZ - 1) / (MaxTargetHZ);
+ if (Quotient == 0) {
+ return 0;
+ } else {
+ return Quotient - 1;
+ }
+}
/**
Initialize the serial device hardware.
@@ -116,20 +150,24 @@ UINT32 SifiveUartGetChar (VOID)
@retval RETURN_DEVICE_ERROR The serail device could not be initialized.
**/
-RETURN_STATUS
+EFI_STATUS
EFIAPI
SerialPortInitialize (
VOID
)
{
- if (Initiated) {
- return RETURN_SUCCESS;
+ UINT32 Divisor;
+ UINT32 CurrentDivisor;
+
+ Divisor = UartMinClkDivisor (SYS_CLK / 2, UART_BAUDRATE);
+ if (Divisor == 0) {
+ return EFI_INVALID_PARAMETER;
}
- if (sifive_uart_init (FixedPcdGet32(PcdU5UartBase), SYS_CLK / 2, UART_BAUDRATE) != 0) {
- return EFI_DEVICE_ERROR;
+ CurrentDivisor = GetReg(UART_REG_DIV);
+ if (Divisor != CurrentDivisor) {
+ sifive_uart_init (FixedPcdGet32(PcdU5UartBase), SYS_CLK / 2, UART_BAUDRATE);
}
- Initiated = TRUE;
- return RETURN_SUCCESS;
+ return EFI_SUCCESS;
}
/**
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 27/30] RISC-V/PlatformPkg: Updates for the latest OpenSBI
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (25 preceding siblings ...)
2021-10-19 8:10 ` [edk2-platforms][PATCH 26/30] SiFive/SerialPortLib: Remove global variable Abner Chang
@ 2021-10-19 8:10 ` Abner Chang
2021-10-19 8:10 ` [edk2-platforms][PATCH 28/30] RiscVPlatformPkg/Sec: Separate EDK2 Opensbi platform hook Abner Chang
` (4 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
Code changes to incorporate with OpenSBI commit ID:
a731c7e36988c3308e1978ecde491f2f6182d490
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../OpensbiPlatformLib/OpensbiPlatformLib.inf | 10 +-
.../PlatformPkg/Universal/Sec/SecMain.inf | 4 +
.../Library/OpensbiPlatformLib/Platform.c | 57 ----
.../Universal/Sec/Edk2OpenSbiPlatform.c | 149 ---------
.../PlatformPkg/Universal/Sec/SecMain.c | 48 ++-
.../Universal/Sec/Riscv64/SecEntry.S | 300 ++++++++++--------
6 files changed, 212 insertions(+), 356 deletions(-)
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
index 909fbffa8d..2e1227733a 100644
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
@@ -51,12 +51,4 @@
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
- gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase
- gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock
-
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize
+
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
index 1cfbef961f..dd5f01ab4d 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
@@ -66,6 +66,10 @@
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
index b477b81d74..c62d235333 100644
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Platform.c
@@ -197,68 +197,11 @@ static u64 generic_tlbr_flush_limit(void)
return SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT;
}
-static int generic_system_reset_check(u32 reset_type, u32 reset_reason)
-{
- if (generic_plat && generic_plat->system_reset_check)
- return generic_plat->system_reset_check(reset_type,
- reset_reason,
- generic_plat_match);
- return fdt_system_reset_check(reset_type, reset_reason);
-}
-
-static void generic_system_reset(u32 reset_type, u32 reset_reason)
-{
- if (generic_plat && generic_plat->system_reset) {
- generic_plat->system_reset(reset_type, reset_reason,
- generic_plat_match);
- return;
- }
-
- fdt_system_reset(reset_type, reset_reason);
-}
-
-#define EDK2_ROOT_FW_REGION 0
-#define EDK2_FW_REGION 1
-#define EDK2_VARIABLE_REGION 2
-#define EDK2_ALL_REGION 3
-#define EDK2_END_REGION 4
-static struct sbi_domain_memregion root_memregs[EDK2_END_REGION + 1] = { 0 };
-
-struct sbi_domain_memregion *get_mem_regions(void) {
- /* EDK2 root firmware domain memory region */
- root_memregs[EDK2_ROOT_FW_REGION].order = log2roundup(FixedPcdGet32(PcdRootFirmwareDomainSize));
- root_memregs[EDK2_ROOT_FW_REGION].base = FixedPcdGet32(PcdRootFirmwareDomainBaseAddress);
- root_memregs[EDK2_ROOT_FW_REGION].flags = 0;
-
- /*EDK2 firmware domain memory region */
- root_memregs[EDK2_FW_REGION].order = log2roundup(FixedPcdGet32(PcdFirmwareDomainSize));
- root_memregs[EDK2_FW_REGION].base = FixedPcdGet32(PcdFirmwareDomainBaseAddress);
- root_memregs[EDK2_FW_REGION].flags = SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREGION_READABLE;
-
- /*EDK2 firmware domain memory region */
- root_memregs[EDK2_VARIABLE_REGION].order = log2roundup(FixedPcdGet32(PcdVariableFirmwareRegionSize));
- root_memregs[EDK2_VARIABLE_REGION].base = FixedPcdGet32(PcdVariableFirmwareRegionBaseAddress);
- root_memregs[EDK2_VARIABLE_REGION].flags = SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGION_WRITEABLE;
-
- /* EDK2 domain allow everything memory region */
- root_memregs[EDK2_ALL_REGION].order = __riscv_xlen;
- root_memregs[EDK2_ALL_REGION].base = 0;
- root_memregs[EDK2_ALL_REGION].flags = (SBI_DOMAIN_MEMREGION_READABLE |
- SBI_DOMAIN_MEMREGION_WRITEABLE |
- SBI_DOMAIN_MEMREGION_EXECUTABLE);
-
- /* EDK2 domain memory region end */
- root_memregs[EDK2_END_REGION].order = 0;
-
- return root_memregs;
-}
-
const struct sbi_platform_operations platform_ops = {
.early_init = generic_early_init,
.final_init = generic_final_init,
.early_exit = generic_early_exit,
.final_exit = generic_final_exit,
- .domains_root_regions = get_mem_regions,
.domains_init = generic_domains_init,
.console_init = fdt_serial_init,
.irqchip_init = fdt_irqchip_init,
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c
index 79b2f33675..779705489c 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c
@@ -117,18 +117,6 @@ int Edk2OpensbiPlatforMMISAGetXLEN (VOID)
return 0;
}
-/** Get platform specific root domain memory regions */
-struct sbi_domain_memregion *
-Edk2OpensbiPlatformGetMemRegions (VOID)
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.domains_root_regions) {
- return platform_ops.domains_root_regions ();
- }
- return 0;
-}
-
/** Initialize (or populate) domains for the platform */
int Edk2OpensbiPlatformDomainsInit (VOID)
{
@@ -140,25 +128,6 @@ int Edk2OpensbiPlatformDomainsInit (VOID)
return 0;
}
-/** Write a character to the platform console output */
-VOID Edk2OpensbiPlatformSerialPutc (
- CHAR8 Ch
- )
-{
- if (platform_ops.console_putc) {
- return platform_ops.console_putc (Ch);
- }
-}
-
-/** Read a character from the platform console input */
-int Edk2OpensbiPlatformSerialGetc (VOID)
-{
- if (platform_ops.console_getc) {
- return platform_ops.console_getc ();
- }
- return 0;
-}
-
/** Initialize the platform console */
int Edk2OpensbiPlatformSerialInit (VOID)
{
@@ -193,30 +162,6 @@ VOID Edk2OpensbiPlatformIrqchipExit (VOID)
}
}
-/** Send IPI to a target HART */
-VOID Edk2OpensbiPlatformIpiSend (
- UINT32 TargetHart
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.ipi_send) {
- return platform_ops.ipi_send (TargetHart);
- }
-}
-
-/** Clear IPI for a target HART */
-VOID Edk2OpensbiPlatformIpiClear (
- UINT32 TargetHart
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.ipi_clear) {
- return platform_ops.ipi_clear (TargetHart);
- }
-}
-
/** Initialize IPI for current HART */
int Edk2OpensbiPlatformIpiInit (
BOOLEAN ColdBoot
@@ -251,33 +196,6 @@ UINT64 Edk2OpensbiPlatformTlbrFlushLimit (VOID)
return 0;
}
-/** Get platform timer value */
-UINT64 Edk2OpensbiPlatformTimerValue (VOID)
-{
- if (platform_ops.timer_value) {
- return platform_ops.timer_value ();
- }
- return 0;
-}
-
-/** Start platform timer event for current HART */
-VOID Edk2OpensbiPlatformTimerEventStart (
- UINT64 NextEvent
- )
-{
- if (platform_ops.timer_event_start) {
- return platform_ops.timer_event_start (NextEvent);
- }
-}
-
-/** Stop platform timer event for current HART */
-VOID Edk2OpensbiPlatformTimerEventStop (VOID)
-{
- if (platform_ops.timer_event_stop) {
- return platform_ops.timer_event_stop ();
- }
-}
-
/** Initialize platform timer for current HART */
int Edk2OpensbiPlatformTimerInit (
BOOLEAN ColdBoot
@@ -301,61 +219,6 @@ VOID Edk2OpensbiPlatformTimerExit (VOID)
}
}
-/** Bringup the given hart */
-int Edk2OpensbiPlatformHartStart (
- UINT32 HartId,
- ulong Saddr
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.hart_start) {
- return platform_ops.hart_start (HartId, Saddr);
- }
- return 0;
-}
-/**
- Stop the current hart from running. This call doesn't expect to
- return if success.
-**/
-int Edk2OpensbiPlatformHartStop (VOID)
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.hart_stop) {
- return platform_ops.hart_stop ();
- }
- return 0;
-}
-
-/**
- Check whether reset type and reason supported by the platform*
-
-**/
-int Edk2OpensbiPlatformSystemResetCheck (
- UINT32 ResetType,
- UINT32 ResetReason
- )
-{
- if (platform_ops.system_reset_check) {
- return platform_ops.system_reset_check (ResetType, ResetReason);
- }
- return 0;
-}
-
-/** Reset the platform */
-VOID Edk2OpensbiPlatformSystemReset (
- UINT32 ResetType,
- UINT32 ResetReason
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.system_reset) {
- return platform_ops.system_reset (ResetType, ResetReason);
- }
-}
-
/** platform specific SBI extension implementation probe function */
int Edk2OpensbiPlatformVendorExtCheck (
long ExtId
@@ -400,27 +263,15 @@ const struct sbi_platform_operations Edk2OpensbiPlatformOps = {
.final_exit = Edk2OpensbiPlatformFinalExit,
.misa_check_extension = Edk2OpensbiPlatforMMISACheckExtension,
.misa_get_xlen = Edk2OpensbiPlatforMMISAGetXLEN,
- .domains_root_regions = Edk2OpensbiPlatformGetMemRegions,
.domains_init = Edk2OpensbiPlatformDomainsInit,
- .console_putc = Edk2OpensbiPlatformSerialPutc,
- .console_getc = Edk2OpensbiPlatformSerialGetc,
.console_init = Edk2OpensbiPlatformSerialInit,
.irqchip_init = Edk2OpensbiPlatformIrqchipInit,
.irqchip_exit = Edk2OpensbiPlatformIrqchipExit,
- .ipi_send = Edk2OpensbiPlatformIpiSend,
- .ipi_clear = Edk2OpensbiPlatformIpiClear,
.ipi_init = Edk2OpensbiPlatformIpiInit,
.ipi_exit = Edk2OpensbiPlatformIpiExit,
.get_tlbr_flush_limit = Edk2OpensbiPlatformTlbrFlushLimit,
- .timer_value = Edk2OpensbiPlatformTimerValue,
- .timer_event_stop = Edk2OpensbiPlatformTimerEventStop,
- .timer_event_start = Edk2OpensbiPlatformTimerEventStart,
.timer_init = Edk2OpensbiPlatformTimerInit,
.timer_exit = Edk2OpensbiPlatformTimerExit,
- .hart_start = Edk2OpensbiPlatformHartStart,
- .hart_stop = Edk2OpensbiPlatformHartStop,
- .system_reset_check = Edk2OpensbiPlatformSystemResetCheck,
- .system_reset = Edk2OpensbiPlatformSystemReset,
.vendor_ext_check = Edk2OpensbiPlatformVendorExtCheck,
.vendor_ext_provider = Edk2OpensbiPlatformVendorExtProvider,
};
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index 93ff8a598d..3bc3690047 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -15,10 +15,12 @@
#include <sbi/riscv_asm.h>
#include <sbi/riscv_atomic.h>
#include <sbi/sbi_console.h> // Reference to header file in opensbi
+#include <sbi/sbi_domain.h>
#include <sbi/sbi_hart.h> // Reference to header file in opensbi
-#include <sbi/sbi_hartmask.h> // Reference to header file in opensbi
+#include <sbi/sbi_hartmask.h> // Reference to header file in opensbi
#include <sbi/sbi_scratch.h> // Reference to header file in opensbi
#include <sbi/sbi_platform.h> // Reference to header file in opensbi
+#include <sbi/sbi_math.h> // Reference to header file in opensbi
#include <sbi/sbi_init.h> // Reference to header file in opensbi
#include <sbi/sbi_ecall.h> // Reference to header file in opensbi
#include <sbi/sbi_trap.h> // Reference to header file in opensbi
@@ -31,8 +33,41 @@ extern struct sbi_platform_operations Edk2OpensbiPlatformOps;
atomic_t BootHartDone = ATOMIC_INITIALIZER(0);
atomic_t NonBootHartMessageLock = ATOMIC_INITIALIZER(0);
+int sbi_domain_root_add_memregion(const struct sbi_domain_memregion *reg);
+
typedef struct sbi_scratch *(*hartid2scratch)(ulong hartid, ulong hartindex);
+struct sbi_domain_memregion fw_memregs;
+
+int SecSetEdk2FwMemoryRegions (VOID) {
+ int Ret;
+
+ Ret = 0;
+
+ //
+ // EDK2 PEI domain memory region
+ //
+ fw_memregs.order = log2roundup(FixedPcdGet32(PcdFirmwareDomainSize));
+ fw_memregs.base = FixedPcdGet32(PcdFirmwareDomainBaseAddress);
+ fw_memregs.flags = SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREGION_READABLE;
+ Ret = sbi_domain_root_add_memregion ((const struct sbi_domain_memregion *)&fw_memregs);
+ if (Ret != 0) {
+ DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of FW Domain fail\n", __FUNCTION__));
+ }
+
+ //
+ // EDK2 EFI Variable domain memory region
+ //
+ fw_memregs.order = log2roundup(FixedPcdGet32(PcdVariableFirmwareRegionSize));
+ fw_memregs.base = FixedPcdGet32(PcdVariableFirmwareRegionBaseAddress);
+ fw_memregs.flags = SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGION_WRITEABLE;
+ Ret = sbi_domain_root_add_memregion ((const struct sbi_domain_memregion *)&fw_memregs);
+ if (Ret != 0) {
+ DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of variable FW Domain fail\n", __FUNCTION__));
+ }
+ return Ret;
+}
+
/**
Locates a section within a series of sections
with the specified section type.
@@ -405,6 +440,13 @@ SecPostOpenSbiPlatformEarlylInit(
DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId));
return 0;
}
+ //
+ // Setup firmware memory region.
+ //
+ if (SecSetEdk2FwMemoryRegions () != 0) {
+ ASSERT (FALSE);
+ }
+
//
// Boot HART is already in the process of OpenSBI initialization.
// We can let other HART to keep booting.
@@ -477,7 +519,7 @@ SecPostOpenSbiPlatformFinalInit (
}
}
- DEBUG((DEBUG_INFO, "%a: Jump to PEI Core with \n", __FUNCTION__));
+ DEBUG((DEBUG_INFO, "%a: Will jump to PEI Core in OpenSBI with \n", __FUNCTION__));
DEBUG((DEBUG_INFO, " sbi_scratch = %x\n", SbiScratch));
DEBUG((DEBUG_INFO, " sbi_platform = %x\n", SbiPlatform));
DEBUG((DEBUG_INFO, " FirmwareContext = %x\n", FirmwareContext));
@@ -793,7 +835,7 @@ VOID EFIAPI SecCoreStartUpWithStack(
sbi_init(Scratch);
}
-void OpensbiDebugPrint (char *debugstr, ...)
+VOID OpensbiDebugPrint (CHAR8 *debugstr, ...)
{
VA_LIST Marker;
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
index dc410703e0..96087738a3 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
@@ -18,6 +18,12 @@
#include <SecMain.h>
+.macro MOV_3R __d0, __s0, __d1, __s1, __d2, __s2
+ add \__d0, \__s0, zero
+ add \__d1, \__s1, zero
+ add \__d2, \__s2, zero
+.endm
+
.text
.align 3
@@ -90,7 +96,11 @@ _scratch_init:
la a4, _hartid_to_scratch
sd a4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp) /* Save _hartid_to_scratch function in scratch buffer*/
sd zero, SBI_SCRATCH_TMP0_OFFSET(tp)
-
+ /* Store trap-exit function address in scratch space */
+ lla a4, _trap_exit
+ sd a4, SBI_SCRATCH_TRAP_EXIT_OFFSET(tp)
+ /* Clear tmp0 in scratch space */
+ sd zero, SBI_SCRATCH_TMP0_OFFSET(tp)
#ifdef FW_OPTIONS
li a4, FW_OPTIONS
sd a4, SBI_SCRATCH_OPTIONS_OFFSET(tp)
@@ -322,160 +332,174 @@ _uninitialized_hart_wait:
wfi
j _uninitialized_hart_wait
- .align 3
- .section .entry, "ax", %progbits
- .align 3
- .globl _trap_handler
-_trap_handler:
-
+.macro TRAP_SAVE_AND_SETUP_SP_T0
/* Swap TP and MSCRATCH */
- csrrw tp, CSR_MSCRATCH, tp
+ csrrw tp, CSR_MSCRATCH, tp
/* Save T0 in scratch space */
- REG_S t0, SBI_SCRATCH_TMP0_OFFSET(tp)
+ REG_S t0, SBI_SCRATCH_TMP0_OFFSET(tp)
- /* Check which mode we came from */
- csrr t0, CSR_MSTATUS
- srl t0, t0, MSTATUS_MPP_SHIFT
- and t0, t0, PRV_M
- xori t0, t0, PRV_M
- beq t0, zero, _trap_handler_m_mode
-
- /* We came from S-mode or U-mode */
-_trap_handler_s_mode:
- /* Set T0 to original SP */
- add t0, sp, zero
-
- /* Setup exception stack */
- add sp, tp, -(SBI_TRAP_REGS_SIZE)
-
- /* Jump to code common for all modes */
- j _trap_handler_all_mode
-
- /* We came from M-mode */
-_trap_handler_m_mode:
- /* Set T0 to original SP */
- add t0, sp, zero
-
- /* Re-use current SP as exception stack */
- add sp, sp, -(SBI_TRAP_REGS_SIZE)
-
-_trap_handler_all_mode:
- /* Save original SP (from T0) on stack */
- REG_S t0, SBI_TRAP_REGS_OFFSET(sp)(sp)
+ /*
+ * Set T0 to appropriate exception stack
+ *
+ * Came_From_M_Mode = ((MSTATUS.MPP < PRV_M) ? 1 : 0) - 1;
+ * Exception_Stack = TP ^ (Came_From_M_Mode & (SP ^ TP))
+ *
+ * Came_From_M_Mode = 0 ==> Exception_Stack = TP
+ * Came_From_M_Mode = -1 ==> Exception_Stack = SP
+ */
+ csrr t0, CSR_MSTATUS
+ srl t0, t0, MSTATUS_MPP_SHIFT
+ and t0, t0, PRV_M
+ slti t0, t0, PRV_M
+ add t0, t0, -1
+ xor sp, sp, tp
+ and t0, t0, sp
+ xor sp, sp, tp
+ xor t0, tp, t0
+
+ /* Save original SP on exception stack */
+ REG_S sp, (SBI_TRAP_REGS_OFFSET(sp) - SBI_TRAP_REGS_SIZE)(t0)
+
+ /* Set SP to exception stack and make room for trap registers */
+ add sp, t0, -(SBI_TRAP_REGS_SIZE)
/* Restore T0 from scratch space */
- REG_L t0, SBI_SCRATCH_TMP0_OFFSET(tp)
+ REG_L t0, SBI_SCRATCH_TMP0_OFFSET(tp)
/* Save T0 on stack */
- REG_S t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
+ REG_S t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
/* Swap TP and MSCRATCH */
- csrrw tp, CSR_MSCRATCH, tp
+ csrrw tp, CSR_MSCRATCH, tp
+.endm
+.macro TRAP_SAVE_MEPC_MSTATUS have_mstatush
/* Save MEPC and MSTATUS CSRs */
- csrr t0, CSR_MEPC
- REG_S t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
- csrr t0, CSR_MSTATUS
- REG_S t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
- REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
-#if __riscv_xlen == 32
- csrr t0, CSR_MISA
- srli t0, t0, ('H' - 'A')
- andi t0, t0, 0x1
- beq t0, zero, _skip_mstatush_save
- csrr t0, CSR_MSTATUSH
- REG_S t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
-_skip_mstatush_save:
-#endif
+ csrr t0, CSR_MEPC
+ REG_S t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
+ csrr t0, CSR_MSTATUS
+ REG_S t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
+.if \have_mstatush
+ csrr t0, CSR_MSTATUSH
+ REG_S t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
+.else
+ REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
+.endif
+.endm
+
+.macro TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0
+ /* Save all general regisers except SP and T0 */
+ REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp)
+ REG_S ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
+ REG_S gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
+ REG_S tp, SBI_TRAP_REGS_OFFSET(tp)(sp)
+ REG_S t1, SBI_TRAP_REGS_OFFSET(t1)(sp)
+ REG_S t2, SBI_TRAP_REGS_OFFSET(t2)(sp)
+ REG_S s0, SBI_TRAP_REGS_OFFSET(s0)(sp)
+ REG_S s1, SBI_TRAP_REGS_OFFSET(s1)(sp)
+ REG_S a0, SBI_TRAP_REGS_OFFSET(a0)(sp)
+ REG_S a1, SBI_TRAP_REGS_OFFSET(a1)(sp)
+ REG_S a2, SBI_TRAP_REGS_OFFSET(a2)(sp)
+ REG_S a3, SBI_TRAP_REGS_OFFSET(a3)(sp)
+ REG_S a4, SBI_TRAP_REGS_OFFSET(a4)(sp)
+ REG_S a5, SBI_TRAP_REGS_OFFSET(a5)(sp)
+ REG_S a6, SBI_TRAP_REGS_OFFSET(a6)(sp)
+ REG_S a7, SBI_TRAP_REGS_OFFSET(a7)(sp)
+ REG_S s2, SBI_TRAP_REGS_OFFSET(s2)(sp)
+ REG_S s3, SBI_TRAP_REGS_OFFSET(s3)(sp)
+ REG_S s4, SBI_TRAP_REGS_OFFSET(s4)(sp)
+ REG_S s5, SBI_TRAP_REGS_OFFSET(s5)(sp)
+ REG_S s6, SBI_TRAP_REGS_OFFSET(s6)(sp)
+ REG_S s7, SBI_TRAP_REGS_OFFSET(s7)(sp)
+ REG_S s8, SBI_TRAP_REGS_OFFSET(s8)(sp)
+ REG_S s9, SBI_TRAP_REGS_OFFSET(s9)(sp)
+ REG_S s10, SBI_TRAP_REGS_OFFSET(s10)(sp)
+ REG_S s11, SBI_TRAP_REGS_OFFSET(s11)(sp)
+ REG_S t3, SBI_TRAP_REGS_OFFSET(t3)(sp)
+ REG_S t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
+ REG_S t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
+ REG_S t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
+.endm
+
+.macro TRAP_CALL_C_ROUTINE
+ /* Call C routine */
+ add a0, sp, zero
+ call sbi_trap_handler
+.endm
+
+.macro TRAP_RESTORE_GENERAL_REGS_EXCEPT_A0_T0
+ /* Restore all general regisers except A0 and T0 */
+ REG_L ra, SBI_TRAP_REGS_OFFSET(ra)(a0)
+ REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(a0)
+ REG_L gp, SBI_TRAP_REGS_OFFSET(gp)(a0)
+ REG_L tp, SBI_TRAP_REGS_OFFSET(tp)(a0)
+ REG_L t1, SBI_TRAP_REGS_OFFSET(t1)(a0)
+ REG_L t2, SBI_TRAP_REGS_OFFSET(t2)(a0)
+ REG_L s0, SBI_TRAP_REGS_OFFSET(s0)(a0)
+ REG_L s1, SBI_TRAP_REGS_OFFSET(s1)(a0)
+ REG_L a1, SBI_TRAP_REGS_OFFSET(a1)(a0)
+ REG_L a2, SBI_TRAP_REGS_OFFSET(a2)(a0)
+ REG_L a3, SBI_TRAP_REGS_OFFSET(a3)(a0)
+ REG_L a4, SBI_TRAP_REGS_OFFSET(a4)(a0)
+ REG_L a5, SBI_TRAP_REGS_OFFSET(a5)(a0)
+ REG_L a6, SBI_TRAP_REGS_OFFSET(a6)(a0)
+ REG_L a7, SBI_TRAP_REGS_OFFSET(a7)(a0)
+ REG_L s2, SBI_TRAP_REGS_OFFSET(s2)(a0)
+ REG_L s3, SBI_TRAP_REGS_OFFSET(s3)(a0)
+ REG_L s4, SBI_TRAP_REGS_OFFSET(s4)(a0)
+ REG_L s5, SBI_TRAP_REGS_OFFSET(s5)(a0)
+ REG_L s6, SBI_TRAP_REGS_OFFSET(s6)(a0)
+ REG_L s7, SBI_TRAP_REGS_OFFSET(s7)(a0)
+ REG_L s8, SBI_TRAP_REGS_OFFSET(s8)(a0)
+ REG_L s9, SBI_TRAP_REGS_OFFSET(s9)(a0)
+ REG_L s10, SBI_TRAP_REGS_OFFSET(s10)(a0)
+ REG_L s11, SBI_TRAP_REGS_OFFSET(s11)(a0)
+ REG_L t3, SBI_TRAP_REGS_OFFSET(t3)(a0)
+ REG_L t4, SBI_TRAP_REGS_OFFSET(t4)(a0)
+ REG_L t5, SBI_TRAP_REGS_OFFSET(t5)(a0)
+ REG_L t6, SBI_TRAP_REGS_OFFSET(t6)(a0)
+.endm
+
+.macro TRAP_RESTORE_MEPC_MSTATUS have_mstatush
+ /* Restore MEPC and MSTATUS CSRs */
+ REG_L t0, SBI_TRAP_REGS_OFFSET(mepc)(a0)
+ csrw CSR_MEPC, t0
+ REG_L t0, SBI_TRAP_REGS_OFFSET(mstatus)(a0)
+ csrw CSR_MSTATUS, t0
+.if \have_mstatush
+ REG_L t0, SBI_TRAP_REGS_OFFSET(mstatusH)(a0)
+ csrw CSR_MSTATUSH, t0
+.endif
+.endm
+
+.macro TRAP_RESTORE_A0_T0
+ /* Restore T0 */
+ REG_L t0, SBI_TRAP_REGS_OFFSET(t0)(a0)
- /* Save all general registers except SP and T0 */
- REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp)
- REG_S ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
- REG_S gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
- REG_S tp, SBI_TRAP_REGS_OFFSET(tp)(sp)
- REG_S t1, SBI_TRAP_REGS_OFFSET(t1)(sp)
- REG_S t2, SBI_TRAP_REGS_OFFSET(t2)(sp)
- REG_S s0, SBI_TRAP_REGS_OFFSET(s0)(sp)
- REG_S s1, SBI_TRAP_REGS_OFFSET(s1)(sp)
- REG_S a0, SBI_TRAP_REGS_OFFSET(a0)(sp)
- REG_S a1, SBI_TRAP_REGS_OFFSET(a1)(sp)
- REG_S a2, SBI_TRAP_REGS_OFFSET(a2)(sp)
- REG_S a3, SBI_TRAP_REGS_OFFSET(a3)(sp)
- REG_S a4, SBI_TRAP_REGS_OFFSET(a4)(sp)
- REG_S a5, SBI_TRAP_REGS_OFFSET(a5)(sp)
- REG_S a6, SBI_TRAP_REGS_OFFSET(a6)(sp)
- REG_S a7, SBI_TRAP_REGS_OFFSET(a7)(sp)
- REG_S s2, SBI_TRAP_REGS_OFFSET(s2)(sp)
- REG_S s3, SBI_TRAP_REGS_OFFSET(s3)(sp)
- REG_S s4, SBI_TRAP_REGS_OFFSET(s4)(sp)
- REG_S s5, SBI_TRAP_REGS_OFFSET(s5)(sp)
- REG_S s6, SBI_TRAP_REGS_OFFSET(s6)(sp)
- REG_S s7, SBI_TRAP_REGS_OFFSET(s7)(sp)
- REG_S s8, SBI_TRAP_REGS_OFFSET(s8)(sp)
- REG_S s9, SBI_TRAP_REGS_OFFSET(s9)(sp)
- REG_S s10, SBI_TRAP_REGS_OFFSET(s10)(sp)
- REG_S s11, SBI_TRAP_REGS_OFFSET(s11)(sp)
- REG_S t3, SBI_TRAP_REGS_OFFSET(t3)(sp)
- REG_S t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
- REG_S t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
- REG_S t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
+ /* Restore A0 */
+ REG_L a0, SBI_TRAP_REGS_OFFSET(a0)(a0)
+.endm
- /* Call C routine */
- add a0, sp, zero
- call sbi_trap_handler
-
- /* Restore all general registers except SP and T0 */
- REG_L ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
- REG_L gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
- REG_L tp, SBI_TRAP_REGS_OFFSET(tp)(sp)
- REG_L t1, SBI_TRAP_REGS_OFFSET(t1)(sp)
- REG_L t2, SBI_TRAP_REGS_OFFSET(t2)(sp)
- REG_L s0, SBI_TRAP_REGS_OFFSET(s0)(sp)
- REG_L s1, SBI_TRAP_REGS_OFFSET(s1)(sp)
- REG_L a0, SBI_TRAP_REGS_OFFSET(a0)(sp)
- REG_L a1, SBI_TRAP_REGS_OFFSET(a1)(sp)
- REG_L a2, SBI_TRAP_REGS_OFFSET(a2)(sp)
- REG_L a3, SBI_TRAP_REGS_OFFSET(a3)(sp)
- REG_L a4, SBI_TRAP_REGS_OFFSET(a4)(sp)
- REG_L a5, SBI_TRAP_REGS_OFFSET(a5)(sp)
- REG_L a6, SBI_TRAP_REGS_OFFSET(a6)(sp)
- REG_L a7, SBI_TRAP_REGS_OFFSET(a7)(sp)
- REG_L s2, SBI_TRAP_REGS_OFFSET(s2)(sp)
- REG_L s3, SBI_TRAP_REGS_OFFSET(s3)(sp)
- REG_L s4, SBI_TRAP_REGS_OFFSET(s4)(sp)
- REG_L s5, SBI_TRAP_REGS_OFFSET(s5)(sp)
- REG_L s6, SBI_TRAP_REGS_OFFSET(s6)(sp)
- REG_L s7, SBI_TRAP_REGS_OFFSET(s7)(sp)
- REG_L s8, SBI_TRAP_REGS_OFFSET(s8)(sp)
- REG_L s9, SBI_TRAP_REGS_OFFSET(s9)(sp)
- REG_L s10, SBI_TRAP_REGS_OFFSET(s10)(sp)
- REG_L s11, SBI_TRAP_REGS_OFFSET(s11)(sp)
- REG_L t3, SBI_TRAP_REGS_OFFSET(t3)(sp)
- REG_L t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
- REG_L t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
- REG_L t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
+ .section .entry, "ax", %progbits
+ .align 3
+ .globl _trap_handler
+ .globl _trap_exit
+_trap_handler:
+ TRAP_SAVE_AND_SETUP_SP_T0
- /* Restore MEPC and MSTATUS CSRs */
- REG_L t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
- csrw CSR_MEPC, t0
- REG_L t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
- csrw CSR_MSTATUS, t0
-#if __riscv_xlen == 32
- csrr t0, CSR_MISA
- srli t0, t0, ('H' - 'A')
- andi t0, t0, 0x1
- beq t0, zero, _skip_mstatush_restore
- REG_L t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
- csrw CSR_MSTATUSH, t0
-_skip_mstatush_restore:
-#endif
+ TRAP_SAVE_MEPC_MSTATUS 0
- /* Restore T0 */
- REG_L t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
+ TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0
+
+ TRAP_CALL_C_ROUTINE
+
+_trap_exit:
+ TRAP_RESTORE_GENERAL_REGS_EXCEPT_A0_T0
+
+ TRAP_RESTORE_MEPC_MSTATUS 0
- /* Restore SP */
- REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(sp)
+ TRAP_RESTORE_A0_T0
mret
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 28/30] RiscVPlatformPkg/Sec: Separate EDK2 Opensbi platform hook.
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (26 preceding siblings ...)
2021-10-19 8:10 ` [edk2-platforms][PATCH 27/30] RISC-V/PlatformPkg: Updates for the latest OpenSBI Abner Chang
@ 2021-10-19 8:10 ` Abner Chang
2021-10-19 8:10 ` [edk2-platforms][PATCH 29/30] RISC-V/PlatformPkg: Determine hart number from DTB Abner Chang
` (3 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Sunil V L, Daniel Schaefer
Separate EDK2 Opensbi platform operations hooks from
Secmain as an individual library which can be override
by OEM platform.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 1 +
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 4 +-
.../FreedomU500VC707Board/U500.dsc | 1 +
.../FreedomU540HiFiveUnleashedBoard/U540.dsc | 1 +
.../Edk2OpensbiPlatformWrapperLib.inf | 44 ++
.../PlatformPkg/Universal/Sec/SecMain.inf | 10 +-
.../Library/Edk2OpensbiPlatformWrapperLib.h | 16 +
.../PlatformPkg/Universal/Sec/SecMain.h | 1 +
.../Edk2OpensbiPlatformWrapperLib.c | 530 ++++++++++++++++++
.../Universal/Sec/Edk2OpenSbiPlatform.c | 277 ---------
.../PlatformPkg/Universal/Sec/SecMain.c | 141 -----
11 files changed, 600 insertions(+), 426 deletions(-)
create mode 100644 Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/Edk2OpensbiPlatformWrapperLib.h
create mode 100644 Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
delete mode 100644 Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
index 947ae40e20..19206556ce 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
@@ -20,6 +20,7 @@
[LibraryClasses]
FirmwareContextProcessorSpecificLib|Include/Library/FirmwareContextProcessorSpecificLib.h
RiscVPlatformTempMemoryInitLib|Include/Library/RiscVPlatformTempMemoryInitLib.h
+ Edk2OpensbiPlatformiLib|Include/Library/Edk2OpensbiPlatformiWrapperLib.h
[Guids]
gUefiRiscVPlatformPkgTokenSpaceGuid = {0x6A67AF99, 0x4592, 0x40F8, { 0xB6, 0xBE, 0x62, 0xBC, 0xA1, 0x0D, 0xA1, 0xEC}}
diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
index bbb043f9ed..47a0fc4494 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
@@ -43,7 +43,6 @@
RiscVOpensbiPlatformLib|Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
- RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
@@ -72,6 +71,8 @@
[LibraryClasses.common.SEC]
ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
+ RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
+ Edk2OpensbiPlatformWrapperLib|Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf
RiscVSpecialPlatformLib|Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf
[LibraryClasses.common.DXE_DRIVER]
@@ -87,6 +88,7 @@
Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf
+ Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf
[Components.common.SEC]
Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
index f14511120e..e680e330ed 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
@@ -158,6 +158,7 @@
ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
+ Edk2OpensbiPlatformWrapperLib|Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf
!ifdef $(SOURCE_DEBUG_ENABLE)
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
index c29b36e9bb..98a6a69ca3 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
@@ -165,6 +165,7 @@
ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
+ Edk2OpensbiPlatformWrapperLib|Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf
RiscVSpecialPlatformLib|Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
!ifdef $(SOURCE_DEBUG_ENABLE)
diff --git a/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf b/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf
new file mode 100644
index 0000000000..8c268c556d
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf
@@ -0,0 +1,44 @@
+## @file
+# EDK2 OpenSBI generic platform wrapper library
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = Edk2OpensbiPlatformWrapperLib
+ FILE_GUID = 364395A3-21BA-400C-96F7-5D9817F6FEE5
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = Edk2OpensbiPlatformWrapperLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ Edk2OpensbiPlatformWrapperLib.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[Pcd]
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ DebugAgentLib
+ PcdLib
+ PrintLib
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
index dd5f01ab4d..ceb6d25222 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
@@ -23,7 +23,6 @@
[Sources]
SecMain.c
- Edk2OpenSbiPlatform.c
[Sources.RISCV64]
Riscv64/SecEntry.S
@@ -40,6 +39,7 @@
BaseMemoryLib
DebugAgentLib
DebugLib
+ Edk2OpensbiPlatformWrapperLib
ExtractGuidedSectionLib
FdtLib
IoLib
@@ -62,14 +62,10 @@
[Pcd]
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize
diff --git a/Platform/RISC-V/PlatformPkg/Include/Library/Edk2OpensbiPlatformWrapperLib.h b/Platform/RISC-V/PlatformPkg/Include/Library/Edk2OpensbiPlatformWrapperLib.h
new file mode 100644
index 0000000000..4da0a64a8c
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Include/Library/Edk2OpensbiPlatformWrapperLib.h
@@ -0,0 +1,16 @@
+/** @file
+ Definition of EDK2 OpenSBI generic platform wrapper library
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef EDK2_OPENSBI_PLATFORM_WRAPPER_LIB_
+#define EDK2_OPENSBI_PLATFORM_WRAPPER_LIB_
+
+#include <sbi/sbi_platform.h>
+
+extern struct sbi_platform_operations Edk2OpensbiPlatformOps;
+
+#endif
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
index 496799efc0..6188778fc4 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
@@ -16,6 +16,7 @@
#include <Library/BaseMemoryLib.h>
#include <Library/DebugAgentLib.h>
#include <Library/DebugLib.h>
+#include <Library/Edk2OpensbiPlatformWrapperLib.h>
#include <Library/ExtractGuidedSectionLib.h>
#include <Library/IoLib.h>
#include <Library/HobLib.h>
diff --git a/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c b/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
new file mode 100644
index 0000000000..6c5c1a789f
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
@@ -0,0 +1,530 @@
+/*
+ EDK2 OpenSBI generic platform wrapper library
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ */
+
+#include <Library/DebugAgentLib.h>
+#include <Library/DebugLib.h>
+#include <IndustryStandard/RiscVOpensbi.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_domain.h>
+#include <sbi/sbi_math.h>
+
+extern struct sbi_platform_operations platform_ops;
+extern atomic_t BootHartDone;
+
+/**
+ Add firmware memory domain.
+
+ @retval OpenSBI error code.
+
+**/
+INT32
+SecSetEdk2FwMemoryRegions (
+ VOID
+ )
+{
+ INT32 Ret;
+ struct sbi_domain_memregion fw_memregs;
+
+ Ret = 0;
+
+ //
+ // EDK2 PEI domain memory region
+ //
+ fw_memregs.order = log2roundup(FixedPcdGet32(PcdFirmwareDomainSize));
+ fw_memregs.base = FixedPcdGet32(PcdFirmwareDomainBaseAddress);
+ fw_memregs.flags = SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREGION_READABLE;
+ Ret = sbi_domain_root_add_memregion ((CONST struct sbi_domain_memregion *)&fw_memregs);
+ if (Ret != 0) {
+ DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of FW Domain fail\n", __FUNCTION__));
+ }
+
+ //
+ // EDK2 EFI Variable domain memory region
+ //
+ fw_memregs.order = log2roundup(FixedPcdGet32(PcdVariableFirmwareRegionSize));
+ fw_memregs.base = FixedPcdGet32(PcdVariableFirmwareRegionBaseAddress);
+ fw_memregs.flags = SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGION_WRITEABLE;
+ Ret = sbi_domain_root_add_memregion ((CONST struct sbi_domain_memregion *)&fw_memregs);
+ if (Ret != 0) {
+ DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of variable FW Domain fail\n", __FUNCTION__));
+ }
+ return Ret;
+}
+/**
+ OpenSBI platform early init hook.
+
+ @param[in] ColdBoot Is cold boot path or warm boot path.
+ @retval OpenSBI error code.
+
+**/
+INT32
+SecPostOpenSbiPlatformEarlylInit(
+ IN BOOLEAN ColdBoot
+ )
+{
+ UINT32 HartId;
+
+ if (!ColdBoot) {
+ HartId = current_hartid();
+ DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId));
+ return 0;
+ }
+ //
+ // Setup firmware memory region.
+ //
+ if (SecSetEdk2FwMemoryRegions () != 0) {
+ ASSERT (FALSE);
+ }
+
+ //
+ // Boot HART is already in the process of OpenSBI initialization.
+ // We can let other HART to keep booting.
+ //
+ DEBUG ((DEBUG_INFO, "%a: Set boot hart done.\n", __FUNCTION__));
+ atomic_write (&BootHartDone, (UINT64)TRUE);
+ return 0;
+}
+
+/**
+ OpenSBI platform final init hook.
+ We restore the next_arg1 to the pointer of EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT.
+
+ @param[in] ColdBoot Is cold boot path or warm boot path.
+ @retval OpenSBI error code.
+
+**/
+INT32
+SecPostOpenSbiPlatformFinalInit (
+ IN BOOLEAN ColdBoot
+ )
+{
+ UINT32 HartId;
+ struct sbi_scratch *SbiScratch;
+ struct sbi_scratch *ScratchSpace;
+ struct sbi_platform *SbiPlatform;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+
+ if (!ColdBoot) {
+ HartId = current_hartid();
+ DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId));
+ return 0;
+ }
+
+ DEBUG((DEBUG_INFO, "%a: Entry, preparing to jump to PEI Core\n\n", __FUNCTION__));
+
+ SbiScratch = sbi_scratch_thishart_ptr();
+ SbiPlatform = (struct sbi_platform *)sbi_platform_ptr(SbiScratch);
+ FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)SbiPlatform->firmware_context;
+
+ //
+ // Print out scratch address of each hart
+ //
+ DEBUG ((DEBUG_INFO, "%a: OpenSBI scratch address for each hart:\n", __FUNCTION__));
+ for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
+ if (sbi_platform_hart_invalid(SbiPlatform, HartId)) {
+ continue;
+ }
+ ScratchSpace = sbi_hartid_to_scratch (HartId);
+ if(ScratchSpace != NULL) {
+ DEBUG((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, ScratchSpace));
+ } else {
+ DEBUG((DEBUG_INFO, " Hart %d not initialized yet\n", HartId));
+ }
+ }
+
+ //
+ // Set firmware context Hart-specific pointer
+ //
+ for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
+ if (sbi_platform_hart_invalid(SbiPlatform, HartId)) {
+ continue;
+ }
+ ScratchSpace = sbi_hartid_to_scratch (HartId);
+ if (ScratchSpace != NULL) {
+ FirmwareContext->HartSpecific[HartId] =
+ (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)ScratchSpace - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE);
+ DEBUG ((DEBUG_INFO, "%a: OpenSBI Hart %d Firmware Context Hart-specific at address: 0x%x\n",
+ __FUNCTION__,
+ HartId,
+ FirmwareContext->HartSpecific [HartId]
+ ));
+ }
+ }
+
+ DEBUG((DEBUG_INFO, "%a: Will jump to PEI Core in OpenSBI with \n", __FUNCTION__));
+ DEBUG((DEBUG_INFO, " sbi_scratch = %x\n", SbiScratch));
+ DEBUG((DEBUG_INFO, " sbi_platform = %x\n", SbiPlatform));
+ DEBUG((DEBUG_INFO, " FirmwareContext = %x\n", FirmwareContext));
+ SbiScratch->next_arg1 = (unsigned long)FirmwareContext;
+
+ return 0;
+}
+/**
+ OpenSBI platform early init hook.
+
+ @param[in] ColdBoot Is cold boot path or warm boot path.
+ @retval OpenSBI error code.
+
+**/
+INT32
+Edk2OpensbiPlatformEarlyInit (
+ IN BOOLEAN ColdBoot
+ )
+{
+ INT32 ReturnCode;
+
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.early_init) {
+ ReturnCode = platform_ops.early_init (ColdBoot);
+ if (ReturnCode) {
+ return ReturnCode;
+ }
+ }
+ if (ColdBoot == TRUE) {
+ return SecPostOpenSbiPlatformEarlylInit(ColdBoot);
+ }
+ return 0;
+}
+/**
+ OpenSBI platform final init hook.
+
+ @param[in] ColdBoot Is cold boot path or warm boot path.
+ @retval OpenSBI error code.
+
+**/
+INT32
+Edk2OpensbiPlatformFinalInit (
+ IN BOOLEAN ColdBoot
+ )
+{
+ INT32 ReturnCode;
+
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.final_init) {
+ ReturnCode = platform_ops.final_init (ColdBoot);
+ if (ReturnCode) {
+ return ReturnCode;
+ }
+ }
+ if (ColdBoot == TRUE) {
+ return SecPostOpenSbiPlatformFinalInit(ColdBoot);
+ }
+ return 0;
+}
+/**
+ OpenSBI platform early exit hook.
+
+**/
+VOID
+Edk2OpensbiPlatformEarlyExit (
+ VOID
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.early_exit) {
+ return platform_ops.early_exit ();
+ }
+}
+
+/**
+ Platform final exit hook
+
+ **/
+VOID
+Edk2OpensbiPlatformFinalExit (
+ VOID
+ )
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.early_exit) {
+ return platform_ops.early_exit ();
+ }
+}
+
+/**
+ For platforms that do not implement misa, non-standard
+ methods are needed to determine cpu extension.
+
+ @param[in] Extension Check ISA extension.
+ @retval OpenSBI error code.
+
+**/
+INT32
+Edk2OpensbiPlatforMMISACheckExtension (
+ IN CHAR8 Extension
+ )
+{
+ if (platform_ops.misa_check_extension) {
+ return platform_ops.misa_check_extension (Extension);
+ }
+ return 0;
+}
+
+/**
+ Get the XLEN.
+
+ @retval Return the XLEN
+
+**/
+INT32
+Edk2OpensbiPlatforMMISAGetXLEN (
+ VOID
+)
+{
+ if (platform_ops.misa_get_xlen) {
+ return platform_ops.misa_get_xlen ();
+ }
+ return 0;
+}
+
+/**
+ Initialize (or populate) domains for the platform*
+
+ @retval OpenSBI error code.
+
+**/
+INT32
+Edk2OpensbiPlatformDomainsInit (
+ VOID
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.domains_init) {
+ return platform_ops.domains_init ();
+ }
+ return 0;
+}
+
+/**
+ Initialize the platform console
+
+ @retval OpenSBI error code.
+
+**/
+INT32
+Edk2OpensbiPlatformSerialInit (
+ VOID
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.console_init) {
+ return platform_ops.console_init ();
+ }
+ return 0;
+}
+
+/**
+ Initialize the platform interrupt controller for current HART
+
+ @param[in] ColdBoot Is cold boot path or warm boot path.
+ @retval OpenSBI error code.
+
+**/
+INT32
+Edk2OpensbiPlatformIrqchipInit (
+ IN BOOLEAN ColdBoot
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.irqchip_init) {
+ return platform_ops.irqchip_init (ColdBoot);
+ }
+ return 0;
+}
+
+/**
+ Exit the platform interrupt controller for current HART
+
+**/
+VOID
+Edk2OpensbiPlatformIrqchipExit (
+ VOID
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.irqchip_exit) {
+ return platform_ops.irqchip_exit ();
+ }
+}
+
+/**
+ Initialize IPI for current HART
+
+ @param[in] ColdBoot Is cold boot path or warm boot path.
+ @retval OpenSBI error code.
+
+**/
+INT32
+Edk2OpensbiPlatformIpiInit (
+ IN BOOLEAN ColdBoot
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.ipi_init) {
+ return platform_ops.ipi_init (ColdBoot);
+ }
+ return 0;
+}
+
+/**
+ Exit IPI for current HART
+
+**/
+VOID
+Edk2OpensbiPlatformIpiExit (
+ VOID
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.ipi_exit) {
+ return platform_ops.ipi_exit ();
+ }
+}
+
+/**
+ Get tlb flush limit value
+
+ @retval Cache flush limit value.
+
+**/
+UINT64
+Edk2OpensbiPlatformTlbrFlushLimit (
+ VOID
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.get_tlbr_flush_limit) {
+ return platform_ops.get_tlbr_flush_limit ();
+ }
+ return 0;
+}
+
+/**
+ Initialize platform timer for current HART
+
+ @param[in] ColdBoot Is cold boot path or warm boot path.
+ @retval OpenSBI error code.
+
+**/
+INT32
+Edk2OpensbiPlatformTimerInit (
+ IN BOOLEAN ColdBoot
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.timer_init) {
+ return platform_ops.timer_init (ColdBoot);
+ }
+ return 0;
+}
+
+/**
+ Exit platform timer for current HART
+
+**/
+VOID
+Edk2OpensbiPlatformTimerExit (
+ VOID
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.timer_exit) {
+ return platform_ops.timer_exit ();
+ }
+}
+
+/**
+ Check platform vendor SBI extension.
+
+ @param[in] ExtId Extension ID.
+ @retval OpenSBI error code.
+
+ **/
+INT32
+Edk2OpensbiPlatformVendorExtCheck (
+ IN long ExtId
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.vendor_ext_check) {
+ return platform_ops.vendor_ext_check (ExtId);
+ }
+ return 0;
+}
+
+/**
+ Platform specific SBI extension implementation provider
+
+ @param[in] ExtId SBI extension ID.
+ @param[in] FuncId Function ID.
+ @param[in] Regs The trap register.
+ @param[in] OutValue Value returned from SBI.
+ @param[in] OutTrap The trap infomation after calling to SBI.
+
+ @retval OpenSBI error code.
+
+**/
+INT32
+Edk2OpensbiPlatformVendorExtProvider (
+ IN long ExtId,
+ IN long FuncId,
+ IN CONST struct sbi_trap_regs *Regs,
+ IN unsigned long *OutValue,
+ IN struct sbi_trap_info *OutTrap
+)
+{
+ DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ if (platform_ops.vendor_ext_provider) {
+ return platform_ops.vendor_ext_provider (
+ ExtId,
+ FuncId,
+ Regs,
+ OutValue,
+ OutTrap
+ );
+ }
+ return 0;
+}
+
+CONST struct sbi_platform_operations Edk2OpensbiPlatformOps = {
+ .early_init = Edk2OpensbiPlatformEarlyInit,
+ .final_init = Edk2OpensbiPlatformFinalInit,
+ .early_exit = Edk2OpensbiPlatformEarlyExit,
+ .final_exit = Edk2OpensbiPlatformFinalExit,
+ .misa_check_extension = Edk2OpensbiPlatforMMISACheckExtension,
+ .misa_get_xlen = Edk2OpensbiPlatforMMISAGetXLEN,
+ .domains_init = Edk2OpensbiPlatformDomainsInit,
+ .console_init = Edk2OpensbiPlatformSerialInit,
+ .irqchip_init = Edk2OpensbiPlatformIrqchipInit,
+ .irqchip_exit = Edk2OpensbiPlatformIrqchipExit,
+ .ipi_init = Edk2OpensbiPlatformIpiInit,
+ .ipi_exit = Edk2OpensbiPlatformIpiExit,
+ .get_tlbr_flush_limit = Edk2OpensbiPlatformTlbrFlushLimit,
+ .timer_init = Edk2OpensbiPlatformTimerInit,
+ .timer_exit = Edk2OpensbiPlatformTimerExit,
+ .vendor_ext_check = Edk2OpensbiPlatformVendorExtCheck,
+ .vendor_ext_provider = Edk2OpensbiPlatformVendorExtProvider,
+};
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c
deleted file mode 100644
index 779705489c..0000000000
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Edk2OpenSbiPlatform.c
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
- */
-
-#include <Library/DebugAgentLib.h>
-#include <Library/DebugLib.h>
-
-#include <libfdt.h>
-#include <sbi/riscv_asm.h>
-#include <sbi/sbi_domain.h>
-#include <sbi/sbi_hartmask.h>
-#include <sbi/sbi_platform.h>
-#include <sbi/sbi_string.h>
-#include <sbi/sbi_math.h>
-#include <sbi_utils/fdt/fdt_domain.h>
-#include <sbi_utils/fdt/fdt_fixup.h>
-#include <sbi_utils/fdt/fdt_helper.h>
-#include <sbi_utils/irqchip/fdt_irqchip.h>
-#include <sbi_utils/serial/fdt_serial.h>
-#include <sbi_utils/timer/fdt_timer.h>
-#include <sbi_utils/ipi/fdt_ipi.h>
-#include <sbi_utils/reset/fdt_reset.h>
-
-#include "SecMain.h"
-
-extern struct sbi_platform_operations platform_ops;
-
-int Edk2OpensbiPlatformEarlyInit (
- BOOLEAN ColdBoot
- )
-{
- int ReturnCode;
-
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.early_init) {
- ReturnCode = platform_ops.early_init (ColdBoot);
- if (ReturnCode) {
- return ReturnCode;
- }
- }
- if (ColdBoot == TRUE) {
- return SecPostOpenSbiPlatformEarlylInit(ColdBoot);
- }
- return 0;
-}
-
-int Edk2OpensbiPlatformFinalInit (
- BOOLEAN ColdBoot
- )
-{
- int ReturnCode;
-
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.final_init) {
- ReturnCode = platform_ops.final_init (ColdBoot);
- if (ReturnCode) {
- return ReturnCode;
- }
- }
- if (ColdBoot == TRUE) {
- return SecPostOpenSbiPlatformFinalInit(ColdBoot);
- }
- return 0;
-}
-
-VOID Edk2OpensbiPlatformEarlyExit (
- VOID
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.early_exit) {
- return platform_ops.early_exit ();
- }
-}
-
-/** Platform final exit */
-VOID Edk2OpensbiPlatformFinalExit (
- VOID
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.early_exit) {
- return platform_ops.early_exit ();
- }
-}
-
-/**
- For platforms that do not implement misa, non-standard
- methods are needed to determine cpu extension.
-**/
-int Edk2OpensbiPlatforMMISACheckExtension (
- CHAR8 Extension
- )
-{
- if (platform_ops.misa_check_extension) {
- return platform_ops.misa_check_extension (Extension);
- }
- return 0;
-}
-
-/**
- For platforms that do not implement misa, non-standard
- methods are needed to get MXL field of misa.
-**/
-int Edk2OpensbiPlatforMMISAGetXLEN (VOID)
-{
- if (platform_ops.misa_get_xlen) {
- return platform_ops.misa_get_xlen ();
- }
- return 0;
-}
-
-/** Initialize (or populate) domains for the platform */
-int Edk2OpensbiPlatformDomainsInit (VOID)
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.domains_init) {
- return platform_ops.domains_init ();
- }
- return 0;
-}
-
-/** Initialize the platform console */
-int Edk2OpensbiPlatformSerialInit (VOID)
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.console_init) {
- return platform_ops.console_init ();
- }
- return 0;
-}
-
-/** Initialize the platform interrupt controller for current HART */
-int Edk2OpensbiPlatformIrqchipInit (
- BOOLEAN ColdBoot
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.irqchip_init) {
- return platform_ops.irqchip_init (ColdBoot);
- }
- return 0;
-}
-
-/** Exit the platform interrupt controller for current HART */
-VOID Edk2OpensbiPlatformIrqchipExit (VOID)
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.irqchip_exit) {
- return platform_ops.irqchip_exit ();
- }
-}
-
-/** Initialize IPI for current HART */
-int Edk2OpensbiPlatformIpiInit (
- BOOLEAN ColdBoot
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.ipi_init) {
- return platform_ops.ipi_init (ColdBoot);
- }
- return 0;
-}
-
-/** Exit IPI for current HART */
-VOID Edk2OpensbiPlatformIpiExit (VOID)
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.ipi_exit) {
- return platform_ops.ipi_exit ();
- }
-}
-
-/** Get tlb flush limit value **/
-UINT64 Edk2OpensbiPlatformTlbrFlushLimit (VOID)
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.get_tlbr_flush_limit) {
- return platform_ops.get_tlbr_flush_limit ();
- }
- return 0;
-}
-
-/** Initialize platform timer for current HART */
-int Edk2OpensbiPlatformTimerInit (
- BOOLEAN ColdBoot
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.timer_init) {
- return platform_ops.timer_init (ColdBoot);
- }
- return 0;
-}
-
-/** Exit platform timer for current HART */
-VOID Edk2OpensbiPlatformTimerExit (VOID)
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.timer_exit) {
- return platform_ops.timer_exit ();
- }
-}
-
-/** platform specific SBI extension implementation probe function */
-int Edk2OpensbiPlatformVendorExtCheck (
- long ExtId
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.vendor_ext_check) {
- return platform_ops.vendor_ext_check (ExtId);
- }
- return 0;
-}
-
-
-/** platform specific SBI extension implementation provider */
-int Edk2OpensbiPlatformVendorExtProvider (
- long ExtId,
- long FuncId,
- const struct sbi_trap_regs *Regs,
- unsigned long *OutValue,
- struct sbi_trap_info *OutTrap
- )
-{
- DEBUG((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
-
- if (platform_ops.vendor_ext_provider) {
- return platform_ops.vendor_ext_provider (
- ExtId,
- FuncId,
- Regs,
- OutValue,
- OutTrap
- );
- }
- return 0;
-}
-
-const struct sbi_platform_operations Edk2OpensbiPlatformOps = {
- .early_init = Edk2OpensbiPlatformEarlyInit,
- .final_init = Edk2OpensbiPlatformFinalInit,
- .early_exit = Edk2OpensbiPlatformEarlyExit,
- .final_exit = Edk2OpensbiPlatformFinalExit,
- .misa_check_extension = Edk2OpensbiPlatforMMISACheckExtension,
- .misa_get_xlen = Edk2OpensbiPlatforMMISAGetXLEN,
- .domains_init = Edk2OpensbiPlatformDomainsInit,
- .console_init = Edk2OpensbiPlatformSerialInit,
- .irqchip_init = Edk2OpensbiPlatformIrqchipInit,
- .irqchip_exit = Edk2OpensbiPlatformIrqchipExit,
- .ipi_init = Edk2OpensbiPlatformIpiInit,
- .ipi_exit = Edk2OpensbiPlatformIpiExit,
- .get_tlbr_flush_limit = Edk2OpensbiPlatformTlbrFlushLimit,
- .timer_init = Edk2OpensbiPlatformTimerInit,
- .timer_exit = Edk2OpensbiPlatformTimerExit,
- .vendor_ext_check = Edk2OpensbiPlatformVendorExtCheck,
- .vendor_ext_provider = Edk2OpensbiPlatformVendorExtProvider,
-};
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index 3bc3690047..f2b2c7b583 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -25,49 +25,12 @@
#include <sbi/sbi_ecall.h> // Reference to header file in opensbi
#include <sbi/sbi_trap.h> // Reference to header file in opensbi
-extern struct sbi_platform_operations Edk2OpensbiPlatformOps;
-
//
// Indicates the boot hart (PcdBootHartId) OpenSBI initialization is done.
//
atomic_t BootHartDone = ATOMIC_INITIALIZER(0);
atomic_t NonBootHartMessageLock = ATOMIC_INITIALIZER(0);
-int sbi_domain_root_add_memregion(const struct sbi_domain_memregion *reg);
-
-typedef struct sbi_scratch *(*hartid2scratch)(ulong hartid, ulong hartindex);
-
-struct sbi_domain_memregion fw_memregs;
-
-int SecSetEdk2FwMemoryRegions (VOID) {
- int Ret;
-
- Ret = 0;
-
- //
- // EDK2 PEI domain memory region
- //
- fw_memregs.order = log2roundup(FixedPcdGet32(PcdFirmwareDomainSize));
- fw_memregs.base = FixedPcdGet32(PcdFirmwareDomainBaseAddress);
- fw_memregs.flags = SBI_DOMAIN_MEMREGION_EXECUTABLE | SBI_DOMAIN_MEMREGION_READABLE;
- Ret = sbi_domain_root_add_memregion ((const struct sbi_domain_memregion *)&fw_memregs);
- if (Ret != 0) {
- DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of FW Domain fail\n", __FUNCTION__));
- }
-
- //
- // EDK2 EFI Variable domain memory region
- //
- fw_memregs.order = log2roundup(FixedPcdGet32(PcdVariableFirmwareRegionSize));
- fw_memregs.base = FixedPcdGet32(PcdVariableFirmwareRegionBaseAddress);
- fw_memregs.flags = SBI_DOMAIN_MEMREGION_READABLE | SBI_DOMAIN_MEMREGION_WRITEABLE;
- Ret = sbi_domain_root_add_memregion ((const struct sbi_domain_memregion *)&fw_memregs);
- if (Ret != 0) {
- DEBUG ((DEBUG_ERROR, "%a: Add firmware regiosn of variable FW Domain fail\n", __FUNCTION__));
- }
- return Ret;
-}
-
/**
Locates a section within a series of sections
with the specified section type.
@@ -424,109 +387,6 @@ RegisterFirmwareSbiExtension (
return EFI_SUCCESS;
}
-/**
- OpenSBI platform early init hook.
-
-**/
-int
-SecPostOpenSbiPlatformEarlylInit(
- IN BOOLEAN ColdBoot
- )
-{
- UINT32 HartId;
-
- if (!ColdBoot) {
- HartId = current_hartid();
- DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId));
- return 0;
- }
- //
- // Setup firmware memory region.
- //
- if (SecSetEdk2FwMemoryRegions () != 0) {
- ASSERT (FALSE);
- }
-
- //
- // Boot HART is already in the process of OpenSBI initialization.
- // We can let other HART to keep booting.
- //
- DEBUG ((DEBUG_INFO, "%a: Set boot hart done.\n", __FUNCTION__));
- atomic_write (&BootHartDone, (UINT64)TRUE);
- return 0;
-}
-
-/**
- OpenSBI platform final init hook.
- We restore the next_arg1 to the pointer of EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT.
-
-**/
-int
-SecPostOpenSbiPlatformFinalInit (
- IN BOOLEAN ColdBoot
- )
-{
- UINT32 HartId;
- struct sbi_scratch *SbiScratch;
- struct sbi_scratch *ScratchSpace;
- struct sbi_platform *SbiPlatform;
- EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
-
- if (!ColdBoot) {
- HartId = current_hartid();
- DEBUG ((DEBUG_INFO, "%a: Non boot hart %d.\n", __FUNCTION__, HartId));
- return 0;
- }
-
- DEBUG((DEBUG_INFO, "%a: Entry, preparing to jump to PEI Core\n\n", __FUNCTION__));
-
- SbiScratch = sbi_scratch_thishart_ptr();
- SbiPlatform = (struct sbi_platform *)sbi_platform_ptr(SbiScratch);
- FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)SbiPlatform->firmware_context;
-
- //
- // Print out scratch address of each hart
- //
- DEBUG ((DEBUG_INFO, "%a: OpenSBI scratch address for each hart:\n", __FUNCTION__));
- for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
- if (sbi_platform_hart_invalid(SbiPlatform, HartId)) {
- continue;
- }
- ScratchSpace = sbi_hartid_to_scratch (HartId);
- if(ScratchSpace != NULL) {
- DEBUG((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, ScratchSpace));
- } else {
- DEBUG((DEBUG_INFO, " Hart %d not initialized yet\n", HartId));
- }
- }
-
- //
- // Set firmware context Hart-specific pointer
- //
- for (HartId = 0; HartId < SBI_HARTMASK_MAX_BITS; HartId ++) {
- if (sbi_platform_hart_invalid(SbiPlatform, HartId)) {
- continue;
- }
- ScratchSpace = sbi_hartid_to_scratch (HartId);
- if (ScratchSpace != NULL) {
- FirmwareContext->HartSpecific[HartId] =
- (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)ScratchSpace - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE);
- DEBUG ((DEBUG_INFO, "%a: OpenSBI Hart %d Firmware Context Hart-specific at address: 0x%x\n",
- __FUNCTION__,
- HartId,
- FirmwareContext->HartSpecific [HartId]
- ));
- }
- }
-
- DEBUG((DEBUG_INFO, "%a: Will jump to PEI Core in OpenSBI with \n", __FUNCTION__));
- DEBUG((DEBUG_INFO, " sbi_scratch = %x\n", SbiScratch));
- DEBUG((DEBUG_INFO, " sbi_platform = %x\n", SbiPlatform));
- DEBUG((DEBUG_INFO, " FirmwareContext = %x\n", FirmwareContext));
- SbiScratch->next_arg1 = (unsigned long)FirmwareContext;
-
- return 0;
-}
/** Transion from SEC phase to PEI phase.
@@ -787,7 +647,6 @@ VOID EFIAPI SecCoreStartUpWithStack(
//
ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(Scratch);
ThisSbiPlatform->platform_ops_addr = (unsigned long)&Edk2OpensbiPlatformOps;
-
if (HartId == FixedPcdGet32(PcdBootHartId)) {
Scratch->next_arg1 = (unsigned long)GetDeviceTreeAddress ();
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 29/30] RISC-V/PlatformPkg: Determine hart number from DTB
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (27 preceding siblings ...)
2021-10-19 8:10 ` [edk2-platforms][PATCH 28/30] RiscVPlatformPkg/Sec: Separate EDK2 Opensbi platform hook Abner Chang
@ 2021-10-19 8:10 ` Abner Chang
2021-10-19 8:10 ` [edk2-platforms][PATCH 30/30] Silicon/RISC-V: Add PciCpuIoDxe driver Abner Chang
` (2 subsequent siblings)
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Determine total number of hart from DTB instead of
using PCD.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
.../U540.fdf.inc | 1 -
.../OpensbiPlatformLib/OpensbiPlatformLib.inf | 3 -
.../PlatformPkg/Universal/Sec/SecMain.inf | 1 -
.../PlatformPkg/Universal/Sec/SecMain.c | 12 ++--
.../Universal/Sec/Riscv64/SecEntry.S | 60 +++++++++++++------
5 files changed, 49 insertions(+), 28 deletions(-)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
index 1a525dc874..404c0b71ca 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.inc
@@ -90,7 +90,6 @@ SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize = 0x10000
SET gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz = 1000000
SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock = 1000000000 # 1GHz system clock
-SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount = 5 # Total cores on U540 platform
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId = 1 # Boot hart ID
#
diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
index 2e1227733a..6661ee8204 100644
--- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
+++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
@@ -46,9 +46,6 @@
RiscVSpecialPlatformLib
[FixedPcd]
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
index ceb6d25222..b949b6c470 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf
@@ -61,7 +61,6 @@
[Pcd]
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index f2b2c7b583..17f33a02cc 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -530,7 +530,7 @@ GetDeviceTreeAddress (
EFI_COMMON_SECTION_HEADER *FoundSection;
if (FixedPcdGet32 (PcdDeviceTreeAddress)) {
- DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddress 0x%x.\n", FixedPcdGet32 (PcdDeviceTreeAddress)));
+ DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddress 0x%x 0x%x.\n", FixedPcdGet32 (PcdDeviceTreeAddress), *((unsigned long *)FixedPcdGet32 (PcdDeviceTreeAddress))));
//
// Device tree address is pointed by PcdDeviceTreeAddress.
//
@@ -647,11 +647,10 @@ VOID EFIAPI SecCoreStartUpWithStack(
//
ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(Scratch);
ThisSbiPlatform->platform_ops_addr = (unsigned long)&Edk2OpensbiPlatformOps;
+ Scratch->next_arg1 = (unsigned long)GetDeviceTreeAddress ();
if (HartId == FixedPcdGet32(PcdBootHartId)) {
-
- Scratch->next_arg1 = (unsigned long)GetDeviceTreeAddress ();
if (Scratch->next_arg1 == (unsigned long)NULL) {
- DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n"));
+ DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found on boot hart\n"));
ASSERT (FALSE);
}
DEBUG ((DEBUG_INFO, "Device Tree at 0x%x\n", Scratch->next_arg1));
@@ -685,6 +684,11 @@ VOID EFIAPI SecCoreStartUpWithStack(
NonBootHartMessageLockValue = atomic_xchg(&NonBootHartMessageLock, TRUE);
};
DEBUG((DEBUG_INFO, "%a: Non boot hart %d initialization.\n", __FUNCTION__, HartId));
+ if (Scratch->next_arg1 == (unsigned long)NULL) {
+ DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n"));
+ ASSERT (FALSE);
+ }
+ DEBUG((DEBUG_INFO, "%a: Non boot hart %d DTB is at 0x%x.\n", __FUNCTION__, HartId, Scratch->next_arg1));
NonBootHartMessageLockValue = atomic_xchg(&NonBootHartMessageLock, FALSE);
//
// Non boot hart wiil be halted waiting for SBI_HART_STARTING.
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
index 96087738a3..0fc7817665 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
@@ -37,14 +37,39 @@ ASM_FUNC (_ModuleEntryPoint)
li a5, FixedPcdGet32 (PcdBootHartId)
bne a6, a5, _wait_for_boot_hart
- li ra, 0
- call _reset_regs
+ /*
+ * Initial the hart count reported in DTB
+ */
+ li a4, FixedPcdGet32 (PcdTemporaryRamBase)
+ li a5, FixedPcdGet32 (PcdTemporaryRamSize)
+ /* Use Temp memory as the stack for calling to C code */
+ add sp, a4, a5
+ /* Get the address of device tree and call generic fw_platform_init */
+ call GetDeviceTreeAddress /* a0 return the device tree address */
+ beqz a0, skip_fw_init
+ add a1, a0, 0 /* a1 is device tree */
+ csrr a0, CSR_MHARTID /* a0 is boot hart ID */
+ call fw_platform_init
+skip_fw_init:
/* Preload HART details
- * s7 -> HART Count
+ * s7 -> Total HART count from PCD or DTB
* s8 -> HART Stack Size
*/
- li s7, FixedPcdGet32 (PcdHartCount)
+ la a0, platform
+#if __riscv_xlen == 64
+ lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a0)
+#else
+ lw s7, SBI_PLATFORM_HART_COUNT_OFFSET(a0)
+#endif
+ /*
+ * This is the number of HARTs described in
+ * DTB for this processor. We allocate the
+ * scratch buffer according to this number.
+ */
+ la a4, _pysical_hart_count
+ sd s7, (a4)
+
li s8, FixedPcdGet32 (PcdOpenSbiStackSize)
/*
@@ -113,20 +138,9 @@ _scratch_init:
li a4, FixedPcdGet32 (PcdTemporaryRamBase)
li a5, FixedPcdGet32 (PcdTemporaryRamSize)
-
/* Use Temp memory as the stack for calling to C code */
add sp, a4, a5
- /* Get the address of device tree and call generic fw_platform_init */
- call GetDeviceTreeAddress /* a0 return the device tree address */
- beqz a0, skip_fw_init
- add a1, a0, 0 /* a1 is device tree */
- csrr a0, CSR_MHARTID /* a0 is hart ID */
- call fw_platform_init
-skip_fw_init:
-
/* Zero out temporary memory */
- li a4, FixedPcdGet32 (PcdTemporaryRamBase)
- li a5, FixedPcdGet32 (PcdTemporaryRamSize)
add a5, a4, a5
1:
li a3, 0x0
@@ -167,7 +181,11 @@ _start_warm:
li s7, FixedPcdGet32 (PcdBootableHartNumber)
bnez s7, 1f
la a4, platform
- REG_L s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
+#if __riscv_xlen == 64
+ lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
+#else
+ lw s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
+#endif
1:
li s8, FixedPcdGet32 (PcdOpenSbiStackSize)
la a4, platform
@@ -209,7 +227,8 @@ _start_warm:
csrr a0, CSR_MHARTID
j _uninitialized_hart_wait
4:
- li s7, FixedPcdGet32 (PcdHartCount)
+ la a5, _pysical_hart_count
+ ld s7, (a5)
/* Find the scratch space for this hart
*
* Scratch buffer is on the top of stack buffer
@@ -275,6 +294,8 @@ _start_warm:
.section .data, "aw"
_boot_hart_done:
RISCV_PTR 0
+_pysical_hart_count:
+ RISCV_PTR 0
.align 3
.section .entry, "ax", %progbits
@@ -293,7 +314,7 @@ _hartid_to_scratch:
/*
* s0 -> HART Stack Size
* s1 -> HART Stack End
- * s2 -> Temporary
+ * s2 -> Total hart count
*/
la s2, platform
#if __riscv_xlen == 64
@@ -301,8 +322,9 @@ _hartid_to_scratch:
#else
lw s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2)
#endif
- li s2, FixedPcdGet32 (PcdHartCount)
+ la s1, _pysical_hart_count /* total HART count */
+ ld s2, (s1)
mul s2, s2, s0
li s1, FixedPcdGet32 (PcdScratchRamBase)
add s1, s1, s2
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [edk2-platforms][PATCH 30/30] Silicon/RISC-V: Add PciCpuIoDxe driver
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (28 preceding siblings ...)
2021-10-19 8:10 ` [edk2-platforms][PATCH 29/30] RISC-V/PlatformPkg: Determine hart number from DTB Abner Chang
@ 2021-10-19 8:10 ` Abner Chang
2021-11-09 4:26 ` [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Daniel Schaefer
2021-11-09 10:06 ` Sunil V L
31 siblings, 0 replies; 33+ messages in thread
From: Abner Chang @ 2021-10-19 8:10 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Add PCI CpuIo protocol to RISC-V.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 1 +
.../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 47 ++
.../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 554 ++++++++++++++++++
3 files changed, 602 insertions(+)
create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c
diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
index 3b5738957d..5c7425421b 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc
@@ -105,3 +105,4 @@
Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe/CpuDxe.inf
Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf
+ Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf b/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
new file mode 100644
index 0000000000..736143bf4c
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
@@ -0,0 +1,47 @@
+## @file
+# Produces the CPU I/O 2 Protocol by using the services of the I/O Library.
+#
+# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+# (C) Copyright 2021 Hewlett Packard Enterprise Development LP<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PciCpuIo2Dxe
+ FILE_GUID = 4032D393-69E6-42BF-BBEA-08F3297374E8
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PciCpuIo2Initialize
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ PciCpuIo2Dxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseLib
+ DebugLib
+ IoLib
+ PcdLib
+ UefiBootServicesTableLib
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation
+
+[Protocols]
+ gEfiCpuIo2ProtocolGuid ## PRODUCES
+
+[Depex]
+ TRUE
diff --git a/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c b/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c
new file mode 100644
index 0000000000..03e3070682
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c
@@ -0,0 +1,554 @@
+/** @file
+ Produces the CPU I/O 2 Protocol.
+
+Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+(C) Copyright 2021 Hewlett Packard Enterprise Development LP<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiDxe.h>
+
+#include <Protocol/CpuIo2.h>
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#define MAX_IO_PORT_ADDRESS 0xFFFF
+
+//
+// Handle for the CPU I/O 2 Protocol
+//
+STATIC EFI_HANDLE mHandle = NULL;
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mInStride[] = {
+ 1, // EfiCpuIoWidthUint8
+ 2, // EfiCpuIoWidthUint16
+ 4, // EfiCpuIoWidthUint32
+ 8, // EfiCpuIoWidthUint64
+ 0, // EfiCpuIoWidthFifoUint8
+ 0, // EfiCpuIoWidthFifoUint16
+ 0, // EfiCpuIoWidthFifoUint32
+ 0, // EfiCpuIoWidthFifoUint64
+ 1, // EfiCpuIoWidthFillUint8
+ 2, // EfiCpuIoWidthFillUint16
+ 4, // EfiCpuIoWidthFillUint32
+ 8 // EfiCpuIoWidthFillUint64
+};
+
+//
+// Lookup table for increment values based on transfer widths
+//
+STATIC CONST UINT8 mOutStride[] = {
+ 1, // EfiCpuIoWidthUint8
+ 2, // EfiCpuIoWidthUint16
+ 4, // EfiCpuIoWidthUint32
+ 8, // EfiCpuIoWidthUint64
+ 1, // EfiCpuIoWidthFifoUint8
+ 2, // EfiCpuIoWidthFifoUint16
+ 4, // EfiCpuIoWidthFifoUint32
+ 8, // EfiCpuIoWidthFifoUint64
+ 0, // EfiCpuIoWidthFillUint8
+ 0, // EfiCpuIoWidthFillUint16
+ 0, // EfiCpuIoWidthFillUint32
+ 0 // EfiCpuIoWidthFillUint64
+};
+
+/**
+ Check parameters to a CPU I/O 2 Protocol service request.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The parameters for this request pass the checks.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+CpuIoCheckParameter (
+ IN BOOLEAN MmioOperation,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ UINT64 MaxCount;
+ UINT64 Limit;
+
+ //
+ // Check to see if Buffer is NULL
+ //
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check to see if Width is in the valid range
+ //
+ if ((UINT32)Width >= EfiCpuIoWidthMaximum) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // For FIFO type, the target address won't increase during the access,
+ // so treat Count as 1
+ //
+ if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
+ Count = 1;
+ }
+
+ //
+ // Check to see if Width is in the valid range for I/O Port operations
+ //
+ Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check to see if Address is aligned
+ //
+ if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // Check to see if any address associated with this transfer exceeds the maximum
+ // allowed address. The maximum address implied by the parameters passed in is
+ // Address + Size * Count. If the following condition is met, then the transfer
+ // is not supported.
+ //
+ // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1
+ //
+ // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count
+ // can also be the maximum integer value supported by the CPU, this range
+ // check must be adjusted to avoid all overflow conditions.
+ //
+ // The following form of the range check is equivalent but assumes that
+ // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).
+ //
+ Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);
+ if (Count == 0) {
+ if (Address > Limit) {
+ return EFI_UNSUPPORTED;
+ }
+ } else {
+ MaxCount = RShiftU64 (Limit, Width);
+ if (MaxCount < (Count - 1)) {
+ return EFI_UNSUPPORTED;
+ }
+ if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
+ return EFI_UNSUPPORTED;
+ }
+ }
+
+ //
+ // Check to see if Buffer is aligned
+ //
+ if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) {
+ return EFI_UNSUPPORTED;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Reads memory-mapped registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[out] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuMemoryServiceRead (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ *Uint8Buffer = MmioRead8 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint64) {
+ *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Writes memory-mapped registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuMemoryServiceWrite (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ MmioWrite8 ((UINTN)Address, *Uint8Buffer);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+ } else if (OperationWidth == EfiCpuIoWidthUint64) {
+ MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Reads I/O registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[out] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuIoServiceRead (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Address += PcdGet64 (PcdPciIoTranslation);
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+
+ for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ *Uint8Buffer = MmioRead8 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Write I/O registers.
+
+ The I/O operations are carried out exactly as requested. The caller is responsible
+ for satisfying any alignment and I/O width restrictions that a PI System on a
+ platform might require. For example on some platforms, width requests of
+ EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
+ be handled by the driver.
+
+ If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+ or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
+ each of the Count operations that is performed.
+
+ If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+ EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times on the same Address.
+
+ If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+ EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+ incremented for each of the Count operations that is performed. The read or
+ write operation is performed Count times from the first element of Buffer.
+
+ @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.
+ @param[in] Width Signifies the width of the I/O or Memory operation.
+ @param[in] Address The base address of the I/O operation.
+ @param[in] Count The number of I/O operations to perform. The number of
+ bytes moved is Width size * Count, starting at Address.
+ @param[in] Buffer For read operations, the destination buffer to store the results.
+ For write operations, the source buffer from which to write data.
+
+ @retval EFI_SUCCESS The data was read from or written to the PI system.
+ @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+ @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
+ @retval EFI_UNSUPPORTED The address range specified by Address, Width,
+ and Count is not valid for this PI system.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+CpuIoServiceWrite (
+ IN EFI_CPU_IO2_PROTOCOL *This,
+ IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINT8 InStride;
+ UINT8 OutStride;
+ EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
+ UINT8 *Uint8Buffer;
+
+ //
+ // Make sure the parameters are valid
+ //
+ Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Address += PcdGet64 (PcdPciIoTranslation);
+
+ //
+ // Select loop based on the width of the transfer
+ //
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+
+ for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
+ if (OperationWidth == EfiCpuIoWidthUint8) {
+ MmioWrite8 ((UINTN)Address, *Uint8Buffer);
+ } else if (OperationWidth == EfiCpuIoWidthUint16) {
+ MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
+ } else if (OperationWidth == EfiCpuIoWidthUint32) {
+ MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+//
+// CPU I/O 2 Protocol instance
+//
+STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
+ {
+ CpuMemoryServiceRead,
+ CpuMemoryServiceWrite
+ },
+ {
+ CpuIoServiceRead,
+ CpuIoServiceWrite
+ }
+};
+
+
+/**
+ The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+ @retval other Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+PciCpuIo2Initialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mHandle,
+ &gEfiCpuIo2ProtocolGuid, &mCpuIo2,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
--
2.31.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (29 preceding siblings ...)
2021-10-19 8:10 ` [edk2-platforms][PATCH 30/30] Silicon/RISC-V: Add PciCpuIoDxe driver Abner Chang
@ 2021-11-09 4:26 ` Daniel Schaefer
2021-11-09 10:06 ` Sunil V L
31 siblings, 0 replies; 33+ messages in thread
From: Daniel Schaefer @ 2021-11-09 4:26 UTC (permalink / raw)
To: Chang, Abner (HPS SW/FW Technologist), devel@edk2.groups.io; +Cc: Sunil V L
[-- Attachment #1: Type: text/plain, Size: 9926 bytes --]
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
________________________________
From: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
Sent: Tuesday, October 19, 2021 16:09
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>; Sunil V L <sunilvl@ventanamicro.com>; Schaefer, Daniel <daniel.schaefer@hpe.com>
Subject: [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9
This is the patch set to incorporate opensbi v0.9 with edk2
RISC-V port. There are many architecture changes to compliant
with the RISC-V SBI implementation (opensbi) and also provide the
flexibility to OEM platform.
Below is the summary of major changes. You can also refer to patch (1/31)
to understand the architecture design.
- Flexibly support privilege modes for edk2 execution phases using PCD.
- M-mode SEC then S-mode all the way to boot OS.
- M-mode SEC and PEI, then S-mode for DXE to boot OS.
- M-mode firmware all the way to S-mode OS.
Default is M-mode SEC then S-mode all the way to boot OS.
Still have to implemente priviledge mode switching for PEI to DXE and
BDSto Boot OS.
- Apply opensbi firmware domain solution to protect firmware regions using
FDF/PCD.
- Provide Platform SEC PPI library that can be executed in either M-mode or
S-mode PEI phases according to OEM platform definition.
- Determine boot hart using Device Tree or PCD. This allows OEM to
flexibly select the desired HARTs for booting system. Non-boot HARTs
can be used for other applications/purposes.
- Provide an edk2 library wrapper of opensbi platform functions. This
allows OEM to have procedures that hooks before or after the certain
opensbi platform functions.
- Other patches to adopt opensbi v0.9.
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Abner Chang (30):
RISC-V/PlatformPkg: Update document
RISC-V: Add RISC-V PeiCoreEntryPoint library
RISC-V: Create opensbi firmware domains
RISC-V: Use RISC-V PeiCoreEntryPoint library
Platform/RISC-V: Add library to get PPI descriptor
Platform/U540: Provide PlatormSecPpiLib
Platform/RISC-V: Use PlatformSecPpiLib
Platform/SiFive: CoreInfoHob uses RiscVFirmwareContextLib
SiFive/U5SeriesPkg: Add CLINT to Device Tree
Platform/RISC-V: Add NULL library instance of RiscVSpecialPlatformLib
SiFive/U540: RiscVSpecialPlatformLib instance of U540
Platform/RISC-V: Remove platform dependency from this library
Platform/RISC-V: Remove Null instance of OpensbilatformLibNull
RiscVPlatformPkg/Sec: Initial hart_index2Id array
RiscVPlatformPkg/OpensbiPlatformLib: Remove platform code
RiscVPlatformPkg/U540: Only use four harts on U540
U5SeriesPkg/PeiCoreInfoHob: Remove hart count check
RiscVPlatformPkg/RiscVSpecialPlatformLib: Rename module name
RiscVPlatformPkg/U540: Add SortLib
ProcessorPkg/opensbi: Update opensbi library
RiscVPlatformPkg/Sec: Check Cold/Warm hart
RiscVPlatformPkg/Sec: Add more comments to Secmain.c
RiscV/ProcessorPkg: Create read mtime CSR library instances
RiscV/ProcessorPkg: Use mtime CSR library
Silicon/SiFive: Use mtime CSR library
SiFive/SerialPortLib: Remove global variable
RISC-V/PlatformPkg: Updates for the latest OpenSBI
RiscVPlatformPkg/Sec: Separate EDK2 Opensbi platform hook.
RISC-V/PlatformPkg: Determine hart number from DTB
Silicon/RISC-V: Add PciCpuIoDxe driver
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 52 +-
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 1 +
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 20 +-
.../FreedomU500VC707Board/U500.dsc | 1 +
.../FreedomU540HiFiveUnleashedBoard/U540.dsc | 11 +-
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 3 +
.../U540.fdf.inc | 94 +-
.../VarStore.fdf.inc | 8 +-
.../Edk2OpensbiPlatformWrapperLib.inf | 44 +
.../OpensbiPlatformLib/OpensbiPlatformLib.inf | 11 +-
.../OpensbiPlatformLibNull.inf | 38 -
.../PeiCoreEntryPoint/PeiCoreEntryPoint.inf | 37 +
.../PlatformSecPpiLibNull.inf | 36 +
.../RiscVSpecialPlatformLibNull.inf | 36 +
.../PlatformPkg/Universal/Sec/SecMain.inf | 15 +-
.../RiscVSpecialPlatformLib.inf | 36 +
.../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 3 +-
.../PlatformSecPpiLib/PlatformSecPpiLib.inf | 43 +
.../Universal/Dxe/TimerDxe/TimerDxe.inf | 1 +
.../EmulatedMachineModeTimerLib.inf | 34 +
.../MachineModeTimerLib.inf | 38 +
.../RiscVTimerLib/BaseRiscVTimerLib.inf | 3 +-
.../ProcessorPkg/Universal/CpuDxe/CpuDxe.inf | 1 +
.../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 47 +
.../Library/Edk2OpensbiPlatformWrapperLib.h | 16 +
.../Include/Library/PlatformSecPpiLib.h | 24 +
.../Include/Library/RiscVSpecialPlatformLib.h | 20 +
.../OpensbiPlatformLib/PlatformOverride.h | 30 -
.../PlatformPkg/Universal/Sec/SecMain.h | 28 +-
.../SiFive/U5SeriesPkg/Include/SifiveU5Uart.h | 1 +
.../Include/IndustryStandard/RiscV.h | 5 +
.../Include/IndustryStandard/RiscVOpensbi.h | 8 +-
.../Include/Library/RiscVCpuLib.h | 3 +
.../Edk2OpensbiPlatformWrapperLib.c | 530 +++++
.../Library/OpensbiPlatformLib/Platform.c | 77 +-
.../Library/OpensbiPlatformLibNull/Platform.c | 51 -
.../PeiCoreEntryPoint/PeiCoreEntryPoint.c | 108 +
.../PlatformSecPpiLibNull/PlatformSecPpiLib.c | 28 +
.../RiscVSpecialPlatformLib.c | 20 +
.../PlatformPkg/Universal/Sec/SecMain.c | 268 +--
.../RiscVSpecialPlatformLib}/SifiveFu540.c | 11 +-
.../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 9 +-
.../PlatformSecPpiLib/PlatformSecPpiLib.c | 148 ++
.../Library/SerialIoLib/SerialPortLib.c | 58 +-
.../Universal/Dxe/TimerDxe/Timer.c | 14 +-
.../Library/RiscVTimerLib/RiscVTimerLib.c | 6 +-
.../ProcessorPkg/Universal/CpuDxe/CpuDxe.c | 2 +-
.../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 554 +++++
.../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 6 +-
Platform/RISC-V/PlatformPkg/Readme.md | 132 +-
.../Documents/Media/RiscVEdk2BootProcess.svg | 1928 +++++++++++++++++
.../Documents/Media/RiscVEdk2FwDomain.svg | 1290 +++++++++++
.../PeiCoreEntryPoint/PeiCoreEntryPoint.uni | 14 +
.../Universal/Sec/Riscv64/SecEntry.S | 372 ++--
.../DeviceTree/fu540-c000.dtsi | 591 ++---
.../Library/RiscVOpensbiLib/opensbi | 2 +-
.../EmulatedMachineModeTimerLib.S | 24 +
.../MachineModeTimerLib/MachineModeTimerLib.S | 25 +
58 files changed, 6105 insertions(+), 911 deletions(-)
create mode 100644 Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf
delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
create mode 100644 Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/Edk2OpensbiPlatformWrapperLib.h
create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/PlatformSecPpiLib.h
create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/RiscVSpecialPlatformLib.h
delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/PlatformOverride.h
create mode 100644 Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c
create mode 100644 Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
rename Platform/{RISC-V/PlatformPkg/Library/OpensbiPlatformLib => SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/RiscVSpecialPlatformLib}/SifiveFu540.c (76%)
create mode 100644 Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.c
create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c
create mode 100644 Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2BootProcess.svg
create mode 100644 Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2FwDomain.svg
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.uni
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S
create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S
--
2.31.1
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^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
` (30 preceding siblings ...)
2021-11-09 4:26 ` [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Daniel Schaefer
@ 2021-11-09 10:06 ` Sunil V L
31 siblings, 0 replies; 33+ messages in thread
From: Sunil V L @ 2021-11-09 10:06 UTC (permalink / raw)
To: Abner Chang; +Cc: devel, Daniel Schaefer
The patch set looks good to me.
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
On Tue, Oct 19, 2021 at 04:09:37PM +0800, Abner Chang wrote:
> This is the patch set to incorporate opensbi v0.9 with edk2
> RISC-V port. There are many architecture changes to compliant
> with the RISC-V SBI implementation (opensbi) and also provide the
> flexibility to OEM platform.
>
> Below is the summary of major changes. You can also refer to patch (1/31)
> to understand the architecture design.
>
> - Flexibly support privilege modes for edk2 execution phases using PCD.
> - M-mode SEC then S-mode all the way to boot OS.
> - M-mode SEC and PEI, then S-mode for DXE to boot OS.
> - M-mode firmware all the way to S-mode OS.
> Default is M-mode SEC then S-mode all the way to boot OS.
> Still have to implemente priviledge mode switching for PEI to DXE and
> BDSto Boot OS.
>
> - Apply opensbi firmware domain solution to protect firmware regions using
> FDF/PCD.
>
> - Provide Platform SEC PPI library that can be executed in either M-mode or
> S-mode PEI phases according to OEM platform definition.
>
> - Determine boot hart using Device Tree or PCD. This allows OEM to
> flexibly select the desired HARTs for booting system. Non-boot HARTs
> can be used for other applications/purposes.
>
> - Provide an edk2 library wrapper of opensbi platform functions. This
> allows OEM to have procedures that hooks before or after the certain
> opensbi platform functions.
>
> - Other patches to adopt opensbi v0.9.
>
> Cc: Sunil V L <sunilvl@ventanamicro.com>
> Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
>
> Abner Chang (30):
> RISC-V/PlatformPkg: Update document
> RISC-V: Add RISC-V PeiCoreEntryPoint library
> RISC-V: Create opensbi firmware domains
> RISC-V: Use RISC-V PeiCoreEntryPoint library
> Platform/RISC-V: Add library to get PPI descriptor
> Platform/U540: Provide PlatormSecPpiLib
> Platform/RISC-V: Use PlatformSecPpiLib
> Platform/SiFive: CoreInfoHob uses RiscVFirmwareContextLib
> SiFive/U5SeriesPkg: Add CLINT to Device Tree
> Platform/RISC-V: Add NULL library instance of RiscVSpecialPlatformLib
> SiFive/U540: RiscVSpecialPlatformLib instance of U540
> Platform/RISC-V: Remove platform dependency from this library
> Platform/RISC-V: Remove Null instance of OpensbilatformLibNull
> RiscVPlatformPkg/Sec: Initial hart_index2Id array
> RiscVPlatformPkg/OpensbiPlatformLib: Remove platform code
> RiscVPlatformPkg/U540: Only use four harts on U540
> U5SeriesPkg/PeiCoreInfoHob: Remove hart count check
> RiscVPlatformPkg/RiscVSpecialPlatformLib: Rename module name
> RiscVPlatformPkg/U540: Add SortLib
> ProcessorPkg/opensbi: Update opensbi library
> RiscVPlatformPkg/Sec: Check Cold/Warm hart
> RiscVPlatformPkg/Sec: Add more comments to Secmain.c
> RiscV/ProcessorPkg: Create read mtime CSR library instances
> RiscV/ProcessorPkg: Use mtime CSR library
> Silicon/SiFive: Use mtime CSR library
> SiFive/SerialPortLib: Remove global variable
> RISC-V/PlatformPkg: Updates for the latest OpenSBI
> RiscVPlatformPkg/Sec: Separate EDK2 Opensbi platform hook.
> RISC-V/PlatformPkg: Determine hart number from DTB
> Silicon/RISC-V: Add PciCpuIoDxe driver
>
> .../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 52 +-
> .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 1 +
> .../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 20 +-
> .../FreedomU500VC707Board/U500.dsc | 1 +
> .../FreedomU540HiFiveUnleashedBoard/U540.dsc | 11 +-
> .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 3 +
> .../U540.fdf.inc | 94 +-
> .../VarStore.fdf.inc | 8 +-
> .../Edk2OpensbiPlatformWrapperLib.inf | 44 +
> .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 11 +-
> .../OpensbiPlatformLibNull.inf | 38 -
> .../PeiCoreEntryPoint/PeiCoreEntryPoint.inf | 37 +
> .../PlatformSecPpiLibNull.inf | 36 +
> .../RiscVSpecialPlatformLibNull.inf | 36 +
> .../PlatformPkg/Universal/Sec/SecMain.inf | 15 +-
> .../RiscVSpecialPlatformLib.inf | 36 +
> .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 3 +-
> .../PlatformSecPpiLib/PlatformSecPpiLib.inf | 43 +
> .../Universal/Dxe/TimerDxe/TimerDxe.inf | 1 +
> .../EmulatedMachineModeTimerLib.inf | 34 +
> .../MachineModeTimerLib.inf | 38 +
> .../RiscVTimerLib/BaseRiscVTimerLib.inf | 3 +-
> .../ProcessorPkg/Universal/CpuDxe/CpuDxe.inf | 1 +
> .../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 47 +
> .../Library/Edk2OpensbiPlatformWrapperLib.h | 16 +
> .../Include/Library/PlatformSecPpiLib.h | 24 +
> .../Include/Library/RiscVSpecialPlatformLib.h | 20 +
> .../OpensbiPlatformLib/PlatformOverride.h | 30 -
> .../PlatformPkg/Universal/Sec/SecMain.h | 28 +-
> .../SiFive/U5SeriesPkg/Include/SifiveU5Uart.h | 1 +
> .../Include/IndustryStandard/RiscV.h | 5 +
> .../Include/IndustryStandard/RiscVOpensbi.h | 8 +-
> .../Include/Library/RiscVCpuLib.h | 3 +
> .../Edk2OpensbiPlatformWrapperLib.c | 530 +++++
> .../Library/OpensbiPlatformLib/Platform.c | 77 +-
> .../Library/OpensbiPlatformLibNull/Platform.c | 51 -
> .../PeiCoreEntryPoint/PeiCoreEntryPoint.c | 108 +
> .../PlatformSecPpiLibNull/PlatformSecPpiLib.c | 28 +
> .../RiscVSpecialPlatformLib.c | 20 +
> .../PlatformPkg/Universal/Sec/SecMain.c | 268 +--
> .../RiscVSpecialPlatformLib}/SifiveFu540.c | 11 +-
> .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 9 +-
> .../PlatformSecPpiLib/PlatformSecPpiLib.c | 148 ++
> .../Library/SerialIoLib/SerialPortLib.c | 58 +-
> .../Universal/Dxe/TimerDxe/Timer.c | 14 +-
> .../Library/RiscVTimerLib/RiscVTimerLib.c | 6 +-
> .../ProcessorPkg/Universal/CpuDxe/CpuDxe.c | 2 +-
> .../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 554 +++++
> .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 6 +-
> Platform/RISC-V/PlatformPkg/Readme.md | 132 +-
> .../Documents/Media/RiscVEdk2BootProcess.svg | 1928 +++++++++++++++++
> .../Documents/Media/RiscVEdk2FwDomain.svg | 1290 +++++++++++
> .../PeiCoreEntryPoint/PeiCoreEntryPoint.uni | 14 +
> .../Universal/Sec/Riscv64/SecEntry.S | 372 ++--
> .../DeviceTree/fu540-c000.dtsi | 591 ++---
> .../Library/RiscVOpensbiLib/opensbi | 2 +-
> .../EmulatedMachineModeTimerLib.S | 24 +
> .../MachineModeTimerLib/MachineModeTimerLib.S | 25 +
> 58 files changed, 6105 insertions(+), 911 deletions(-)
> create mode 100644 Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf
> delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
> create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
> create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf
> create mode 100644 Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf
> create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
> create mode 100644 Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.inf
> create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
> create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf
> create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf
> create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/Edk2OpensbiPlatformWrapperLib.h
> create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/PlatformSecPpiLib.h
> create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/RiscVSpecialPlatformLib.h
> delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/PlatformOverride.h
> create mode 100644 Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c
> delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c
> create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c
> create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c
> create mode 100644 Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
> rename Platform/{RISC-V/PlatformPkg/Library/OpensbiPlatformLib => SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/RiscVSpecialPlatformLib}/SifiveFu540.c (76%)
> create mode 100644 Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.c
> create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c
> create mode 100644 Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2BootProcess.svg
> create mode 100644 Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2FwDomain.svg
> create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.uni
> create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S
> create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S
>
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 33+ messages in thread
