From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web09.7330.1634634498108700986 for ; Tue, 19 Oct 2021 02:08:24 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=kjMAlqsf; spf=temperror, err=temporary DNS error (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=0926d272d9=abner.chang@hpe.com) Received: from pps.filterd (m0150242.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J8CF9P020959; Tue, 19 Oct 2021 09:08:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=SX1r7yhUbt58o5tF2CRjy85apWfo3sXeFykrnOIv/2o=; b=kjMAlqsfoLPOj7HRQCAOX6rkc4fjw3Xhd7/t6beouK1fzIW+TOkoNdHBD94Lth8WFJN2 VFk+s2aJ58m36ApSRcoosUW/1XFkw3bh/Vc+PZRVxK7Pc+uKGHdl/q6l5ChmMBkrhhzq mwUgf9CEZC5QxA2WsjNaPSHygHSc895bpcdJgnnFbd0qkczYmeAqpOvLUiCwLZ914goU C6/OJgQowEOLXMZczRDblVo3sOxpatMjBWOU9J9vUGAZ5qTjT3+ILZAviC3ZAXX+DbZp 8WIoE3btn8ARRz1WSIP/FrAgi6fiF522aaXuRkDqQv2DgRWbhOcpwlsQ746Ldj9amkkw Nw== Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0a-002e3701.pphosted.com with ESMTP id 3bsta50efd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:16 +0000 Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id 0A51DC3; Tue, 19 Oct 2021 09:08:15 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id EFAAB48; Tue, 19 Oct 2021 09:08:13 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Sunil V L , Daniel Schaefer Subject: [edk2-platforms][PATCH 02/30] RISC-V: Add RISC-V PeiCoreEntryPoint library Date: Tue, 19 Oct 2021 16:09:39 +0800 Message-Id: <20211019081007.31165-3-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: 5vmMlaQB4py_A_1EWbkQcR6rlu4DS61X X-Proofpoint-ORIG-GUID: 5vmMlaQB4py_A_1EWbkQcR6rlu4DS61X X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-18_07,2021-10-18_01,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 priorityscore=1501 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 suspectscore=0 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109230001 definitions=main-2110190056 Content-Transfer-Encoding: quoted-printable - Add RISC-V PeiCoreEntryPoint library that incorporates with opensbi next phase switching mechanism. - Use RiscVFirmwareContext library to get the pointer of opensbi FirmwareContext. Cc: Sunil V L Cc: Daniel Schaefer Signed-off-by: Abner Chang --- .../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 7 +- .../PeiCoreEntryPoint/PeiCoreEntryPoint.inf | 36 +++++++ .../PeiCoreEntryPoint/PeiCoreEntryPoint.c | 97 +++++++++++++++++++ .../PeiCoreEntryPoint/PeiCoreEntryPoint.uni | 14 +++ 4 files changed, 153 insertions(+), 1 deletion(-) create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/P= eiCoreEntryPoint.inf create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/P= eiCoreEntryPoint.c create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/P= eiCoreEntryPoint.uni diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RI= SC-V/PlatformPkg/RiscVPlatformPkg.dsc index 5d9674a965..8eec09549f 100644 --- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc +++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc @@ -1,7 +1,7 @@ #/** @file=0D # RISC-V platform package.=0D #=0D -# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -58,6 +58,10 @@ TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplat= e.inf=0D PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf=0D =0D +[LibraryClasses.common.PEI_CORE]=0D + # RISC-V platform PEI core entry point.=0D + PeiCoreEntryPoint|Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/= PeiCoreEntryPoint.inf=0D +=0D [LibraryClasses.common.PEIM]=0D FirmwareContextProcessorSpecificLib|Platform/RISC-V/PlatformPkg/Library/= FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf= =0D HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D @@ -77,6 +81,7 @@ Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/Platfo= rmUpdateProgressLibNull.inf=0D Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/= FirmwareContextProcessorSpecificLib.inf=0D Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/R= iscVPlatformTempMemoryInitLibNull.inf=0D + Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.= inf=0D =0D [Components.common.SEC]=0D Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf=0D diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreE= ntryPoint.inf b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCo= reEntryPoint.inf new file mode 100644 index 0000000000..e16a974636 --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoi= nt.inf @@ -0,0 +1,36 @@ +## @file=0D +# Module entry point library for PEI core on RISC-V with RISC-V OpenSBI.=0D +#=0D +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D PeiCoreEntryPoint=0D + MODULE_UNI_FILE =3D PeiCoreEntryPoint.uni=0D + FILE_GUID =3D 2EBF4D2C-99B2-4A09-8C5C-318FB0EF7250= =0D + MODULE_TYPE =3D PEI_CORE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D PeiCoreEntryPoint|PEI_CORE=0D +=0D +#=0D +# VALID_ARCHITECTURES =3D RISCV64=0D +#=0D +=0D +[Sources]=0D + PeiCoreEntryPoint.c=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec=0D + Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + DebugLib=0D + RiscVFirmwareContextLib=0D +=0D diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreE= ntryPoint.c b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCore= EntryPoint.c new file mode 100644 index 0000000000..2fd0f2315b --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoi= nt.c @@ -0,0 +1,97 @@ +/** @file=0D + Entry point to a the PEI Core on RISC-V platform with RISC-V OpenSBI.=0D +=0D +Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
=0D +Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights = reserved.
=0D +=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +=0D +#include =0D +#include =0D +//=0D +// The Library classes this module produced=0D +//=0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + The entry point of PE/COFF Image for the PEI Core.=0D +=0D + This function is the entry point for the PEI Foundation, which allows th= e SEC phase=0D + to pass information about the stack, temporary RAM and the Boot Firmware= Volume.=0D + In addition, it also allows the SEC phase to pass services and data forw= ard for use=0D + during the PEI phase in the form of one or more PPIs.=0D + There is no limit to the number of additional PPIs that can be passed fr= om SEC into=0D + the PEI Foundation. As part of its initialization phase, the PEI Foundat= ion will add=0D + these SEC-hosted PPIs to its PPI database such that both the PEI Foundat= ion and any=0D + modules can leverage the associated service calls and/or code in these e= arly PPIs.=0D + This function is required to call ProcessModuleEntryPointList() with the= Context=0D + parameter set to NULL. ProcessModuleEntryPoint() is never expected to r= eturn.=0D + The PEI Core is responsible for calling ProcessLibraryConstructorList() = as soon as=0D + the PEI Services Table and the file handle for the PEI Core itself have = been established.=0D + If ProcessModuleEntryPointList() returns, then ASSERT() and halt the sys= tem.=0D +=0D + @param SecCoreData This is actually the RISC-V boot HART ID passed in a= 0 register.=0D +=0D + @param PpiList This is actually the EFI_RISCV_OPENSBI_FIRMWARE_CONT= EXT passed=0D + in a1 register.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +_ModuleEntryPoint(=0D + IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,=0D + IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList=0D +)=0D +{=0D + EFI_SEC_PEI_HAND_OFF *ThisSecCoreData;=0D + EFI_PEI_PPI_DESCRIPTOR *ThisPpiList;=0D + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;=0D +=0D + FirmwareContext =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)PpiList;=0D + SetFirmwareContextPointer (FirmwareContext);=0D + ThisSecCoreData =3D (EFI_SEC_PEI_HAND_OFF *)FirmwareContext->SecPeiHandO= ffData;=0D + ThisPpiList =3D (EFI_PEI_PPI_DESCRIPTOR *)FirmwareContext->SecPeiHandoff= Ppi;=0D + ProcessModuleEntryPointList (ThisSecCoreData, ThisPpiList, NULL);=0D +=0D + //=0D + // Should never return=0D + //=0D + ASSERT(FALSE);=0D + CpuDeadLoop ();=0D +}=0D +=0D +=0D +/**=0D + Required by the EBC compiler and identical in functionality to _ModuleEn= tryPoint().=0D +=0D + This function is required to call _ModuleEntryPoint() passing in SecCore= Data and PpiList.=0D +=0D + @param SecCoreData Points to a data structure containing information ab= out the PEI core's=0D + operating environment, such as the size and location= of temporary RAM,=0D + the stack location and the BFV location.=0D +=0D + @param PpiList Points to a list of one or more PPI descriptors to b= e installed=0D + initially by the PEI core. An empty PPI list consis= ts of=0D + a single descriptor with the end-tag=0D + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST.=0D + As part of its initialization phase, the PEI Foundat= ion will=0D + add these SEC-hosted PPIs to its PPI database, such = that both=0D + the PEI Foundationand any modules can leverage the a= ssociated=0D + service calls and/or code in these early PPIs.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +EfiMain (=0D + IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,=0D + IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList=0D + )=0D +{=0D + _ModuleEntryPoint (SecCoreData, PpiList);=0D +}=0D diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreE= ntryPoint.uni b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCo= reEntryPoint.uni new file mode 100644 index 0000000000..1955b7a05b --- /dev/null +++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoi= nt.uni @@ -0,0 +1,14 @@ +// /** @file=0D +// Module entry point library for PEI core on RISC-V with RISC-V OpenSBI.= =0D +//=0D +// Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +//=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D +//=0D +// **/=0D +=0D +=0D +#string STR_MODULE_ABSTRACT #language en-US "RISC-V module ent= ry point library for PEI core"=0D +=0D +#string STR_MODULE_DESCRIPTION #language en-US "RISC-V module ent= ry point library for PEI core."=0D +=0D --=20 2.31.1