From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web10.7408.1634634534030076795 for ; Tue, 19 Oct 2021 02:08:57 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=V/7ON6SW; spf=temperror, err=temporary DNS error (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=0926d272d9=abner.chang@hpe.com) Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19J8W5Mc018505; Tue, 19 Oct 2021 09:08:53 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=dOauE1xMOs+DcuqazkCwiehq2FXbPe3aAH8RQ5erEVE=; b=V/7ON6SWM/IskIOkQIHz/jxw5GpUxWulCONI7+82xW3zvEedLCOypd+DiTLoVYdTbhh0 oCv9ITrmiDqEoe2CHdjRZjYS4SeLd95YRUfVhiQFg/CHyp1RXUz4lzhwTAAf7OmYYRcK jZPXQc/yCuQgk62/iWwSOVleykS8rAoroLlXNgnt5Y08Aik5BmHRhJAUzniN/bOso/SD IMcl1Dk/bqCofYbinKINjywlbIEDq0pfN0jiRXWdsA20JmiAZv9hlMHBt40kGeXyOylu 2wuJvcDfWvo5EAC+H7VGn/Zj9WTEWd3qrBqCEhtSC8hGNcuQO9636/Oo5KAvX4oe4nyD 2Q== Received: from g9t5008.houston.hpe.com (g9t5008.houston.hpe.com [15.241.48.72]) by mx0b-002e3701.pphosted.com with ESMTP id 3bseymmq25-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Oct 2021 09:08:53 +0000 Received: from g9t2301.houston.hpecorp.net (g9t2301.houston.hpecorp.net [16.220.97.129]) by g9t5008.houston.hpe.com (Postfix) with ESMTP id D2EE556; Tue, 19 Oct 2021 09:08:52 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g9t2301.houston.hpecorp.net (Postfix) with ESMTP id C559C48; Tue, 19 Oct 2021 09:08:51 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Sunil V L Subject: [edk2-platforms][PATCH 29/30] RISC-V/PlatformPkg: Determine hart number from DTB Date: Tue, 19 Oct 2021 16:10:06 +0800 Message-Id: <20211019081007.31165-30-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: ClexM_tOKfYQas_dDt_1KaiPwsL2N8ec X-Proofpoint-GUID: ClexM_tOKfYQas_dDt_1KaiPwsL2N8ec X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-18_07,2021-10-18_01,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 mlxscore=0 suspectscore=0 impostorscore=0 mlxlogscore=999 phishscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109230001 definitions=main-2110190056 Content-Transfer-Encoding: quoted-printable Determine total number of hart from DTB instead of using PCD. Signed-off-by: Abner Chang Cc: Daniel Schaefer Cc: Sunil V L --- .../U540.fdf.inc | 1 - .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 3 - .../PlatformPkg/Universal/Sec/SecMain.inf | 1 - .../PlatformPkg/Universal/Sec/SecMain.c | 12 ++-- .../Universal/Sec/Riscv64/SecEntry.S | 60 +++++++++++++------ 5 files changed, 49 insertions(+), 28 deletions(-) diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U5= 40.fdf.inc index 1a525dc874..404c0b71ca 100644 --- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.= inc +++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.fdf.= inc @@ -90,7 +90,6 @@ SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSi= ze =3D 0x10000 =0D SET gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz =3D= 1000000=0D SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock =3D= 1000000000 # 1GHz system clock=0D -SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount =3D= 5 # Total cores on U540 platform=0D SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId =3D= 1 # Boot hart ID=0D =0D #=0D diff --git a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Opensbi= PlatformLib.inf b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/Op= ensbiPlatformLib.inf index 2e1227733a..6661ee8204 100644 --- a/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatfor= mLib.inf +++ b/Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatfor= mLib.inf @@ -46,9 +46,6 @@ RiscVSpecialPlatformLib=0D =0D [FixedPcd]=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize=0D =0D =0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf b/Platfo= rm/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf index ceb6d25222..b949b6c470 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf @@ -61,7 +61,6 @@ =0D [Pcd]=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId=0D - gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize=0D gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform= /RISC-V/PlatformPkg/Universal/Sec/SecMain.c index f2b2c7b583..17f33a02cc 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c @@ -530,7 +530,7 @@ GetDeviceTreeAddress ( EFI_COMMON_SECTION_HEADER *FoundSection;=0D =0D if (FixedPcdGet32 (PcdDeviceTreeAddress)) {=0D - DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddr= ess 0x%x.\n", FixedPcdGet32 (PcdDeviceTreeAddress)));=0D + DEBUG ((DEBUG_INFO, "Use fixed address of DBT from PcdDeviceTreeAddr= ess 0x%x 0x%x.\n", FixedPcdGet32 (PcdDeviceTreeAddress), *((unsigned long *= )FixedPcdGet32 (PcdDeviceTreeAddress))));=0D //=0D // Device tree address is pointed by PcdDeviceTreeAddress.=0D //=0D @@ -647,11 +647,10 @@ VOID EFIAPI SecCoreStartUpWithStack( //=0D ThisSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(Scratch);=0D ThisSbiPlatform->platform_ops_addr =3D (unsigned long)&Edk2OpensbiPlatfo= rmOps;=0D + Scratch->next_arg1 =3D (unsigned long)GetDeviceTreeAddress ();=0D if (HartId =3D=3D FixedPcdGet32(PcdBootHartId)) {=0D -=0D - Scratch->next_arg1 =3D (unsigned long)GetDeviceTreeAddress ();=0D if (Scratch->next_arg1 =3D=3D (unsigned long)NULL) {=0D - DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n"));=0D + DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found on boot hart= \n"));=0D ASSERT (FALSE);=0D }=0D DEBUG ((DEBUG_INFO, "Device Tree at 0x%x\n", Scratch->next_arg1));=0D @@ -685,6 +684,11 @@ VOID EFIAPI SecCoreStartUpWithStack( NonBootHartMessageLockValue =3D atomic_xchg(&NonBootHartMessageLock, T= RUE);=0D };=0D DEBUG((DEBUG_INFO, "%a: Non boot hart %d initialization.\n", __FUNCTION_= _, HartId));=0D + if (Scratch->next_arg1 =3D=3D (unsigned long)NULL) {=0D + DEBUG ((DEBUG_ERROR, "Platform Device Tree is not found\n"));=0D + ASSERT (FALSE);=0D + }=0D + DEBUG((DEBUG_INFO, "%a: Non boot hart %d DTB is at 0x%x.\n", __FUNCTION_= _, HartId, Scratch->next_arg1));=0D NonBootHartMessageLockValue =3D atomic_xchg(&NonBootHartMessageLock, FAL= SE);=0D //=0D // Non boot hart wiil be halted waiting for SBI_HART_STARTING.=0D diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S b= /Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S index 96087738a3..0fc7817665 100644 --- a/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S +++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S @@ -37,14 +37,39 @@ ASM_FUNC (_ModuleEntryPoint) li a5, FixedPcdGet32 (PcdBootHartId)=0D bne a6, a5, _wait_for_boot_hart=0D =0D - li ra, 0=0D - call _reset_regs=0D + /*=0D + * Initial the hart count reported in DTB=0D + */=0D + li a4, FixedPcdGet32 (PcdTemporaryRamBase)=0D + li a5, FixedPcdGet32 (PcdTemporaryRamSize)=0D =0D + /* Use Temp memory as the stack for calling to C code */=0D + add sp, a4, a5=0D + /* Get the address of device tree and call generic fw_platform_init */=0D + call GetDeviceTreeAddress /* a0 return the device tree address */=0D + beqz a0, skip_fw_init=0D + add a1, a0, 0 /* a1 is device tree */=0D + csrr a0, CSR_MHARTID /* a0 is boot hart ID */=0D + call fw_platform_init=0D +skip_fw_init:=0D /* Preload HART details=0D - * s7 -> HART Count=0D + * s7 -> Total HART count from PCD or DTB=0D * s8 -> HART Stack Size=0D */=0D - li s7, FixedPcdGet32 (PcdHartCount)=0D + la a0, platform=0D +#if __riscv_xlen =3D=3D 64=0D + lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a0)=0D +#else=0D + lw s7, SBI_PLATFORM_HART_COUNT_OFFSET(a0)=0D +#endif=0D + /*=0D + * This is the number of HARTs described in=0D + * DTB for this processor. We allocate the=0D + * scratch buffer according to this number.=0D + */=0D + la a4, _pysical_hart_count=0D + sd s7, (a4)=0D +=0D li s8, FixedPcdGet32 (PcdOpenSbiStackSize)=0D =0D /*=0D @@ -113,20 +138,9 @@ _scratch_init: =0D li a4, FixedPcdGet32 (PcdTemporaryRamBase)=0D li a5, FixedPcdGet32 (PcdTemporaryRamSize)=0D -=0D /* Use Temp memory as the stack for calling to C code */=0D add sp, a4, a5=0D - /* Get the address of device tree and call generic fw_platform_init */=0D - call GetDeviceTreeAddress /* a0 return the device tree address */=0D - beqz a0, skip_fw_init=0D - add a1, a0, 0 /* a1 is device tree */=0D - csrr a0, CSR_MHARTID /* a0 is hart ID */=0D - call fw_platform_init=0D -skip_fw_init:=0D -=0D /* Zero out temporary memory */=0D - li a4, FixedPcdGet32 (PcdTemporaryRamBase)=0D - li a5, FixedPcdGet32 (PcdTemporaryRamSize)=0D add a5, a4, a5=0D 1:=0D li a3, 0x0=0D @@ -167,7 +181,11 @@ _start_warm: li s7, FixedPcdGet32 (PcdBootableHartNumber)=0D bnez s7, 1f=0D la a4, platform=0D - REG_L s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)=0D +#if __riscv_xlen =3D=3D 64=0D + lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)=0D +#else=0D + lw s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)=0D +#endif=0D 1:=0D li s8, FixedPcdGet32 (PcdOpenSbiStackSize)=0D la a4, platform=0D @@ -209,7 +227,8 @@ _start_warm: csrr a0, CSR_MHARTID=0D j _uninitialized_hart_wait=0D 4:=0D - li s7, FixedPcdGet32 (PcdHartCount)=0D + la a5, _pysical_hart_count=0D + ld s7, (a5)=0D /* Find the scratch space for this hart=0D *=0D * Scratch buffer is on the top of stack buffer=0D @@ -275,6 +294,8 @@ _start_warm: .section .data, "aw"=0D _boot_hart_done:=0D RISCV_PTR 0=0D +_pysical_hart_count:=0D + RISCV_PTR 0=0D =0D .align 3=0D .section .entry, "ax", %progbits=0D @@ -293,7 +314,7 @@ _hartid_to_scratch: /*=0D * s0 -> HART Stack Size=0D * s1 -> HART Stack End=0D - * s2 -> Temporary=0D + * s2 -> Total hart count=0D */=0D la s2, platform=0D #if __riscv_xlen =3D=3D 64=0D @@ -301,8 +322,9 @@ _hartid_to_scratch: #else=0D lw s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2)=0D #endif=0D - li s2, FixedPcdGet32 (PcdHartCount)=0D =0D + la s1, _pysical_hart_count /* total HART count */=0D + ld s2, (s1)=0D mul s2, s2, s0=0D li s1, FixedPcdGet32 (PcdScratchRamBase)=0D add s1, s1, s2=0D --=20 2.31.1