From: "Abner Chang" <abner.chang@hpe.com>
To: devel@edk2.groups.io
Cc: abner.chang@hpe.com, Sunil V L <sunilvl@ventanamicro.com>,
Daniel Schaefer <daniel.schaefer@hpe.com>
Subject: [edk2-platforms][PATCH 06/30] Platform/U540: Provide PlatormSecPpiLib
Date: Tue, 19 Oct 2021 16:09:43 +0800 [thread overview]
Message-ID: <20211019081007.31165-7-abner.chang@hpe.com> (raw)
In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com>
Provide PlatormSecPpiLib instance for U540
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../FreedomU540HiFiveUnleashedBoard/U540.dsc | 1 +
.../PlatformSecPpiLib/PlatformSecPpiLib.inf | 43 +++++
.../PlatformSecPpiLib/PlatformSecPpiLib.c | 148 ++++++++++++++++++
3 files changed, 192 insertions(+)
create mode 100644 Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.inf
create mode 100644 Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.c
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
index be23fc39fd..d12af19825 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/U540.dsc
@@ -192,6 +192,7 @@
PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
# RISC-V platform PEI core entry point.
PeiCoreEntryPoint|Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ PlatformSecPpiLib|Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.inf
[LibraryClasses.common.PEIM]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
diff --git a/Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.inf b/Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.inf
new file mode 100644
index 0000000000..7e9e1a5e20
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.inf
@@ -0,0 +1,43 @@
+## @file
+# Library instance to to provide PPI before PEI Core
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PlatformSecPpiLib
+ FILE_GUID = 8F8E049E-F193-427C-998E-1E8FE2612D94
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformSecPpiLib|PEI_CORE
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ PlatformSecPpiLib.c
+
+[Ppis]
+[Ppis]
+ gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED
+ gEfiTemporaryRamDonePpiGuid # PPI ALWAYS_PRODUCED
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ MemoryAllocationLib
+ PrintLib
+ RiscVFirmwareContextLib
diff --git a/Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.c b/Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.c
new file mode 100644
index 0000000000..ef84e8c1bc
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.c
@@ -0,0 +1,148 @@
+/**@file
+ Library to install platform PPI before PEI Core
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+#include <IndustryStandard/RiscVOpensbi.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <Library/PlatformSecPpiLib.h>
+#include <Library/PrintLib.h>
+#include <Library/RiscVFirmwareContextLib.h>
+
+#include <Ppi/TemporaryRamDone.h>
+#include <Ppi/TemporaryRamSupport.h>
+
+EFI_STATUS
+EFIAPI
+TemporaryRamMigration (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
+ IN UINTN CopySize
+ );
+
+EFI_STATUS
+EFIAPI
+TemporaryRamDone (
+ VOID
+ );
+
+STATIC EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = {
+ TemporaryRamMigration
+};
+
+STATIC EFI_PEI_TEMPORARY_RAM_DONE_PPI mTemporaryRamDonePpi = {
+ TemporaryRamDone
+};
+
+STATIC EFI_PEI_PPI_DESCRIPTOR mPrivateDispatchTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gEfiTemporaryRamSupportPpiGuid,
+ &mTemporaryRamSupportPpi
+ },
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiTemporaryRamDonePpiGuid,
+ &mTemporaryRamDonePpi
+ },
+};
+
+/** Temporary RAM migration function.
+
+ This function migrates the data from temporary RAM to permanent
+ memory.
+
+ @param[in] PeiServices PEI service
+ @param[in] TemporaryMemoryBase Temporary memory base address
+ @param[in] PermanentMemoryBase Permanent memory base address
+ @param[in] CopySize Size to copy
+
+**/
+EFI_STATUS
+EFIAPI
+TemporaryRamMigration (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
+ IN UINTN CopySize
+ )
+{
+ VOID *OldHeap;
+ VOID *NewHeap;
+ VOID *OldStack;
+ VOID *NewStack;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+
+ DEBUG ((DEBUG_INFO,
+ "%a: Temp Mem Base:0x%Lx, Permanent Mem Base:0x%Lx, CopySize:0x%Lx\n",
+ __FUNCTION__,
+ TemporaryMemoryBase,
+ PermanentMemoryBase,
+ (UINT64)CopySize
+ ));
+
+ OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;
+ NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize >> 1));
+
+ OldStack = (VOID*)((UINTN)TemporaryMemoryBase + (CopySize >> 1));
+ NewStack = (VOID*)(UINTN)PermanentMemoryBase;
+
+ CopyMem (NewHeap, OldHeap, CopySize >> 1); // Migrate Heap
+ CopyMem (NewStack, OldStack, CopySize >> 1); // Migrate Stack
+
+ //
+ // Reset firmware context pointer
+ //
+ GetFirmwareContextPointer (&FirmwareContext);
+ FirmwareContext = (VOID *)FirmwareContext + (unsigned long)((UINTN)NewStack - (UINTN)OldStack);
+ SetFirmwareContextPointer (FirmwareContext);
+
+ //
+ // Relocate PEI Service **
+ //
+ FirmwareContext->PeiServiceTable += (unsigned long)((UINTN)NewStack - (UINTN)OldStack);
+ DEBUG ((DEBUG_INFO, "%a: OpenSBI Firmware Context is relocated to 0x%x\n", __FUNCTION__, FirmwareContext));
+ DEBUG ((DEBUG_INFO, "OpenSBI Firmware Context at 0x%x\n", FirmwareContext));
+ DEBUG ((DEBUG_INFO, " PEI Service at 0x%x\n\n", FirmwareContext->PeiServiceTable));
+
+ register uintptr_t a0 asm ("a0") = (uintptr_t)((UINTN)NewStack - (UINTN)OldStack);
+ asm volatile ("add sp, sp, a0"::"r"(a0):);
+ return EFI_SUCCESS;
+}
+
+/** Temprary RAM done function.
+
+**/
+EFI_STATUS EFIAPI TemporaryRamDone (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "%a: 2nd time PEI core, temporary ram done.\n", __FUNCTION__));
+ return EFI_SUCCESS;
+}
+/** Return platform SEC PPI before PEI Core
+
+ @param[in,out] ThisPpiList Pointer to retrieve EFI_PEI_PPI_DESCRIPTOR.
+
+**/
+EFI_STATUS
+GetPlatformPrePeiCorePpiDescriptor (
+ IN OUT EFI_PEI_PPI_DESCRIPTOR **ThisPpiList
+)
+{
+ *ThisPpiList = mPrivateDispatchTable;
+ return EFI_SUCCESS;
+}
+
--
2.31.1
next prev parent reply other threads:[~2021-10-19 9:08 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-19 8:09 [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 01/30] RISC-V/PlatformPkg: Update document Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 02/30] RISC-V: Add RISC-V PeiCoreEntryPoint library Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 03/30] RISC-V: Create opensbi firmware domains Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 04/30] RISC-V: Use RISC-V PeiCoreEntryPoint library Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 05/30] Platform/RISC-V: Add library to get PPI descriptor Abner Chang
2021-10-19 8:09 ` Abner Chang [this message]
2021-10-19 8:09 ` [edk2-platforms][PATCH 07/30] Platform/RISC-V: Use PlatformSecPpiLib Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 08/30] Platform/SiFive: CoreInfoHob uses RiscVFirmwareContextLib Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 09/30] SiFive/U5SeriesPkg: Add CLINT to Device Tree Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 10/30] Platform/RISC-V: Add NULL library instance of RiscVSpecialPlatformLib Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 11/30] SiFive/U540: RiscVSpecialPlatformLib instance of U540 Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 12/30] Platform/RISC-V: Remove platform dependency from this library Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 13/30] Platform/RISC-V: Remove Null instance of OpensbilatformLibNull Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 14/30] RiscVPlatformPkg/Sec: Initial hart_index2Id array Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 15/30] RiscVPlatformPkg/OpensbiPlatformLib: Remove platform code Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 16/30] RiscVPlatformPkg/U540: Only use four harts on U540 Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 17/30] U5SeriesPkg/PeiCoreInfoHob: Remove hart count check Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 18/30] RiscVPlatformPkg/RiscVSpecialPlatformLib: Rename module name Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 19/30] RiscVPlatformPkg/U540: Add SortLib Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 20/30] ProcessorPkg/opensbi: Update opensbi library Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 21/30] RiscVPlatformPkg/Sec: Check Cold/Warm hart Abner Chang
2021-10-19 8:09 ` [edk2-platforms][PATCH 22/30] RiscVPlatformPkg/Sec: Add more comments to Secmain.c Abner Chang
2021-10-19 8:10 ` [edk2-platforms][PATCH 23/30] RiscV/ProcessorPkg: Create read mtime CSR library instances Abner Chang
2021-10-19 8:10 ` [edk2-platforms][PATCH 24/30] RiscV/ProcessorPkg: Use mtime CSR library Abner Chang
2021-10-19 8:10 ` [edk2-platforms][PATCH 25/30] Silicon/SiFive: " Abner Chang
2021-10-19 8:10 ` [edk2-platforms][PATCH 26/30] SiFive/SerialPortLib: Remove global variable Abner Chang
2021-10-19 8:10 ` [edk2-platforms][PATCH 27/30] RISC-V/PlatformPkg: Updates for the latest OpenSBI Abner Chang
2021-10-19 8:10 ` [edk2-platforms][PATCH 28/30] RiscVPlatformPkg/Sec: Separate EDK2 Opensbi platform hook Abner Chang
2021-10-19 8:10 ` [edk2-platforms][PATCH 29/30] RISC-V/PlatformPkg: Determine hart number from DTB Abner Chang
2021-10-19 8:10 ` [edk2-platforms][PATCH 30/30] Silicon/RISC-V: Add PciCpuIoDxe driver Abner Chang
2021-11-09 4:26 ` [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Daniel Schaefer
2021-11-09 10:06 ` Sunil V L
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211019081007.31165-7-abner.chang@hpe.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox