From: "Zeng, Star" <star.zeng@intel.com>
To: devel@edk2.groups.io
Cc: Star Zeng <star.zeng@intel.com>,
Michael D Kinney <michael.d.kinney@intel.com>,
Liming Gao <gaoliming@byosoft.com.cn>,
Zhiguang Liu <zhiguang.liu@intel.com>, Ray Ni <ray.ni@intel.com>
Subject: [PATCH] MdePkg Cpuid.h: Define CPUID.(EAX=7,ECX=0):EDX[30]
Date: Thu, 21 Oct 2021 11:28:20 +0800 [thread overview]
Message-ID: <20211021032820.355-1-star.zeng@intel.com> (raw)
This patch follows new Intel SDM to define CPUID.(EAX=7,ECX=0):EDX[30].
Signed-off-by: Star Zeng <star.zeng@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
---
MdePkg/Include/Register/Intel/Cpuid.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/MdePkg/Include/Register/Intel/Cpuid.h b/MdePkg/Include/Register/Intel/Cpuid.h
index 6f77e174c115..5ec85ba561ac 100644
--- a/MdePkg/Include/Register/Intel/Cpuid.h
+++ b/MdePkg/Include/Register/Intel/Cpuid.h
@@ -1587,9 +1587,9 @@ typedef union {
///
UINT32 EnumeratesSupportForCapability:1;
///
- /// [Bit 30] Reserved.
+ /// [Bit 30] Enumerates support for the IA32_CORE_CAPABILITIES MSR.
///
- UINT32 Reserved3:1;
+ UINT32 EnumeratesSupportForCoreCapabilitiesMsr:1;
///
/// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD).
/// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow
--
2.27.0.windows.1
next reply other threads:[~2021-10-21 3:28 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-21 3:28 Zeng, Star [this message]
2021-10-22 3:28 ` [PATCH] MdePkg Cpuid.h: Define CPUID.(EAX=7,ECX=0):EDX[30] Ni, Ray
2021-10-28 1:05 ` 回复: [edk2-devel] " gaoliming
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