From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web09.4462.1634786906568674693 for ; Wed, 20 Oct 2021 20:28:26 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: star.zeng@intel.com) X-IronPort-AV: E=McAfee;i="6200,9189,10143"; a="228882333" X-IronPort-AV: E=Sophos;i="5.87,168,1631602800"; d="scan'208";a="228882333" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2021 20:28:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,168,1631602800"; d="scan'208";a="721084610" Received: from shwdeopenlab103.ccr.corp.intel.com ([10.239.56.20]) by fmsmga005.fm.intel.com with ESMTP; 20 Oct 2021 20:28:23 -0700 From: "Zeng, Star" To: devel@edk2.groups.io Cc: Star Zeng , Michael D Kinney , Liming Gao , Zhiguang Liu , Ray Ni Subject: [PATCH] MdePkg Cpuid.h: Define CPUID.(EAX=7,ECX=0):EDX[30] Date: Thu, 21 Oct 2021 11:28:20 +0800 Message-Id: <20211021032820.355-1-star.zeng@intel.com> X-Mailer: git-send-email 2.27.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable This patch follows new Intel SDM to define CPUID.(EAX=3D7,ECX=3D0):EDX[30]. Signed-off-by: Star Zeng Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Ray Ni --- MdePkg/Include/Register/Intel/Cpuid.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/MdePkg/Include/Register/Intel/Cpuid.h b/MdePkg/Include/Registe= r/Intel/Cpuid.h index 6f77e174c115..5ec85ba561ac 100644 --- a/MdePkg/Include/Register/Intel/Cpuid.h +++ b/MdePkg/Include/Register/Intel/Cpuid.h @@ -1587,9 +1587,9 @@ typedef union { ///=0D UINT32 EnumeratesSupportForCapability:1;=0D ///=0D - /// [Bit 30] Reserved.=0D + /// [Bit 30] Enumerates support for the IA32_CORE_CAPABILITIES MSR.=0D ///=0D - UINT32 Reserved3:1;=0D + UINT32 EnumeratesSupportForCoreCapabilitiesMsr:1;=0D ///=0D /// [Bit 31] Enumerates support for Speculative Store Bypass Disable (= SSBD).=0D /// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They= allow=0D --=20 2.27.0.windows.1