From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [216.205.24.124]) by mx.groups.io with SMTP id smtpd.web12.6911.1634808742761963872 for ; Thu, 21 Oct 2021 02:32:23 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=GUb24sOv; spf=pass (domain: redhat.com, ip: 216.205.24.124, mailfrom: kraxel@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1634808740; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TzQGeEgZ8iyTMF8nH7G9Flvpuj2jmOIYRxhgt9IC55s=; b=GUb24sOvzP0XGgHz1LqCVeqA2HNo/Lp6aXpT7W7VizJYVc3/wIiFCcOyZBFvoaDkw2VWmG rPMcymV9yHUpT64jG1tuu4/EXBrC0hhfafPDB+9Lq8/JBFDopgmj7XQ4Jpjw54aeQjRqlM 4R3pF5sTRrv/qHBV5JjJRKNcsLNKKpA= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-497-o61l0zyIO_ibaEo6cuNoEQ-1; Thu, 21 Oct 2021 05:32:15 -0400 X-MC-Unique: o61l0zyIO_ibaEo6cuNoEQ-1 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 6E0DB362F8; Thu, 21 Oct 2021 09:32:13 +0000 (UTC) Received: from sirius.home.kraxel.org (unknown [10.39.192.23]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 3328860C13; Thu, 21 Oct 2021 09:32:13 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id 78E2D1800796; Thu, 21 Oct 2021 11:32:11 +0200 (CEST) Date: Thu, 21 Oct 2021 11:32:11 +0200 From: "Gerd Hoffmann" To: Min Xu Cc: devel@edk2.groups.io, Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: Re: [PATCH V10 4/4] OvmfPkg: Enable TDX in ResetVector Message-ID: <20211021093211.uni6il2jucgb3glt@sirius.home.kraxel.org> References: <8a9d1ec1b30c9fa10284f5d62bc521d156ca32cc.1634774871.git.min.m.xu@intel.com> MIME-Version: 1.0 In-Reply-To: <8a9d1ec1b30c9fa10284f5d62bc521d156ca32cc.1634774871.git.min.m.xu@intel.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=kraxel@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit On Thu, Oct 21, 2021 at 08:17:34AM +0800, Min Xu wrote: > RFC： https://bugzilla.tianocore.org/show_bug.cgi?id=3429 > > Intel's Trust Domain Extensions (Intel TDX) refers to an Intel technology > that extends Virtual Machines Extensions (VMX) and Multi-Key Total Memory > Encryption (MKTME) with a new kind of virutal machines guest called a > Trust Domain (TD). A TD is desinged to run in a CPU mode that protects the > confidentiality of TD memory contents and the TD's CPU state from other > software, including the hosting Virtual-Machine Monitor (VMM), unless > explicitly shared by the TD itself. > > Note: Intel TDX is only available on X64, so the Tdx related changes are > in X64 path. In IA32 path, there may be null stub to make the build > success. > > This patch includes below major changes. > > 1. Ia32/IntelTdx.asm > IntelTdx.asm includes below routines used in ResetVector > - IsTdx > Check if the running system is Tdx guest. > > - InitTdxWorkarea > It initialize the TDX_WORK_AREA. Because it is called by both BSP and > APs and to avoid the race condition, only BSP can initialize the > WORK_AREA. AP will wait until the field of TDX_WORK_AREA_PGTBL_READY > is set. > > - ReloadFlat32 > After reset all CPUs in TDX are initialized to 32-bit protected mode. > But GDT register is not set. So this routine loads the GDT then jump > to Flat 32 protected mode again. > > - InitTdx > This routine wrap above 3 routines together to do Tdx initialization > in ResetVector phase. > > - IsTdxEnabled > It is a OneTimeCall to probe if TDX is enabled by checking the > CC_WORK_AREA. > > - CheckTdxFeaturesBeforeBuildPagetables > This routine is called to check if it is Non-TDX guest, TDX-Bsp or > TDX-APs. Because in TDX guest all the initialization is done by BSP > (including the page tables). APs should not build the tables. > > - TdxPostBuildPageTables > It is called after Page Tables are built by BSP. > byte[TDX_WORK_AREA_PGTBL_READY] is set by BSP to indicate APs can > leave spin and go. > > 2. Ia32/PageTables64.asm > As described above only the TDX BSP build the page tables. So > PageTables64.asm is updated to make sure only TDX BSP build the > PageTables. TDX APs will skip the page table building and set Cr3 > directly. > > 3. Ia16/ResetVectorVtf0.asm > In Tdx all CPUs "reset" to run on 32-bit protected mode with flat > descriptor (paging disabled). But in Non-Td guest the initial state of > CPUs is 16-bit real mode. To resolve this conflict, BITS 16/32 is used > in the ResetVectorVtf0.asm. It checks the 32-bit protected mode or 16-bit > real mode, then jump to the corresponding entry point. Acked-by: Gerd Hoffmann