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These information are essential to the HostBridge driver to initialize the PCIe subsystem. Cc: Thang Nguyen Cc: Chuong Tran Cc: Phong Vo Cc: Leif Lindholm Cc: Michael D Kinney Cc: Ard Biesheuvel Cc: Nate DeSimone Signed-off-by: Nhi Pham --- Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc = | 1 + Silicon/Ampere/AmpereAltraPkg/Library/PciHostBridgeLib/PciHostBridgeLib.in= f | 39 +++ Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h = | 5 + Silicon/Ampere/AmpereAltraPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c = | 256 ++++++++++++++++++++ 4 files changed, 301 insertions(+) diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc b/Silicon= /Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc index edf3e4988625..3b576df24073 100644 --- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dsc.inc @@ -225,6 +225,7 @@ [LibraryClasses.common.DXE_DRIVER] SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + PciHostBridgeLib|Silicon/Ampere/AmpereAltraPkg/Library/PciHostBridgeLib/= PciHostBridgeLib.inf =20 [LibraryClasses.common.UEFI_APPLICATION] UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiTianoCust= omDecompressLib.inf diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/PciHostBridgeLib/PciHost= BridgeLib.inf b/Silicon/Ampere/AmpereAltraPkg/Library/PciHostBridgeLib/PciH= ostBridgeLib.inf new file mode 100644 index 000000000000..fdc7ea8862dc --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/PciHostBridgeLib/PciHostBridgeL= ib.inf @@ -0,0 +1,39 @@ +## @file +# +# Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D PciHostBridgeLib + FILE_GUID =3D 9D0522E5-B5FD-4E3F-9D10-52AE221FA314 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciHostBridgeLib|DXE_DRIVER + +[Sources] + PciHostBridgeLib.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + DevicePathLib + HobLib + MemoryAllocationLib + +[Guids] + gRootComplexInfoHobGuid + +[Protocols] + gEfiCpuIo2ProtocolGuid ## CONSUMES + +[Depex] + gEfiCpuIo2ProtocolGuid diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h b/Silico= n/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h index f3e6b4041737..132c0d6d6cac 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h @@ -239,6 +239,11 @@ // #define AC01_PCIE_MAX_RCS_PER_SOCKET 8 =20 +// +// The size of IO space +// +#define AC01_PCIE_IO_SIZE 0x2000 + // // The base address of {TCU, CSR, MMCONFIG} Registers // diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/PciHostBridgeLib/PciHost= BridgeLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/PciHostBridgeLib/PciHos= tBridgeLib.c new file mode 100644 index 000000000000..cf0f0ee32147 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/PciHostBridgeLib/PciHostBridgeL= ib.c @@ -0,0 +1,256 @@ +/** @file + PCI Host Bridge Library instance for Ampere Altra-based platforms. + + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED +STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] =3D= { + L"Mem", L"I/O", L"Bus" +}; + +#pragma pack(1) +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; +#pragma pack () + +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath =3D { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)), + (UINT8)((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) + } + }, + EISA_PNP_ID (0x0A08), // PCIe + 0 + }, { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } +}; + +STATIC PCI_ROOT_BRIDGE mRootBridgeTemplate =3D { + 0, // Segment + 0, // Supports + 0, // Attributes + TRUE, // DmaAbove4G + FALSE, // NoExtendedConfigSpace + FALSE, // ResourceAssigned + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, + { + // Bus + 0, + 0xFF, + 0 + }, { + // Io + 0, + 0, + 0 + }, { + // Mem + MAX_UINT64, + 0, + 0 + }, { + // MemAbove4G + MAX_UINT64, + 0, + 0 + }, { + // PMem + MAX_UINT64, + 0, + 0 + }, { + // PMemAbove4G + MAX_UINT64, + 0, + 0 + }, + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath +}; + +/** + Return all the root bridge instances in an array. + + @param Count Return the count of root bridge instances. + + @return All the root bridge instances in an array. + The array should be passed into PciHostBridgeFreeRootBridges() + when it's not used. +**/ +PCI_ROOT_BRIDGE * +EFIAPI +PciHostBridgeGetRootBridges ( + UINTN *Count + ) +{ + AC01_ROOT_COMPLEX *RootComplex; + AC01_ROOT_COMPLEX *RootComplexList; + EFI_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath; + PCI_ROOT_BRIDGE *RootBridge; + PCI_ROOT_BRIDGE *RootBridges; + UINT8 Index; + UINT8 RootBridgeCount =3D 0; + VOID *Hob; + + Hob =3D GetFirstGuidHob (&gRootComplexInfoHobGuid); + if (Hob =3D=3D NULL) { + return NULL; + } + + RootComplexList =3D (AC01_ROOT_COMPLEX *)GET_GUID_HOB_DATA (Hob); + + RootBridges =3D AllocatePool (AC01_PCIE_MAX_ROOT_COMPLEX * sizeof (PCI_R= OOT_BRIDGE)); + if (RootBridges =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Failed to allocate RootBridges\n", __FUNCTIO= N__)); + return NULL; + } + + for (Index =3D 0; Index < AC01_PCIE_MAX_ROOT_COMPLEX; Index++) { + RootComplex =3D &RootComplexList[Index]; + if (!RootComplex->Active) { + continue; + } + RootBridge =3D &RootBridges[RootBridgeCount]; + CopyMem (RootBridge, &mRootBridgeTemplate, sizeof (PCI_ROOT_BRIDGE)); + + if (RootComplex->Mmio32Base !=3D 0) { + RootBridge->Mem.Base =3D RootComplex->Mmio32Base; + RootBridge->Mem.Limit =3D RootComplex->Mmio32Base + RootComplex->Mmi= o32Size - 1; + RootBridge->PMem.Base =3D RootBridge->Mem.Base; + RootBridge->PMem.Limit =3D RootBridge->Mem.Limit; + RootBridge->Io.Base =3D RootComplex->Mmio32Base + RootComplex->Mmio3= 2Size - AC01_PCIE_IO_SIZE; + RootBridge->Io.Limit =3D RootBridge->Mem.Limit; + } + + if (RootComplex->MmioBase !=3D 0) { + RootBridge->PMemAbove4G.Base =3D RootComplex->MmioBase; + RootBridge->PMemAbove4G.Limit =3D RootComplex->MmioBase + RootComple= x->MmioSize - 1; + } + + RootBridge->Segment =3D RootComplex->Logical; + + DevicePath =3D AllocateCopyPool ( + sizeof (EFI_PCI_ROOT_BRIDGE_DEVICE_PATH), + (VOID *)&mEfiPciRootBridgeDevicePath + ); + if (DevicePath =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Failed to allocate device path\n", __FUNCT= ION__)); + return NULL; + } + + // + // Embedded the Root Complex Index into the DevicePath + // This will be used later by the platform NotifyPhase() + // + DevicePath->AcpiDevicePath.UID =3D Index; + + RootBridge->DevicePath =3D (EFI_DEVICE_PATH_PROTOCOL *)DevicePath; + RootBridgeCount++; + } + + *Count =3D RootBridgeCount; + return RootBridges; +} + +/** + Free the root bridge instances array returned from PciHostBridgeGetRootB= ridges(). + + @param Bridges The root bridge instances array. + @param Count The count of the array. +**/ +VOID +EFIAPI +PciHostBridgeFreeRootBridges ( + PCI_ROOT_BRIDGE *Bridges, + UINTN Count + ) +{ + // + // Unsupported + // +} + +/** + Inform the platform that the resource conflict happens. + + @param HostBridgeHandle Handle of the Host Bridge. + @param Configuration Pointer to PCI I/O and PCI memory resource + descriptors. The Configuration contains the reso= urces + for all the root bridges. The resource for each = root + bridge is terminated with END descriptor and an + additional END is appended indicating the end of= the + entire resources. The resource descriptor field + values follow the description in + EFI_PCI_HOST_BRIDGE_RESOUrce_ALLOCATION_PROTOCOL + .SubmitResources(). +**/ +VOID +EFIAPI +PciHostBridgeResourceConflict ( + EFI_HANDLE HostBridgeHandle, + VOID *Configuration + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + UINTN RootBridgeIndex; + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n")); + + RootBridgeIndex =3D 0; + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration; + while (Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); + for (; Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR; Descript= or++) { + ASSERT (Descriptor->ResType < + (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) / + sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0]) + ) + ); + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment =3D 0x%lx / 0x%lx\n", + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType= ], + Descriptor->AddrLen, Descriptor->AddrRangeMax + )); + if (Descriptor->ResType =3D=3D ACPI_ADDRESS_SPACE_TYPE_MEM) { + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag =3D %ld / %02x= %s\n", + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag= , + ((Descriptor->SpecificFlag & + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETC= HABLE + ) !=3D 0) ? L" (Prefetchable)" : L"" + )); + } + } + // + // Skip the END descriptor for root bridge + // + ASSERT (Descriptor->Desc =3D=3D ACPI_END_TAG_DESCRIPTOR); + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 + ); + } +} --=20 2.17.1