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vunguyen@os.amperecomputing.com, Thang Nguyen , Chuong Tran , Phong Vo , Leif Lindholm , Michael D Kinney , Ard Biesheuvel , Nate DeSimone Subject: [edk2-platforms][PATCH v4 24/31] AmpereAltraPkg: Add configuration screen for PCIe Date: Fri, 22 Oct 2021 13:18:02 +0700 Message-ID: <20211022061809.31087-25-nhi@os.amperecomputing.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211022061809.31087-1-nhi@os.amperecomputing.com> References: <20211022061809.31087-1-nhi@os.amperecomputing.com> X-ClientProxiedBy: HK2PR02CA0168.apcprd02.prod.outlook.com (2603:1096:201:1f::28) To PH0PR01MB7287.prod.exchangelabs.com (2603:10b6:510:10a::21) Return-Path: nhi@os.amperecomputing.com MIME-Version: 1.0 Received: from sw004.amperecomputing.com (118.69.219.201) by HK2PR02CA0168.apcprd02.prod.outlook.com (2603:1096:201:1f::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.16 via Frontend Transport; Fri, 22 Oct 2021 06:20:40 +0000 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quoted-printable Content-Type: text/plain From: Vu Nguyen This menu screen allows the user to: - Enable/Disable each Root Complex - Enable/Disable SMMU support - Enable/Disable Strong Ordering - Set Bifurcation mode for each Root Complex Cc: Thang Nguyen Cc: Chuong Tran Cc: Phong Vo Cc: Leif Lindholm Cc: Michael D Kinney Cc: Ard Biesheuvel Cc: Nate DeSimone Signed-off-by: Nhi Pham --- Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec = | 3 + Platform/Ampere/JadePkg/Jade.dsc = | 5 + Platform/Ampere/JadePkg/Jade.fdf = | 5 + Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConf= igDxe.inf | 61 + Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConf= igDxe.h | 114 ++ Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConf= igNVDataStruct.h | 91 ++ Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexConfigHii.h = | 33 + Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConf= igVfr.vfr | 219 ++++ Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConf= igDxe.c | 1226 ++++++++++++++++++++ Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConf= igDxe.uni | 102 ++ 10 files changed, 1859 insertions(+) diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec b/Silicon/Amp= ere/AmpereAltraPkg/AmpereAltraPkg.dec index 7bd4d3ac9462..460255768aed 100644 --- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec @@ -61,3 +61,6 @@ [Guids] =20 ## Include/Guid/RootComplexInfoHob.h gRootComplexInfoHobGuid =3D { 0x568a258a, 0xcaa1, 0x47e9, { 0xbb, 0= x89, 0x65, 0xa3, 0x73, 0x9b, 0x58, 0x75 } } + + ## Include/Guid/RootComplexConfigHii.h + gRootComplexConfigFormSetGuid =3D { 0xE84E70D6, 0xE4B2, 0x4C6E, { 0x98, = 0x51, 0xCB, 0x2B, 0xAC, 0x77, 0x7D, 0xBB } } diff --git a/Platform/Ampere/JadePkg/Jade.dsc b/Platform/Ampere/JadePkg/Jad= e.dsc index 03932215b499..6c4294bef159 100644 --- a/Platform/Ampere/JadePkg/Jade.dsc +++ b/Platform/Ampere/JadePkg/Jade.dsc @@ -181,3 +181,8 @@ [Components.common] Platform/Ampere/JadePkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf Platform/Ampere/JadePkg/Drivers/SmbiosMemInfoDxe/SmbiosMemInfoDxe.inf + + # + # HII + # + Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexCo= nfigDxe.inf diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jad= e.fdf index 84b7b36cbc43..8891bad8f55e 100644 --- a/Platform/Ampere/JadePkg/Jade.fdf +++ b/Platform/Ampere/JadePkg/Jade.fdf @@ -352,4 +352,9 @@ [FV.FvMain] INF ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.in= f INF Platform/Ampere/JadePkg/Drivers/SmbiosMemInfoDxe/SmbiosMemInfoDxe.in= f =20 + # + # HII + # + INF Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootCompl= exConfigDxe.inf + !include Silicon/Ampere/AmpereSiliconPkg/FvRules.fdf.inc diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/Roo= tComplexConfigDxe.inf b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexCo= nfigDxe/RootComplexConfigDxe.inf new file mode 100644 index 000000000000..b0c66109a92a --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComple= xConfigDxe.inf @@ -0,0 +1,61 @@ +## @file +# +# Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D RootComplexConfigDxe + FILE_GUID =3D 9820A15A-ECFE-404B-97C8-A2B76F0AB103 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D RootComplexDriverEntry + +[Sources.common] + RootComplexConfigDxe.c + RootComplexConfigDxe.h + RootComplexConfigDxe.uni + RootComplexConfigNVDataStruct.h + RootComplexConfigVfr.vfr + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec + Silicon/Ampere/AmpereSiliconPkg/AmpereSiliconPkg.dec + +[LibraryClasses] + AmpereCpuLib + BaseLib + BaseMemoryLib + DebugLib + DevicePathLib + HiiLib + HobLib + MemoryAllocationLib + NVParamLib + PrintLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + +[Protocols] + gEfiDevicePathProtocolGuid + gEfiHiiStringProtocolGuid ## CONSUMES + gEfiHiiConfigRoutingProtocolGuid ## CONSUMES + gEfiHiiConfigAccessProtocolGuid ## PRODUCES + gEfiHiiDatabaseProtocolGuid ## CONSUMES + gEfiConfigKeywordHandlerProtocolGuid ## CONSUMES + +[Guids] + gEfiIfrTianoGuid ## CONSUMES + gPlatformInfoHobGuid ## CONSUMES + gPlatformManagerFormsetGuid ## CONSUMES + gRootComplexConfigFormSetGuid ## CONSUMES + gRootComplexInfoHobGuid ## CONSUMES + +[Depex] + TRUE diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/Roo= tComplexConfigDxe.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConf= igDxe/RootComplexConfigDxe.h new file mode 100644 index 000000000000..c02ee765a19a --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComple= xConfigDxe.h @@ -0,0 +1,114 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef BOARD_PCIE_SCREEN_H_ +#define BOARD_PCIE_SCREEN_H_ + +#include "RootComplexConfigNVDataStruct.h" + +// +// This is the generated IFR binary data for each formset defined in VFR. +// This data array is ready to be used as input of HiiAddPackages() to +// create a packagelist (which contains Form packages, String packages, et= c). +// +extern UINT8 RootComplexConfigVfrBin[]; + +// +// This is the generated String package data for all .UNI files. +// This data array is ready to be used as input of HiiAddPackages() to +// create a packagelist (which contains Form packages, String packages, et= c). +// +extern UINT8 RootComplexConfigDxeStrings[]; + +#define MAX_EDITABLE_ELEMENTS 3 +#define RC0_STATUS_OFFSET \ + OFFSET_OF (ROOT_COMPLEX_CONFIG_VARSTORE_DATA, RCStatus[0]) +#define RC0_BIFUR_LO_OFFSET \ + OFFSET_OF (ROOT_COMPLEX_CONFIG_VARSTORE_DATA, RCBifurcationLow[0]) +#define RC0_BIFUR_HI_OFFSET \ + OFFSET_OF (ROOT_COMPLEX_CONFIG_VARSTORE_DATA, RCBifurcationHigh[0]) +#define SMMU_PMU_OFFSET \ + OFFSET_OF (ROOT_COMPLEX_CONFIG_VARSTORE_DATA, SmmuPmu) + +#define STRONG_ORDERING_OFFSET \ + OFFSET_OF (NVPARAM_ROOT_COMPLEX_CONFIG_VARSTORE_DATA, PcieStrongOrdering= ) + +// +// Signature: Ampere Computing PCIe Screen +// +#define SCREEN_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('A', 'C', 'P', 'S') + +#define MAX_STRING_SIZE 32 + +#define STRONG_ORDERING_DEFAULT_OPTION_VALUE 1 +#define STRONG_ORDERING_DEFAULT_NVPARAM_VALUE 0xFFFFFFFF + +typedef struct { + UINTN Signature; + + EFI_HANDLE DriverHandle; + EFI_HII_HANDLE HiiHandle; + ROOT_COMPLEX_CONFIG_VARSTORE_DATA VarStoreConfig; + NVPARAM_ROOT_COMPLEX_CONFIG_VARSTORE_DATA NVParamVarStoreConfig= ; + + // + // Consumed protocol + // + EFI_HII_DATABASE_PROTOCOL *HiiDatabase; + EFI_HII_STRING_PROTOCOL *HiiString; + EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting; + EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL *HiiKeywordHandler; + + // + // Produced protocol + // + EFI_HII_CONFIG_ACCESS_PROTOCOL ConfigAccess; +} SCREEN_PRIVATE_DATA; + +typedef struct { + UINTN PciDevIdx; + EFI_STRING_ID GotoStringId; + EFI_STRING_ID GotoHelpStringId; + UINT16 GotoKey; + BOOLEAN ShowItem; +} SETUP_GOTO_DATA; + +#define SCREEN_PRIVATE_FROM_THIS(a) \ + CR (a, SCREEN_PRIVATE_DATA, ConfigAccess, SCREEN_PRIVATE_DATA_SIGNATURE) + +#pragma pack(1) + +/// +/// HII specific Vendor Device Path definition. +/// +typedef struct { + VENDOR_DEVICE_PATH VendorDevicePath; + EFI_DEVICE_PATH_PROTOCOL End; +} HII_VENDOR_DEVICE_PATH; + +#pragma pack() + +UINT8 +PcieRCDevMapLowDefaultSetting ( + IN UINTN RCIndex, + IN SCREEN_PRIVATE_DATA *PrivateData + ); + +UINT8 +PcieRCDevMapHighDefaultSetting ( + IN UINTN RCIndex, + IN SCREEN_PRIVATE_DATA *PrivateData + ); + +BOOLEAN +PcieRCActiveDefaultSetting ( + IN UINTN RCIndex, + IN SCREEN_PRIVATE_DATA *PrivateData + ); + +#endif /* BOARD_PCIE_SCREEN_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/Roo= tComplexConfigNVDataStruct.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootCo= mplexConfigDxe/RootComplexConfigNVDataStruct.h new file mode 100644 index 000000000000..3350f6eb7fe4 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComple= xConfigNVDataStruct.h @@ -0,0 +1,91 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef BOARD_PCIE_VFR_H_ +#define BOARD_PCIE_VFR_H_ + +#include + +#define VARSTORE_ID 0x1234 +#define FORM_ID 0x1235 +#define RC0_FORM_ID 0x1236 +#define RC1_FORM_ID 0x1237 +#define RC2_FORM_ID 0x1238 +#define RC3_FORM_ID 0x1239 +#define RC4_FORM_ID 0x123A +#define RC5_FORM_ID 0x123B +#define RC6_FORM_ID 0x123C +#define RC7_FORM_ID 0x123D +#define RC8_FORM_ID 0x123E +#define RC9_FORM_ID 0x123F +#define RC10_FORM_ID 0x1240 +#define RC11_FORM_ID 0x1241 +#define RC12_FORM_ID 0x1242 +#define RC13_FORM_ID 0x1243 +#define RC14_FORM_ID 0x1244 +#define RC15_FORM_ID 0x1245 + +#define QUESTION_ID_BASE 0x8002 +#define GOTO_ID_BASE 0x8040 + +#define SMMU_PMU_ID 0x9000 +#define STRONG_ORDERING_ID 0x9001 + +#define NVPARAM_VARSTORE_NAME L"PcieIfrNVParamData" +#define NVPARAM_VARSTORE_ID 0x1233 + +#pragma pack(1) + +// +// NVParam data structure definition +// +typedef struct { + BOOLEAN PcieStrongOrdering; +} NVPARAM_ROOT_COMPLEX_CONFIG_VARSTORE_DATA; + +#pragma pack() + +// +// Labels definition +// +#define LABEL_UPDATE 0x2223 +#define LABEL_END 0x2224 +#define LABEL_RC0_UPDATE 0x2225 +#define LABEL_RC0_END 0x2226 +#define LABEL_RC1_UPDATE 0x2227 +#define LABEL_RC1_END 0x2228 +#define LABEL_RC2_UPDATE 0x2229 +#define LABEL_RC2_END 0x222A +#define LABEL_RC3_UPDATE 0x222B +#define LABEL_RC3_END 0x222C +#define LABEL_RC4_UPDATE 0x222D +#define LABEL_RC4_END 0x222E +#define LABEL_RC5_UPDATE 0x222F +#define LABEL_RC5_END 0x2230 +#define LABEL_RC6_UPDATE 0x2231 +#define LABEL_RC6_END 0x2232 +#define LABEL_RC7_UPDATE 0x2233 +#define LABEL_RC7_END 0x2234 +#define LABEL_RC8_UPDATE 0x2235 +#define LABEL_RC8_END 0x2236 +#define LABEL_RC9_UPDATE 0x2237 +#define LABEL_RC9_END 0x2238 +#define LABEL_RC10_UPDATE 0x2239 +#define LABEL_RC10_END 0x223A +#define LABEL_RC11_UPDATE 0x223B +#define LABEL_RC11_END 0x223C +#define LABEL_RC12_UPDATE 0x223D +#define LABEL_RC12_END 0x223E +#define LABEL_RC13_UPDATE 0x223F +#define LABEL_RC13_END 0x2240 +#define LABEL_RC14_UPDATE 0x2241 +#define LABEL_RC14_END 0x2242 +#define LABEL_RC15_UPDATE 0x2243 +#define LABEL_RC15_END 0x2244 + +#endif /* BOARD_PCIE_VFR_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexConfigHi= i.h b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexConfigHii.h new file mode 100644 index 000000000000..d82604cdf85e --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexConfigHii.h @@ -0,0 +1,33 @@ +/** @file + + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef ROOT_COMPLEX_CONFIG_HII_H_ +#define ROOT_COMPLEX_CONFIG_HII_H_ + +#include + +#define ROOT_COMPLEX_CONFIG_FORMSET_GUID \ + { \ + 0xE84E70D6, 0xE4B2, 0x4C6E, { 0x98, 0x51, 0xCB, 0x2B, 0xAC, 0x77, 0x7= D, 0xBB } \ + } + +extern EFI_GUID gRootComplexConfigFormSetGuid; + +// +// NV data structure definition +// +typedef struct { + BOOLEAN RCStatus[AC01_PCIE_MAX_ROOT_COMPLEX]; + UINT8 RCBifurcationLow[AC01_PCIE_MAX_ROOT_COMPLEX]; + UINT8 RCBifurcationHigh[AC01_PCIE_MAX_ROOT_COMPLEX]; + UINT32 SmmuPmu; +} ROOT_COMPLEX_CONFIG_VARSTORE_DATA; + +#define ROOT_COMPLEX_CONFIG_VARSTORE_NAME L"PcieIfrNVData" + +#endif /* ROOT_COMPLEX_CONFIG_HII_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/Roo= tComplexConfigVfr.vfr b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexCo= nfigDxe/RootComplexConfigVfr.vfr new file mode 100644 index 000000000000..4772d3c45cfb --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComple= xConfigVfr.vfr @@ -0,0 +1,219 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include "RootComplexConfigNVDataStruct.h" + +formset + guid =3D ROOT_COMPLEX_CONFIG_FORMSET_GUID, + title =3D STRING_TOKEN(STR_PCIE_FORM), + help =3D STRING_TOKEN(STR_PCIE_FORM_HELP), + classguid =3D gPlatformManagerFormsetGuid, + + // + // Define a variable Storage + // + varstore ROOT_COMPLEX_CONFIG_VARSTORE_DATA, + varid =3D VARSTORE_ID, + name =3D PcieIfrNVData, + guid =3D ROOT_COMPLEX_CONFIG_FORMSET_GUID; + + varstore NVPARAM_ROOT_COMPLEX_CONFIG_VARSTORE_DATA, + varid =3D NVPARAM_VARSTORE_ID, + name =3D PcieIfrNVParamData, + guid =3D ROOT_COMPLEX_CONFIG_FORMSET_GUID; + + form + formid =3D FORM_ID, + title =3D STRING_TOKEN(STR_PCIE_FORM); + + subtitle text =3D STRING_TOKEN(STR_PCIE_FORM); + + label LABEL_UPDATE; + // dynamic content here + label LABEL_END; + endform; + + form + formid =3D RC0_FORM_ID, + title =3D STRING_TOKEN(STR_PCIE_RC0_FORM); + + subtitle text =3D STRING_TOKEN(STR_PCIE_RC0_FORM); + + label LABEL_RC0_UPDATE; + // dynamic content here + label LABEL_RC0_END; + endform; + + form + formid =3D RC1_FORM_ID, + title =3D STRING_TOKEN(STR_PCIE_RC1_FORM); + + subtitle text =3D STRING_TOKEN(STR_PCIE_RC1_FORM); + + label LABEL_RC1_UPDATE; + // dynamic content here + label LABEL_RC1_END; + endform; + + form + formid =3D RC2_FORM_ID, + title =3D STRING_TOKEN(STR_PCIE_RC2_FORM); + + subtitle text =3D STRING_TOKEN(STR_PCIE_RC2_FORM); + + label LABEL_RC2_UPDATE; + // dynamic content here + label LABEL_RC2_END; + endform; + + form + formid =3D RC3_FORM_ID, + title =3D STRING_TOKEN(STR_PCIE_RC3_FORM); + + subtitle text =3D STRING_TOKEN(STR_PCIE_RC3_FORM); + + label LABEL_RC3_UPDATE; + // dynamic content here + label LABEL_RC3_END; + endform; + + form + formid =3D RC4_FORM_ID, + title =3D STRING_TOKEN(STR_PCIE_RC4_FORM); + + subtitle text =3D STRING_TOKEN(STR_PCIE_RC4_FORM); + + label LABEL_RC4_UPDATE; + // dynamic content here + label LABEL_RC4_END; + endform; + + form + formid =3D RC5_FORM_ID, + title =3D STRING_TOKEN(STR_PCIE_RC5_FORM); + + subtitle text =3D STRING_TOKEN(STR_PCIE_RC5_FORM); + + label LABEL_RC5_UPDATE; + // dynamic content here + label LABEL_RC5_END; + endform; + + form + formid =3D RC6_FORM_ID, + title =3D STRING_TOKEN(STR_PCIE_RC6_FORM); + + subtitle text =3D STRING_TOKEN(STR_PCIE_RC6_FORM); + + label LABEL_RC6_UPDATE; + // dynamic content here + label LABEL_RC6_END; + endform; + + form + formid =3D RC7_FORM_ID, + title =3D STRING_TOKEN(STR_PCIE_RC7_FORM); + + subtitle text =3D STRING_TOKEN(STR_PCIE_RC7_FORM); + + label LABEL_RC7_UPDATE; + // dynamic content here + label LABEL_RC7_END; + endform; + + form + formid =3D RC8_FORM_ID, + title =3D STRING_TOKEN(STR_PCIE_RC8_FORM); + + subtitle text =3D STRING_TOKEN(STR_PCIE_RC8_FORM); + + label LABEL_RC8_UPDATE; + // dynamic content here + label LABEL_RC8_END; + endform; + + form + formid =3D RC9_FORM_ID, + title =3D STRING_TOKEN(STR_PCIE_RC9_FORM); + + subtitle text =3D STRING_TOKEN(STR_PCIE_RC9_FORM); + + label LABEL_RC9_UPDATE; + // dynamic content here + label LABEL_RC9_END; + endform; + + form + formid =3D RC10_FORM_ID, + title =3D STRING_TOKEN(STR_PCIE_RC10_FORM); + + subtitle text =3D STRING_TOKEN(STR_PCIE_RC10_FORM); + + label LABEL_RC10_UPDATE; + // dynamic content here + label LABEL_RC10_END; + endform; + + form + formid =3D RC11_FORM_ID, + title =3D STRING_TOKEN(STR_PCIE_RC11_FORM); + + subtitle text =3D STRING_TOKEN(STR_PCIE_RC11_FORM); + + label LABEL_RC11_UPDATE; + // dynamic content here + label LABEL_RC11_END; + endform; + + form + formid =3D RC12_FORM_ID, + title =3D STRING_TOKEN(STR_PCIE_RC12_FORM); + + subtitle text =3D STRING_TOKEN(STR_PCIE_RC12_FORM); + + label LABEL_RC12_UPDATE; + // dynamic content here + label LABEL_RC12_END; + endform; + + form + formid =3D RC13_FORM_ID, + title =3D STRING_TOKEN(STR_PCIE_RC13_FORM); + + subtitle text =3D STRING_TOKEN(STR_PCIE_RC13_FORM); + + label LABEL_RC13_UPDATE; + // dynamic content here + label LABEL_RC13_END; + endform; + + form + formid =3D RC14_FORM_ID, + title =3D STRING_TOKEN(STR_PCIE_RC14_FORM); + + subtitle text =3D STRING_TOKEN(STR_PCIE_RC14_FORM); + + label LABEL_RC14_UPDATE; + // dynamic content here + label LABEL_RC14_END; + endform; + + form + formid =3D RC15_FORM_ID, + title =3D STRING_TOKEN(STR_PCIE_RC15_FORM); + + subtitle text =3D STRING_TOKEN(STR_PCIE_RC15_FORM); + + label LABEL_RC15_UPDATE; + // dynamic content here + label LABEL_RC15_END; + endform; + +endformset; diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/Roo= tComplexConfigDxe.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConf= igDxe/RootComplexConfigDxe.c new file mode 100644 index 000000000000..e03be2a2f9dc --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComple= xConfigDxe.c @@ -0,0 +1,1226 @@ +/** @file + + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "RootComplexConfigDxe.h" + +BOOLEAN mReadOnlyStrongOrdering; +CHAR16 mPcieNvparamVarstoreName[] =3D NVPARAM_VARSTORE_NAME; +CHAR16 gPcieVarstoreName[] =3D ROOT_COMPLEX_CONFIG_VARSTORE_NAM= E; +EFI_GUID gPcieFormSetGuid =3D ROOT_COMPLEX_CONFIG_FORMSET_GUID= ; + +SCREEN_PRIVATE_DATA *mPrivateData =3D NULL; + +HII_VENDOR_DEVICE_PATH mHiiVendorDevicePath =3D { + { + { + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + { + (UINT8)(sizeof (VENDOR_DEVICE_PATH)), + (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8) + } + }, + ROOT_COMPLEX_CONFIG_FORMSET_GUID + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + (UINT8)(END_DEVICE_PATH_LENGTH), + (UINT8)((END_DEVICE_PATH_LENGTH) >> 8) + } + } +}; + +BOOLEAN +IsEmptyRC ( + IN AC01_ROOT_COMPLEX *RootComplex + ) +{ + UINT8 Idx; + + for (Idx =3D PcieController0; Idx < MaxPcieController; Idx++) { + if (RootComplex->Pcie[Idx].Active) { + return FALSE; + } + } + + return TRUE; +} + +AC01_ROOT_COMPLEX * +GetRootComplex ( + UINT8 Index + ) +{ + AC01_ROOT_COMPLEX *RootComplexList; + VOID *Hob; + + Hob =3D GetFirstGuidHob (&gRootComplexInfoHobGuid); + if (Hob =3D=3D NULL) { + return NULL; + } + + RootComplexList =3D (AC01_ROOT_COMPLEX *)GET_GUID_HOB_DATA (Hob); + return &RootComplexList[Index]; +} + +/** + This function allows a caller to extract the current configuration for o= ne + or more named elements from the target driver. + + @param This Points to the EFI_HII_CONFIG_ACCESS_PROTO= COL. + @param Request A null-terminated Unicode string in + format. + @param Progress On return, points to a character in the R= equest + string. Points to the string's null termi= nator if + request was successful. Points to the mos= t recent + '&' before the first failing name/value p= air (or + the beginning of the string if the failur= e is in + the first name/value pair) if the request= was not + successful. + @param Results A null-terminated Unicode string in + format which has all valu= es filled + in for the names in the Request string. S= tring to + be allocated by the called function. + @retval EFI_SUCCESS The Results is filled with the requested = values. + @retval EFI_OUT_OF_RESOURCES Not enough memory to store the results. + @retval EFI_INVALID_PARAMETER Request is illegal syntax, or unknown nam= e. + @retval EFI_NOT_FOUND Routing data doesn't match any storage in= this + driver. +**/ +EFI_STATUS +EFIAPI +ExtractConfig ( + IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This, + IN CONST EFI_STRING Request, + OUT EFI_STRING *Progress, + OUT EFI_STRING *Results + ) +{ + EFI_STATUS Status; + UINTN BufferSize; + SCREEN_PRIVATE_DATA *PrivateData; + EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting; + EFI_STRING ConfigRequest; + UINTN Size; + CHAR16 *StrPointer; + BOOLEAN AllocatedRequest; + UINT8 *VarStoreConfig; + UINT32 Value; + + if (Progress =3D=3D NULL || Results =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if (Request =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + // + // Initialize the local variables. + // + ConfigRequest =3D NULL; + Size =3D 0; + *Progress =3D Request; + AllocatedRequest =3D FALSE; + + PrivateData =3D SCREEN_PRIVATE_FROM_THIS (This); + HiiConfigRouting =3D PrivateData->HiiConfigRouting; + + // + // Check routing data in . + // Note: if only one Storage is used, then this checking could be skippe= d. + // + if (HiiIsConfigHdrMatch (Request, &gPcieFormSetGuid, mPcieNvparamVarstor= eName)) { + VarStoreConfig =3D (UINT8 *)&PrivateData->NVParamVarStoreConfig; + ASSERT (VarStoreConfig !=3D NULL); + + Status =3D NVParamGet ( + NV_SI_MESH_S0_CXG_RC_STRONG_ORDERING_EN, + NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC, + &Value + ); + ASSERT_EFI_ERROR (Status); + if (Value !=3D 0) { + PrivateData->NVParamVarStoreConfig.PcieStrongOrdering =3D TRUE; + } + + Status =3D NVParamGet ( + NV_SI_MESH_S1_CXG_RC_STRONG_ORDERING_EN, + NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC, + &Value + ); + ASSERT_EFI_ERROR (Status); + if (Value !=3D 0) { + PrivateData->NVParamVarStoreConfig.PcieStrongOrdering =3D TRUE; + } + + BufferSize =3D sizeof (NVPARAM_ROOT_COMPLEX_CONFIG_VARSTORE_DATA); + + } else if (HiiIsConfigHdrMatch (Request, &gPcieFormSetGuid, gPcieVarstor= eName)) { + VarStoreConfig =3D (UINT8 *)&PrivateData->VarStoreConfig; + ASSERT (VarStoreConfig !=3D NULL); + + // + // Get Buffer Storage data from EFI variable. + // Try to get the current setting from variable. + // + BufferSize =3D sizeof (ROOT_COMPLEX_CONFIG_VARSTORE_DATA); + Status =3D gRT->GetVariable ( + gPcieVarstoreName, + &gPcieFormSetGuid, + NULL, + &BufferSize, + VarStoreConfig + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + } else { + return EFI_NOT_FOUND; + } + + // + // Set Request to the unified request string. + // + ConfigRequest =3D Request; + + // + // Check whether Request includes Request Element. + // + if (StrStr (Request, L"OFFSET") =3D=3D NULL) { + // + // Check Request Element does exist in Request String + // + StrPointer =3D StrStr (Request, L"PATH"); + if (StrPointer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + if (StrStr (StrPointer, L"&") =3D=3D NULL) { + // + // Allocate and fill a buffer large enough to hold the t= emplate + // followed by "&OFFSET=3D0&WIDTH=3DWWWWWWWWWWWWWWWW" followed by a = Null-terminator + // + Size =3D (StrLen (Request) + 32 + 1) * sizeof (CHAR16); + ConfigRequest =3D AllocateZeroPool (Size); + ASSERT (ConfigRequest !=3D NULL); + AllocatedRequest =3D TRUE; + UnicodeSPrint ( + ConfigRequest, + Size, + L"%s&OFFSET=3D0&WIDTH=3D%016LX", + Request, + (UINT64)BufferSize + ); + } + } + + // + // Convert buffer data to by helper function BlockToConfig(= ) + // + Status =3D HiiConfigRouting->BlockToConfig ( + HiiConfigRouting, + ConfigRequest, + VarStoreConfig, + BufferSize, + Results, + Progress + ); + + // + // Free the allocated config request string. + // + if (AllocatedRequest) { + FreePool (ConfigRequest); + } + + // + // Set Progress string to the original request string. + // + if (Request =3D=3D NULL) { + *Progress =3D NULL; + } else if (StrStr (Request, L"OFFSET") =3D=3D NULL) { + *Progress =3D Request + StrLen (Request); + } + + return Status; +} + +/** + This function processes the results of changes in configuration. + + @param This Points to the EFI_HII_CONFIG_ACCESS_PROTO= COL. + @param Configuration A null-terminated Unicode string in + format. + @param Progress A pointer to a string filled in with the = offset of + the most recent '&' before the first fail= ing + name/value pair (or the beginning of the = string if + the failure is in the first name/value pa= ir) or + the terminating NULL if all was successfu= l. + @retval EFI_SUCCESS The Results is processed successfully. + @retval EFI_INVALID_PARAMETER Configuration is NULL. + @retval EFI_NOT_FOUND Routing data doesn't match any storage in= this + driver. +**/ +EFI_STATUS +EFIAPI +RouteConfig ( + IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This, + IN CONST EFI_STRING Configuration, + OUT EFI_STRING *Progress + ) +{ + EFI_STATUS Status; + UINTN BufferSize; + SCREEN_PRIVATE_DATA *PrivateData; + EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting; + UINT8 *VarStoreConfig; + UINT32 Value; + + if (Configuration =3D=3D NULL || Progress =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + PrivateData =3D SCREEN_PRIVATE_FROM_THIS (This); + HiiConfigRouting =3D PrivateData->HiiConfigRouting; + *Progress =3D Configuration; + + if (HiiIsConfigHdrMatch (Configuration, &gPcieFormSetGuid, mPcieNvparamV= arstoreName)) { + VarStoreConfig =3D (UINT8 *)&PrivateData->NVParamVarStoreConfig; + BufferSize =3D sizeof (NVPARAM_ROOT_COMPLEX_CONFIG_VARSTORE_DATA); + } else if (HiiIsConfigHdrMatch (Configuration, &gPcieFormSetGuid, gPcieV= arstoreName)) { + BufferSize =3D sizeof (ROOT_COMPLEX_CONFIG_VARSTORE_DATA); + VarStoreConfig =3D (UINT8 *)&PrivateData->VarStoreConfig; + } + ASSERT (VarStoreConfig !=3D NULL); + + // + // Check if configuring Name/Value storage + // + if (StrStr (Configuration, L"OFFSET") =3D=3D NULL) { + // + // Don't have any Name/Value storage names + // + return EFI_SUCCESS; + } + + // + // Convert to buffer data by helper function ConfigToBlock(= ) + // + Status =3D HiiConfigRouting->ConfigToBlock ( + HiiConfigRouting, + Configuration, + (UINT8 *)VarStoreConfig, + &BufferSize, + Progress + ); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Check routing data in . + // + if (HiiIsConfigHdrMatch (Configuration, &gPcieFormSetGuid, mPcieNvparamV= arstoreName)) { + Value =3D PrivateData->NVParamVarStoreConfig.PcieStrongOrdering ? + STRONG_ORDERING_DEFAULT_NVPARAM_VALUE : 0; + + if (!mReadOnlyStrongOrdering) { + // + // Update whole 16 RCs. + // + Status =3D NVParamSet ( + NV_SI_MESH_S0_CXG_RC_STRONG_ORDERING_EN, + NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC, + NV_PERM_BIOS | NV_PERM_MANU, + Value + ); + ASSERT_EFI_ERROR (Status); + + // + // No need to check slave present + // + Status =3D NVParamSet ( + NV_SI_MESH_S1_CXG_RC_STRONG_ORDERING_EN, + NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC, + NV_PERM_BIOS | NV_PERM_MANU, + Value + ); + ASSERT_EFI_ERROR (Status); + } + } else if (HiiIsConfigHdrMatch (Configuration, &gPcieFormSetGuid, gPcieV= arstoreName)) { + // + // Store Buffer Storage back to variable + // + Status =3D gRT->SetVariable ( + gPcieVarstoreName, + &gPcieFormSetGuid, + EFI_VARIABLE_NON_VOLATILE | + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS, + sizeof (ROOT_COMPLEX_CONFIG_VARSTORE_DATA), + (ROOT_COMPLEX_CONFIG_VARSTORE_DATA *)VarStoreConfig + ); + } + + return Status; +} + +/** + This function processes the results of changes in configuration. + + @param This Points to the EFI_HII_CONFIG_ACCESS_PROTO= COL. + @param Action Specifies the type of action taken by the= browser. + @param QuestionId A unique value which is sent to the origi= nal + exporting driver so that it can identify = the type + of data to expect. + @param Type The type of value for the question. + @param Value A pointer to the data being sent to the o= riginal + exporting driver. + @param ActionRequest On return, points to the action requested= by the + callback function. + @retval EFI_SUCCESS The callback successfully handled the act= ion. + @retval EFI_OUT_OF_RESOURCES Not enough storage is available to hold t= he + variable and its data. + @retval EFI_DEVICE_ERROR The variable could not be saved. + @retval EFI_UNSUPPORTED The specified Action is not supported by = the + callback. +**/ +EFI_STATUS +EFIAPI +DriverCallback ( + IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This, + IN EFI_BROWSER_ACTION Action, + IN EFI_QUESTION_ID QuestionId, + IN UINT8 Type, + IN EFI_IFR_TYPE_VALUE *Value, + OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest + ) +{ + SCREEN_PRIVATE_DATA *PrivateData; + EFI_STATUS Status; + + if (((Value =3D=3D NULL) && + (Action !=3D EFI_BROWSER_ACTION_FORM_OPEN) && + (Action !=3D EFI_BROWSER_ACTION_FORM_CLOSE)) || + (ActionRequest =3D=3D NULL)) + { + return EFI_INVALID_PARAMETER; + } + + PrivateData =3D SCREEN_PRIVATE_FROM_THIS (This); + + Status =3D EFI_SUCCESS; + + switch (Action) { + case EFI_BROWSER_ACTION_FORM_OPEN: + break; + + case EFI_BROWSER_ACTION_FORM_CLOSE: + break; + + case EFI_BROWSER_ACTION_DEFAULT_STANDARD: + case EFI_BROWSER_ACTION_DEFAULT_MANUFACTURING: + if (QuestionId =3D=3D SMMU_PMU_ID) { + // + // SMMU PMU + // + Value->u32 =3D 0; + break; + } + + if (QuestionId =3D=3D STRONG_ORDERING_ID) { + // + // Strong Ordering + // + Value->u8 =3D STRONG_ORDERING_DEFAULT_OPTION_VALUE; + break; + } + + switch ((QuestionId - 0x8002) % MAX_EDITABLE_ELEMENTS) { + case 0: + Value->u8 =3D PcieRCActiveDefaultSetting ((QuestionId - 0x8002) / MA= X_EDITABLE_ELEMENTS, PrivateData); + break; + + case 1: + Value->u8 =3D PcieRCDevMapLowDefaultSetting ((QuestionId - 0x8002) /= MAX_EDITABLE_ELEMENTS, PrivateData); + break; + + case 2: + Value->u8 =3D PcieRCDevMapHighDefaultSetting ((QuestionId - 0x8002) = / MAX_EDITABLE_ELEMENTS, PrivateData); + break; + } + break; + + case EFI_BROWSER_ACTION_RETRIEVE: + case EFI_BROWSER_ACTION_CHANGING: + case EFI_BROWSER_ACTION_SUBMITTED: + break; + + default: + Status =3D EFI_UNSUPPORTED; + break; + } + + return Status; +} + +/** + This function return default settings for Dev Map Low. + + @param RootComplex RootComplex ID. + @param PrivateData Private data. + + @retval Default dev settings. +**/ +UINT8 +PcieRCDevMapLowDefaultSetting ( + IN UINTN RCIndex, + IN SCREEN_PRIVATE_DATA *PrivateData + ) +{ + AC01_ROOT_COMPLEX *RootComplex =3D GetRootComplex (RCIndex); + + return RootComplex->DefaultDevMapLow; +} + +/** + This function return default settings for Dev Map High. + + @param RootComplex RootComplex ID. + @param PrivateData Private data. + + @retval Default dev settings. +**/ +UINT8 +PcieRCDevMapHighDefaultSetting ( + IN UINTN RCIndex, + IN SCREEN_PRIVATE_DATA *PrivateData + ) +{ + AC01_ROOT_COMPLEX *RootComplex =3D GetRootComplex (RCIndex); + + return RootComplex->DefaultDevMapHigh; +} + +BOOLEAN +PcieRCActiveDefaultSetting ( + IN UINTN RCIndex, + IN SCREEN_PRIVATE_DATA *PrivateData + ) +{ + AC01_ROOT_COMPLEX *RootComplex =3D GetRootComplex (RCIndex); + + return RootComplex->DefaultActive; +} + +VOID * +CreateDevMapOptions ( + AC01_ROOT_COMPLEX *RootComplex + ) +{ + EFI_STRING_ID StringId; + VOID *OptionsOpCodeHandle; + + OptionsOpCodeHandle =3D HiiAllocateOpCodeHandle (); + ASSERT (OptionsOpCodeHandle !=3D NULL); + + StringId =3D RootComplex->Type =3D=3D RootComplexTypeA ? + STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE0) : + STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE4); + HiiCreateOneOfOptionOpCode ( + OptionsOpCodeHandle, + StringId, + 0, + EFI_IFR_NUMERIC_SIZE_1, + DevMapMode1 + ); + + StringId =3D RootComplex->Type =3D=3D RootComplexTypeA ? + STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE1) : + STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE5); + HiiCreateOneOfOptionOpCode ( + OptionsOpCodeHandle, + StringId, + 0, + EFI_IFR_NUMERIC_SIZE_1, + DevMapMode2 + ); + + StringId =3D RootComplex->Type =3D=3D RootComplexTypeA ? + STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE2) : + STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE6); + HiiCreateOneOfOptionOpCode ( + OptionsOpCodeHandle, + StringId, + 0, + EFI_IFR_NUMERIC_SIZE_1, + DevMapMode3 + ); + + StringId =3D RootComplex->Type =3D=3D RootComplexTypeA ? + STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE3) : + STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE7); + HiiCreateOneOfOptionOpCode ( + OptionsOpCodeHandle, + StringId, + 0, + EFI_IFR_NUMERIC_SIZE_1, + DevMapMode4 + ); + + return OptionsOpCodeHandle; +} + +/** + This function sets up the first elements of the form. + @param RootComplex RootComplex ID. + @param PrivateData Private data. + + @retval EFI_SUCCESS The form is set up successfully. +**/ +EFI_STATUS +PcieRCScreenSetup ( + IN UINTN RCIndex, + IN SCREEN_PRIVATE_DATA *PrivateData + ) +{ + AC01_ROOT_COMPLEX *RootComplex; + CHAR16 Str[MAX_STRING_SIZE]; + EFI_IFR_GUID_LABEL *EndLabel; + EFI_IFR_GUID_LABEL *StartLabel; + UINT16 BifurHiVarOffset; + UINT16 BifurLoVarOffset; + UINT16 DisabledStatusVarOffset; + UINT8 QuestionFlags, QuestionFlagsSubItem; + VOID *EndOpCodeHandle; + VOID *OptionsOpCodeHandle; + VOID *StartOpCodeHandle; + + RootComplex =3D GetRootComplex (RCIndex); + + // Initialize the container for dynamic opcodes + StartOpCodeHandle =3D HiiAllocateOpCodeHandle (); + ASSERT (StartOpCodeHandle !=3D NULL); + EndOpCodeHandle =3D HiiAllocateOpCodeHandle (); + ASSERT (EndOpCodeHandle !=3D NULL); + + // Create Hii Extend Label OpCode as the start opcode + StartLabel =3D (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode ( + StartOpCodeHandle, + &gEfiIfrTianoGuid, + NULL, + sizeof (EFI_IFR_GUID_LABEL) + ); + StartLabel->ExtendOpCode =3D EFI_IFR_EXTEND_OP_LABEL; + StartLabel->Number =3D LABEL_RC0_UPDATE + 2 * RCIndex; + + // Create Hii Extend Label OpCode as the end opcode + EndLabel =3D (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode ( + EndOpCodeHandle, + &gEfiIfrTianoGuid, + NULL, + sizeof (EFI_IFR_GUID_LABEL) + ); + EndLabel->ExtendOpCode =3D EFI_IFR_EXTEND_OP_LABEL; + EndLabel->Number =3D LABEL_RC0_END + 2 * RCIndex; + + // Create textbox to show the socket number which current Root Complex b= elongs to + HiiCreateTextOpCode ( + StartOpCodeHandle, + STRING_TOKEN (STR_PCIE_SOCKET), + STRING_TOKEN (STR_PCIE_SOCKET_HELP), + HiiSetString ( + PrivateData->HiiHandle, + 0, + (RootComplex->Socket) ? L"1" : L"0", + NULL + ) + ); + + // Create textbox to show the Root Complex type + HiiCreateTextOpCode ( + StartOpCodeHandle, + STRING_TOKEN (STR_PCIE_RC_TYPE), + STRING_TOKEN (STR_PCIE_RC_TYPE_HELP), + HiiSetString ( + PrivateData->HiiHandle, + 0, + (RootComplex->Type =3D=3D RootComplexTypeA) ? L"Root Complex Type-A"= : L"Root Complex Type-B", + NULL + ) + ); + + UnicodeSPrint (Str, sizeof (Str), L"Root Complex #%2d", RCIndex); + + DisabledStatusVarOffset =3D (UINT16)RC0_STATUS_OFFSET + sizeof (BOOLEAN)= * RCIndex; + BifurLoVarOffset =3D (UINT16)RC0_BIFUR_LO_OFFSET + sizeof (UINT8) * RCIn= dex; + BifurHiVarOffset =3D (UINT16)RC0_BIFUR_HI_OFFSET + sizeof (UINT8) * RCIn= dex; + + QuestionFlags =3D EFI_IFR_FLAG_RESET_REQUIRED | EFI_IFR_FLAG_CALLBACK; + if (IsEmptyRC (RootComplex) + || (GetNumberOfActiveSockets () =3D=3D 1 && RootComplex->Socket =3D= =3D 1)) + { + // + // Do not allow changing if none of Root Port underneath enabled + // or slave Root Complex on 1P system. + // + QuestionFlags |=3D EFI_IFR_FLAG_READ_ONLY; + } + + // Create the Root Complex Disable checkbox + HiiCreateCheckBoxOpCode ( + StartOpCodeHandle, // Container for dynamic cre= ated opcodes + 0x8002 + MAX_EDITABLE_ELEMENTS * RCIndex, // QuestionId (or "key") + VARSTORE_ID, // VarStoreId + DisabledStatusVarOffset, // VarOffset in Buffer Stora= ge + HiiSetString ( + PrivateData->HiiHandle, + 0, + Str, + NULL + ), // Prompt + STRING_TOKEN (STR_PCIE_RC_STATUS_HELP), // Help + QuestionFlags, // QuestionFlags + 0, // CheckBoxFlags + NULL // DefaultsOpCodeHandle + ); + + if (RootComplex->Type =3D=3D RootComplexTypeA) { + // + // Create Option OpCode to display bifurcation for RootComplexTypeA + // + OptionsOpCodeHandle =3D CreateDevMapOptions (RootComplex); + + if (RootComplex->DefaultDevMapLow !=3D 0) { + QuestionFlags |=3D EFI_IFR_FLAG_READ_ONLY; + } + + HiiCreateOneOfOpCode ( + StartOpCodeHandle, // Container for dynamic c= reated opcodes + 0x8003 + MAX_EDITABLE_ELEMENTS * RCIndex, // Question ID (or call it= "key") + VARSTORE_ID, // VarStore ID + BifurLoVarOffset, // Offset in Buffer Storag= e + STRING_TOKEN (STR_PCIE_RCA_BIFUR), // Question prompt text + STRING_TOKEN (STR_PCIE_RCA_BIFUR_HELP), // Question help text + QuestionFlags, // Question flag + EFI_IFR_NUMERIC_SIZE_1, // Data type of Question V= alue + OptionsOpCodeHandle, // Option Opcode list + NULL // Default Opcode is NULl + ); + } else { + // + // Create Option OpCode to display bifurcation for RootComplexTypeB-Lo= w + // + OptionsOpCodeHandle =3D CreateDevMapOptions (RootComplex); + + QuestionFlagsSubItem =3D QuestionFlags; + if (RootComplex->DefaultDevMapLow !=3D 0) { + QuestionFlagsSubItem |=3D EFI_IFR_FLAG_READ_ONLY; + } + + HiiCreateOneOfOpCode ( + StartOpCodeHandle, // Container for dynamic = created opcodes + 0x8003 + MAX_EDITABLE_ELEMENTS * RCIndex, // Question ID (or call i= t "key") + VARSTORE_ID, // VarStore ID + BifurLoVarOffset, // Offset in Buffer Stora= ge + STRING_TOKEN (STR_PCIE_RCB_LO_BIFUR), // Question prompt text + STRING_TOKEN (STR_PCIE_RCB_LO_BIFUR_HELP), // Question help text + QuestionFlagsSubItem, // Question flag + EFI_IFR_NUMERIC_SIZE_1, // Data type of Question = Value + OptionsOpCodeHandle, // Option Opcode list + NULL // Default Opcode is NULl + ); + + // + // Create Option OpCode to display bifurcation for RootComplexTypeB-Hi= gh + // + OptionsOpCodeHandle =3D CreateDevMapOptions (RootComplex); + + QuestionFlagsSubItem =3D QuestionFlags; + if (RootComplex->DefaultDevMapHigh !=3D 0) { + QuestionFlagsSubItem |=3D EFI_IFR_FLAG_READ_ONLY; + } + + HiiCreateOneOfOpCode ( + StartOpCodeHandle, // Container for dynamic = created opcodes + 0x8004 + MAX_EDITABLE_ELEMENTS * RCIndex, // Question ID (or call i= t "key") + VARSTORE_ID, // VarStore ID + BifurHiVarOffset, // Offset in Buffer Stora= ge + STRING_TOKEN (STR_PCIE_RCB_HI_BIFUR), // Question prompt text + STRING_TOKEN (STR_PCIE_RCB_HI_BIFUR_HELP), // Question help text + QuestionFlagsSubItem, // Question flag + EFI_IFR_NUMERIC_SIZE_1, // Data type of Question = Value + OptionsOpCodeHandle, // Option Opcode list + NULL // Default Opcode is NULl + ); + } + + HiiUpdateForm ( + PrivateData->HiiHandle, // HII handle + &gPcieFormSetGuid, // Formset GUID + RC0_FORM_ID + RCIndex, // Form ID + StartOpCodeHandle, // Label for where to insert opcodes + EndOpCodeHandle // Insert data + ); + + HiiFreeOpCodeHandle (StartOpCodeHandle); + HiiFreeOpCodeHandle (EndOpCodeHandle); + + return EFI_SUCCESS; +} + +/** + This function sets up the first elements of the form. + + @param PrivateData Private data. + + @retval EFI_SUCCESS The form is set up successfully. +**/ +EFI_STATUS +PcieMainScreenSetup ( + IN SCREEN_PRIVATE_DATA *PrivateData + ) +{ + VOID *StartOpCodeHandle; + EFI_IFR_GUID_LABEL *StartLabel; + VOID *EndOpCodeHandle; + EFI_IFR_GUID_LABEL *EndLabel; + CHAR16 Str[MAX_STRING_SIZE]; + UINTN RootComplex; + SETUP_GOTO_DATA *GotoItem =3D NULL; + EFI_QUESTION_ID GotoId; + UINT8 QuestionFlags; + + // Initialize the container for dynamic opcodes + StartOpCodeHandle =3D HiiAllocateOpCodeHandle (); + ASSERT (StartOpCodeHandle !=3D NULL); + EndOpCodeHandle =3D HiiAllocateOpCodeHandle (); + ASSERT (EndOpCodeHandle !=3D NULL); + + // Create Hii Extend Label OpCode as the start opcode + StartLabel =3D (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode ( + StartOpCodeHandle, + &gEfiIfrTianoGuid, + NULL, + sizeof (EFI_IFR_GUID_LABEL) + ); + StartLabel->ExtendOpCode =3D EFI_IFR_EXTEND_OP_LABEL; + StartLabel->Number =3D LABEL_UPDATE; + + // Create Hii Extend Label OpCode as the end opcode + EndLabel =3D (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode ( + EndOpCodeHandle, + &gEfiIfrTianoGuid, + NULL, + sizeof (EFI_IFR_GUID_LABEL) + ); + EndLabel->ExtendOpCode =3D EFI_IFR_EXTEND_OP_LABEL; + EndLabel->Number =3D LABEL_END; + + QuestionFlags =3D EFI_IFR_FLAG_CALLBACK | EFI_IFR_FLAG_RESET_REQUIRED; + + HiiCreateCheckBoxOpCode ( + StartOpCodeHandle, // Container for dynamic crea= ted opcodes + SMMU_PMU_ID, // Question ID + VARSTORE_ID, // VarStore ID + (UINT16)SMMU_PMU_OFFSET, // Offset in Buffer Storage + STRING_TOKEN (STR_PCIE_SMMU_PMU_PROMPT), // Question prompt text + STRING_TOKEN (STR_PCIE_SMMU_PMU_HELP), // Question help text + QuestionFlags, + 0, + NULL + ); + + if (mReadOnlyStrongOrdering) { + QuestionFlags |=3D EFI_IFR_FLAG_READ_ONLY; + } + + HiiCreateCheckBoxOpCode ( + StartOpCodeHandle, // Container for dynam= ic created opcodes + STRONG_ORDERING_ID, // Question ID + NVPARAM_VARSTORE_ID, // VarStore ID + (UINT16)STRONG_ORDERING_OFFSET, // Offset in Buffer St= orage + STRING_TOKEN (STR_PCIE_STRONG_ORDERING_PROMPT), // Question prompt tex= t + STRING_TOKEN (STR_PCIE_STRONG_ORDERING_HELP), // Question help text + QuestionFlags, + STRONG_ORDERING_DEFAULT_OPTION_VALUE, + NULL + ); + + // + // Create the a seperated line + // + HiiCreateTextOpCode ( + StartOpCodeHandle, + STRING_TOKEN (STR_PCIE_FORM_SEPERATE_LINE), + STRING_TOKEN (STR_PCIE_FORM_SEPERATE_LINE), + STRING_TOKEN (STR_PCIE_FORM_SEPERATE_LINE) + ); + + // Create Goto form for each RootComplex + for (RootComplex =3D 0; RootComplex < AC01_PCIE_MAX_ROOT_COMPLEX; RootCo= mplex++) { + + GotoItem =3D AllocateZeroPool (sizeof (SETUP_GOTO_DATA)); + if (GotoItem =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + GotoItem->PciDevIdx =3D RootComplex; + + GotoId =3D GOTO_ID_BASE + (UINT16)RootComplex; + + // Update HII string + UnicodeSPrint (Str, sizeof (Str), L"Root Complex #%2d", RootComplex); + GotoItem->GotoStringId =3D HiiSetString ( + PrivateData->HiiHandle, + 0, + Str, + NULL + ); + GotoItem->GotoHelpStringId =3D STRING_TOKEN (STR_PCIE_GOTO_HELP); + GotoItem->ShowItem =3D TRUE; + + // Add goto control + HiiCreateGotoOpCode ( + StartOpCodeHandle, + RC0_FORM_ID + RootComplex, + GotoItem->GotoStringId, + GotoItem->GotoHelpStringId, + EFI_IFR_FLAG_CALLBACK, + GotoId + ); + } + + HiiUpdateForm ( + PrivateData->HiiHandle, // HII handle + &gPcieFormSetGuid, // Formset GUID + FORM_ID, // Form ID + StartOpCodeHandle, // Label for where to insert opcodes + EndOpCodeHandle // Insert data + ); + + HiiFreeOpCodeHandle (StartOpCodeHandle); + HiiFreeOpCodeHandle (EndOpCodeHandle); + + return EFI_SUCCESS; +} + +VOID +NVParamVarstoreInit ( + VOID + ) +{ + BOOLEAN BoardSettingValid; + BOOLEAN UserSettingValid; + BOOLEAN Update; + EFI_STATUS Status; + UINT32 UserValue; + UINT32 InitValue; + + mReadOnlyStrongOrdering =3D FALSE; + + // S0 + UserSettingValid =3D FALSE; + Status =3D NVParamGet ( + NV_SI_MESH_S0_CXG_RC_STRONG_ORDERING_EN, + NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC, + &UserValue + ); + if (!EFI_ERROR (Status)) { + UserSettingValid =3D TRUE; + } + + // + // InitValue will be default value or board setting value. + // + BoardSettingValid =3D FALSE; + Status =3D NVParamGet ( + NV_SI_RO_BOARD_MESH_S0_CXG_RC_STRONG_ORDERING_EN, + NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC, + &InitValue + ); + if (!EFI_ERROR (Status) && InitValue > 0) { + BoardSettingValid =3D TRUE; + mReadOnlyStrongOrdering =3D TRUE; + } else { + InitValue =3D STRONG_ORDERING_DEFAULT_NVPARAM_VALUE; + } + + Update =3D TRUE; + if ((UserSettingValid && (UserValue =3D=3D InitValue)) + || (!BoardSettingValid && UserSettingValid && (UserValue =3D=3D 0)))= { + Update =3D FALSE; + } + + if (Update) { + Status =3D NVParamSet ( + NV_SI_MESH_S0_CXG_RC_STRONG_ORDERING_EN, + NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC, + NV_PERM_BIOS | NV_PERM_MANU, + InitValue + ); + ASSERT_EFI_ERROR (Status); + } + + // + // No need to check slave present. + // + UserSettingValid =3D FALSE; + Status =3D NVParamGet ( + NV_SI_MESH_S1_CXG_RC_STRONG_ORDERING_EN, + NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC, + &UserValue + ); + if (!EFI_ERROR (Status)) { + UserSettingValid =3D TRUE; + } + + // + // InitValue will be default value or board setting value. + // + BoardSettingValid =3D FALSE; + Status =3D NVParamGet ( + NV_SI_RO_BOARD_MESH_S1_CXG_RC_STRONG_ORDERING_EN, + NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC, + &InitValue + ); + if (!EFI_ERROR (Status) && InitValue > 0) { + BoardSettingValid =3D TRUE; + mReadOnlyStrongOrdering =3D TRUE; + } else { + InitValue =3D STRONG_ORDERING_DEFAULT_NVPARAM_VALUE; + } + + Update =3D TRUE; + if ((UserSettingValid && (UserValue =3D=3D InitValue)) + || (!BoardSettingValid && UserSettingValid && (UserValue =3D=3D 0)))= { + Update =3D FALSE; + } + + if (Update) { + Status =3D NVParamSet ( + NV_SI_MESH_S1_CXG_RC_STRONG_ORDERING_EN, + NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC, + NV_PERM_BIOS | NV_PERM_MANU, + InitValue + ); + ASSERT_EFI_ERROR (Status); + } +} + +/** + Build PCIe menu screen. + + @retval EFI_SUCCESS The operation is successful. + + @retval Others An error occurred. +**/ +EFI_STATUS +EFIAPI +RootComplexDriverEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + AC01_ROOT_COMPLEX *RootComplex; + BOOLEAN IsUpdated; + EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL *HiiKeywordHandler; + EFI_HANDLE DriverHandle; + EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting; + EFI_HII_DATABASE_PROTOCOL *HiiDatabase; + EFI_HII_HANDLE HiiHandle; + EFI_HII_STRING_PROTOCOL *HiiString; + EFI_STATUS Status; + ROOT_COMPLEX_CONFIG_VARSTORE_DATA *VarStoreConfig; + UINT8 RCIndex; + UINTN BufferSize; + + // + // Initialize driver private data + // + mPrivateData =3D AllocateZeroPool (sizeof (SCREEN_PRIVATE_DATA)); + if (mPrivateData =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + mPrivateData->Signature =3D SCREEN_PRIVATE_DATA_SIGNATURE; + mPrivateData->ConfigAccess.ExtractConfig =3D ExtractConfig; + mPrivateData->ConfigAccess.RouteConfig =3D RouteConfig; + mPrivateData->ConfigAccess.Callback =3D DriverCallback; + + // + // Locate Hii Database protocol + // + Status =3D gBS->LocateProtocol ( + &gEfiHiiDatabaseProtocolGuid, + NULL, + (VOID **)&HiiDatabase + ); + if (EFI_ERROR (Status)) { + return Status; + } + mPrivateData->HiiDatabase =3D HiiDatabase; + + // + // Locate HiiString protocol + // + Status =3D gBS->LocateProtocol ( + &gEfiHiiStringProtocolGuid, + NULL, + (VOID **)&HiiString + ); + if (EFI_ERROR (Status)) { + return Status; + } + mPrivateData->HiiString =3D HiiString; + + // + // Locate ConfigRouting protocol + // + Status =3D gBS->LocateProtocol ( + &gEfiHiiConfigRoutingProtocolGuid, + NULL, + (VOID **)&HiiConfigRouting + ); + if (EFI_ERROR (Status)) { + return Status; + } + mPrivateData->HiiConfigRouting =3D HiiConfigRouting; + + // + // Locate keyword handler protocol + // + Status =3D gBS->LocateProtocol ( + &gEfiConfigKeywordHandlerProtocolGuid, + NULL, + (VOID **)&HiiKeywordHandler + ); + if (EFI_ERROR (Status)) { + return Status; + } + mPrivateData->HiiKeywordHandler =3D HiiKeywordHandler; + + DriverHandle =3D NULL; + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &DriverHandle, + &gEfiDevicePathProtocolGuid, + &mHiiVendorDevicePath, + &gEfiHiiConfigAccessProtocolGuid, + &mPrivateData->ConfigAccess, + NULL + ); + ASSERT_EFI_ERROR (Status); + + mPrivateData->DriverHandle =3D DriverHandle; + + // + // Publish our HII data + // + HiiHandle =3D HiiAddPackages ( + &gPcieFormSetGuid, + DriverHandle, + RootComplexConfigDxeStrings, + RootComplexConfigVfrBin, + NULL + ); + if (HiiHandle =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + mPrivateData->HiiHandle =3D HiiHandle; + + // + // Initialize NVParam varstore configuration data + // + NVParamVarstoreInit (); + + // + // Initialize efi varstore configuration data + // + VarStoreConfig =3D &mPrivateData->VarStoreConfig; + ZeroMem (VarStoreConfig, sizeof (ROOT_COMPLEX_CONFIG_VARSTORE_DATA)); + + // Get Buffer Storage data from EFI variable + BufferSize =3D sizeof (ROOT_COMPLEX_CONFIG_VARSTORE_DATA); + Status =3D gRT->GetVariable ( + gPcieVarstoreName, + &gPcieFormSetGuid, + NULL, + &BufferSize, + VarStoreConfig + ); + + IsUpdated =3D FALSE; + + if (EFI_ERROR (Status)) { + VarStoreConfig->SmmuPmu =3D 0; /* Disable by default */ + IsUpdated =3D TRUE; + } + // Update board settings to menu + for (RCIndex =3D 0; RCIndex < AC01_PCIE_MAX_ROOT_COMPLEX; RCIndex++) { + RootComplex =3D GetRootComplex (RCIndex); + + if (EFI_ERROR (Status)) { + VarStoreConfig->RCBifurcationLow[RCIndex] =3D RootComplex->DevMapLow= ; + VarStoreConfig->RCBifurcationHigh[RCIndex] =3D RootComplex->DevMapHi= gh; + VarStoreConfig->RCStatus[RCIndex] =3D RootComplex->Active; + IsUpdated =3D TRUE; + } + } + + if (IsUpdated) { + // Update Buffer Storage + Status =3D gRT->SetVariable ( + gPcieVarstoreName, + &gPcieFormSetGuid, + EFI_VARIABLE_NON_VOLATILE | + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS, + sizeof (ROOT_COMPLEX_CONFIG_VARSTORE_DATA), + VarStoreConfig + ); + if (EFI_ERROR (Status)) { + return Status; + } + } + Status =3D PcieMainScreenSetup (mPrivateData); + ASSERT_EFI_ERROR (Status); + + for (RCIndex =3D 0; RCIndex < AC01_PCIE_MAX_ROOT_COMPLEX; RCIndex++) { + Status =3D PcieRCScreenSetup (RCIndex, mPrivateData); + ASSERT_EFI_ERROR (Status); + } + + return Status; +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/Roo= tComplexConfigDxe.uni b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexCo= nfigDxe/RootComplexConfigDxe.uni new file mode 100644 index 000000000000..f28fda05def9 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComple= xConfigDxe.uni @@ -0,0 +1,102 @@ +// +// Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// + +#langdef en-US "English" + +#string STR_PCIE_FORM #language en-US "PCIe Root Complex= Configuration" +#string STR_PCIE_FORM_HELP #language en-US "Configure Root Co= mplex" + +#string STR_PCIE_FORM_SEPERATE_LINE #language en-US "" + +///// + +#string STR_PCIE_GOTO #language en-US "" +#string STR_PCIE_GOTO_HELP #language en-US "Change On Board R= oot Complex Settings." + +#string STR_PCIE_RC_STATUS #language en-US "" +#string STR_PCIE_RC_STATUS_HELP #language en-US "Enable / Disable = Root Complex" + +#string STR_PCIE_RCA_BIFUR #language en-US "Bifurcation x16" +#string STR_PCIE_RCA_BIFUR_HELP #language en-US "Set bifurcation m= ode for x16 Root Complex Type-A" + +#string STR_PCIE_RCB_LO_BIFUR #language en-US "Bifurcation 1st x= 8" +#string STR_PCIE_RCB_LO_BIFUR_HELP #language en-US "Set bifurcation m= ode for 1st x8 Root Complex Type-B" + +#string STR_PCIE_RCB_HI_BIFUR #language en-US "Bifurcation 2nd x= 8" +#string STR_PCIE_RCB_HI_BIFUR_HELP #language en-US "Set bifurcation m= ode for 2nd x8 Root Complex Type-B" + +///// + +#string STR_PCIE_RC0_FORM #language en-US "Root Complex 0 Co= nfiguration" +#string STR_PCIE_RC0_FORM_HELP #language en-US "Root Complex 0 Co= nfiguration" + +#string STR_PCIE_RC1_FORM #language en-US "Root Complex 1 Co= nfiguration" +#string STR_PCIE_RC1_FORM_HELP #language en-US "Root Complex 1 Co= nfiguration" + +#string STR_PCIE_RC2_FORM #language en-US "Root Complex 2 Co= nfiguration" +#string STR_PCIE_RC2_FORM_HELP #language en-US "Root Complex 2 Co= nfiguration" + +#string STR_PCIE_RC3_FORM #language en-US "Root Complex 3 Co= nfiguration" +#string STR_PCIE_RC3_FORM_HELP #language en-US "Root Complex 3 Co= nfiguration" + +#string STR_PCIE_RC4_FORM #language en-US "Root Complex 4 Co= nfiguration" +#string STR_PCIE_RC4_FORM_HELP #language en-US "Root Complex 4 Co= nfiguration" + +#string STR_PCIE_RC5_FORM #language en-US "Root Complex 5 Co= nfiguration" +#string STR_PCIE_RC5_FORM_HELP #language en-US "Root Complex 5 Co= nfiguration" + +#string STR_PCIE_RC6_FORM #language en-US "Root Complex 6 Co= nfiguration" +#string STR_PCIE_RC6_FORM_HELP #language en-US "Root Complex 6 Co= nfiguration" + +#string STR_PCIE_RC7_FORM #language en-US "Root Complex 7 Co= nfiguration" +#string STR_PCIE_RC7_FORM_HELP #language en-US "Root Complex 7 Co= nfiguration" + +#string STR_PCIE_RC8_FORM #language en-US "Root Complex 8 Co= nfiguration" +#string STR_PCIE_RC8_FORM_HELP #language en-US "Root Complex 8 Co= nfiguration" + +#string STR_PCIE_RC9_FORM #language en-US "Root Complex 9 Co= nfiguration" +#string STR_PCIE_RC9_FORM_HELP #language en-US "Root Complex 9 Co= nfiguration" + +#string STR_PCIE_RC10_FORM #language en-US "Root Complex 10 C= onfiguration" +#string STR_PCIE_RC10_FORM_HELP #language en-US "Root Complex 10 C= onfiguration" + +#string STR_PCIE_RC11_FORM #language en-US "Root Complex 11 C= onfiguration" +#string STR_PCIE_RC11_FORM_HELP #language en-US "Root Complex 11 C= onfiguration" + +#string STR_PCIE_RC12_FORM #language en-US "Root Complex 12 C= onfiguration" +#string STR_PCIE_RC12_FORM_HELP #language en-US "Root Complex 12 C= onfiguration" + +#string STR_PCIE_RC13_FORM #language en-US "Root Complex 13 C= onfiguration" +#string STR_PCIE_RC13_FORM_HELP #language en-US "Root Complex 13 C= onfiguration" + +#string STR_PCIE_RC14_FORM #language en-US "Root Complex 14 C= onfiguration" +#string STR_PCIE_RC14_FORM_HELP #language en-US "Root Complex 14 C= onfiguration" + +#string STR_PCIE_RC15_FORM #language en-US "Root Complex 15 C= onfiguration" +#string STR_PCIE_RC15_FORM_HELP #language en-US "Root Complex 15 C= onfiguration" + +#string STR_PCIE_BIFUR_SELECT_VALUE0 #language en-US "x16" +#string STR_PCIE_BIFUR_SELECT_VALUE1 #language en-US "x8+x8" +#string STR_PCIE_BIFUR_SELECT_VALUE2 #language en-US "x8+x4+x4" +#string STR_PCIE_BIFUR_SELECT_VALUE3 #language en-US "x4+x4+x4+x4" +#string STR_PCIE_BIFUR_SELECT_VALUE4 #language en-US "x8" +#string STR_PCIE_BIFUR_SELECT_VALUE5 #language en-US "x4+x4" +#string STR_PCIE_BIFUR_SELECT_VALUE6 #language en-US "x4+x2+x2" +#string STR_PCIE_BIFUR_SELECT_VALUE7 #language en-US "x2+x2+x2+x2" + +#string STR_PCIE_SOCKET #language en-US "Socket" +#string STR_PCIE_SOCKET_HELP #language en-US "Socket 0 - Master= ; Socket 1 - Slave" +#string STR_PCIE_SOCKET_VALUE #language en-US "" + +#string STR_PCIE_RC_TYPE #language en-US "Type" +#string STR_PCIE_RC_TYPE_HELP #language en-US "Type-A: x16 lanes= bifurcated down to x4; Type-B: 2 of x8 lanes, each bifurcated down to x2" +#string STR_PCIE_RC_TYPE_VALUE #language en-US "" + +#string STR_PCIE_SMMU_PMU_PROMPT #language en-US "SMMU Pmu" +#string STR_PCIE_SMMU_PMU_HELP #language en-US "Enable/Disable PM= U feature for SMMU" + +#string STR_PCIE_STRONG_ORDERING_PROMPT #language en-US "PCIe Strong Order= ing" +#string STR_PCIE_STRONG_ORDERING_HELP #language en-US "Enable/disable PC= Ie Strong Ordering with internal bus" --=20 2.17.1