[PATCH] MdeModulePkg\UfsBlockIoPei: UFS MMIO address size support both 32/64 bit

[ian.chiu@intel.com]

From: Ian Chiu <Ian.chiu@intel.com>

https://bugzilla.tianocore.org/show_bug.cgi?id=3703
MMIO base address size will overflow while finding two or more Host
controller in the system. Correct it and support 32 and 64 bits address
space.

Signed-off-by: Ian Chiu <ian.chiu@intel.com>
Cc: Maggie Chu <maggie.chu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
---
 MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c | 37 ++++++++++++++++++++++++--
 1 file changed, 35 insertions(+), 2 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c b/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c
index 447a05b5b2..69a19c60a2 100644
--- a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c
+++ b/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c
@@ -76,6 +76,7 @@ InitializeUfsHcPeim (
   UINT16                   Device;
   UINT16                   Function;
   UINT32                   Size;
+  UINT64                   MmioSize;
   UINT8                    SubClass;
   UINT8                    BaseClass;
   UFS_HC_PEI_PRIVATE_DATA  *Private;
@@ -119,16 +120,48 @@ InitializeUfsHcPeim (
           PciAnd16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (UINT16)~(EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));
           PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET), 0xFFFFFFFF);
           Size = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET));
+
+          switch (Size & 0x07) {
+            case 0x0:
+              //
+              // Memory space: anywhere in 32 bit address space
+              //
+              MmioSize = (~(Size & 0xFFFFFFF0)) + 1;
+              break;
+            case 0x4:
+              //
+              // Memory space: anywhere in 64 bit address space
+              //
+              MmioSize = Size & 0xFFFFFFF0;
+
+              //
+              // Fix the length to support some spefic 64 bit BAR
+              //
+              Size |= ((UINT32)(-1) << HighBitSet32 (Size));
+
+              //
+              // Calculate the size of 64bit bar
+              //
+              MmioSize  |= LShiftU64 ((UINT64) Size, 32);
+              MmioSize  = (~(MmioSize)) + 1;
+              break;
+            default:
+              //
+              // Unknown BAR type
+              //
+              ASSERT (FALSE);
+              continue;
+          };
           //
           // Assign resource to the Ufs Pci host controller's MMIO BAR.
           // Enable the Ufs Pci host controller by setting BME and MSE bits of PCI_CMD register.
           //
-          PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET), (UINT32)(PcdGet32 (PcdUfsPciHostControllerMmioBase) + Size * Private->TotalUfsHcs));
+          PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET), (UINT32)(PcdGet32 (PcdUfsPciHostControllerMmioBase) + MmioSize * Private->TotalUfsHcs));
           PciOr16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));
           //
           // Record the allocated Mmio base address.
           //
-          Private->UfsHcPciAddr[Private->TotalUfsHcs] = PcdGet32 (PcdUfsPciHostControllerMmioBase) + Size * Private->TotalUfsHcs;
+          Private->UfsHcPciAddr[Private->TotalUfsHcs] = PcdGet32 (PcdUfsPciHostControllerMmioBase) + (UINTN) MmioSize * Private->TotalUfsHcs;
           Private->TotalUfsHcs++;
           ASSERT (Private->TotalUfsHcs < MAX_UFS_HCS);
         }
-- 
2.16.2.windows.1