From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) by mx.groups.io with SMTP id smtpd.web08.11352.1635250996173714733 for ; Tue, 26 Oct 2021 05:23:16 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20210112.gappssmtp.com header.s=20210112 header.b=zm+JI37o; spf=pass (domain: nuviainc.com, ip: 209.85.221.49, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f49.google.com with SMTP id d3so14743290wrh.8 for ; Tue, 26 Oct 2021 05:23:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20210112.gappssmtp.com; s=20210112; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=XoI5t5IN7UZP5ww61IhYELFv/MeW9opY0pcROH3l8Y0=; b=zm+JI37ogJNDIjeCmDPNcoI5eNQDM6fFpzdujVGiw8IFRc+VR9VdLSS57Srp7XOeQw IAUri6oc1i4Jq07uL97gwIsUN/+UUm+1HLv1iwOtIWjzsZNkRWL+2ukvvurS56bx7ozN 435rYm2z9Dy3YjoUlh3WEdDIZ5g+yze9PQtwjRfUwFqRlz601Oc4gphLwucGcafM8gM+ CE6/Gm0a7ZmGpGV8wY2XeWGvVgcx9Caju+BtGORgn90rMaSXD5uIcXT2/9Ey73rDNip9 bc50GEYSCnXy0grdM1S9AHs3OEUwYPi5GwyaUljLeKK4XReph+L9K0I8PSyGCISe+BzY gf2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=XoI5t5IN7UZP5ww61IhYELFv/MeW9opY0pcROH3l8Y0=; b=WxPpd1fcQM38T8oXY0C29tnt1UoWXJtwVZ/AFgvnEw8LXczQVHYlwcSVcVbBL8OLRp 5CV5y7BUKx7+h2+H8MRUmLL7f67rWEb5ITfOKfmFQOAxkdFSGtgJMOjqb/1iZp60Wx4P GLjEwIJ8RQqZ8Y41wy+QPTxlJcftlbQWPWPxIjl5b9GNID7gbLOp1djxKs/w7hFH4NyT 4zUTNkO/wVPDSFifolhYmxaoPNCKxSqkBcFb8GIYmUnwzLsylG3fQfkw8WbUz+sh6PxA 0E/WdCpGPXUAXwYi7Kd02ILM7FP8pnEbU35Ti6ulZ86XEIo8bpj8zvryUUcXi1pmSiOV 6uUw== X-Gm-Message-State: AOAM531ydb8OuuBvXxhzpjghatyB5wd1RhDa0bSeMdCUSF0VR/ejyKQy vxIuL/xq64g7xXdEFMfntvXLsg== X-Google-Smtp-Source: ABdhPJzAuat3wzwjUzN8BWV+vOflVBeftNYJZNhmk6jc2pVB/CfQ7bgOo6z6Y0rwBgaMZ3YAkKBZog== X-Received: by 2002:a5d:6b86:: with SMTP id n6mr19869625wrx.334.1635250994445; Tue, 26 Oct 2021 05:23:14 -0700 (PDT) Return-Path: Received: from leviathan (cpc92314-cmbg19-2-0-cust559.5-4.cable.virginm.net. [82.11.186.48]) by smtp.gmail.com with ESMTPSA id e18sm10113203wrv.44.2021.10.26.05.23.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Oct 2021 05:23:14 -0700 (PDT) Date: Tue, 26 Oct 2021 13:23:12 +0100 From: "Leif Lindholm" To: Nhi Pham Cc: devel@edk2.groups.io, patches@amperecomputing.com, vunguyen@os.amperecomputing.com, Thang Nguyen , Chuong Tran , Phong Vo , Michael D Kinney , Ard Biesheuvel , Nate DeSimone Subject: Re: [edk2-platforms][PATCH v4 11/31] AmpereAltraPkg: Add Root Complex HOB data structures Message-ID: <20211026122312.yqemaedhokr2h7tm@leviathan> References: <20211022061809.31087-1-nhi@os.amperecomputing.com> <20211022061809.31087-12-nhi@os.amperecomputing.com> MIME-Version: 1.0 In-Reply-To: <20211022061809.31087-12-nhi@os.amperecomputing.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Oct 22, 2021 at 13:17:49 +0700, Nhi Pham wrote: > From: Vu Nguyen > > Provide common data structures and macros which will be consumed by > various PCIe modules. > > Cc: Thang Nguyen > Cc: Chuong Tran > Cc: Phong Vo > Cc: Leif Lindholm > Cc: Michael D Kinney > Cc: Ard Biesheuvel > Cc: Nate DeSimone > > Signed-off-by: Nhi Pham Reviewed-by: Leif Lindholm > --- > Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec | 3 + > Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h | 140 ++++++++++++++++++++ > 2 files changed, 143 insertions(+) > > diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec > index c1226c296dad..e19925c68a0e 100644 > --- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec > +++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec > @@ -52,3 +52,6 @@ [Guids] > > ## Include/Guid/PlatformInfoHob.h > gPlatformInfoHobGuid = { 0x7f73e372, 0x7183, 0x4022, { 0xb3, 0x76, 0x78, 0x30, 0x32, 0x6d, 0x79, 0xb4 } } > + > + ## Include/Guid/RootComplexInfoHob.h > + gRootComplexInfoHobGuid = { 0x568a258a, 0xcaa1, 0x47e9, { 0xbb, 0x89, 0x65, 0xa3, 0x73, 0x9b, 0x58, 0x75 } } > diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h > new file mode 100644 > index 000000000000..89da1ac696a5 > --- /dev/null > +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h > @@ -0,0 +1,140 @@ > +/** @file > + > + Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef ROOT_COMPLEX_INFO_HOB_H_ > +#define ROOT_COMPLEX_INFO_HOB_H_ > + > +#define ROOT_COMPLEX_INFO_HOB_GUID \ > + { 0x568a258a, 0xcaa1, 0x47e9, { 0xbb, 0x89, 0x65, 0xa3, 0x73, 0x9b, 0x58, 0x75 } } > + > +extern GUID gRootComplexInfoHobGuid; > + > +#define PRESET_INVALID 0xFF > + > +// > +// PCIe link width > +// > +#define LINK_WIDTH_NONE 0x00 > +#define LINK_WIDTH_X1 0x01 > +#define LINK_WIDTH_X2 0x02 > +#define LINK_WIDTH_X4 0x04 > +#define LINK_WIDTH_X8 0x08 > +#define LINK_WIDTH_X16 0x10 > + > +// > +// PCIe link speed > +// > +#define LINK_SPEED_NONE 0x00 > +#define LINK_SPEED_GEN1 0x01 > +#define LINK_SPEED_GEN2 0x02 > +#define LINK_SPEED_GEN3 0x04 > +#define LINK_SPEED_GEN4 0x08 > + > +typedef enum { > + DevMapMode1 = 0, > + DevMapMode2, > + DevMapMode3, > + DevMapMode4, > + MaxDevMapMode = DevMapMode4 > +} DEV_MAP_MODE; > + > +// > +// PCIe controller index > +// > +typedef enum { > + PcieController0 = 0, > + PcieController1, > + PcieController2, > + PcieController3, > + PcieController4, > + MaxPcieControllerA = PcieController4, > + PcieController5, > + PcieController6, > + PcieController7, > + MaxPcieController, > + MaxPcieControllerB = MaxPcieController > +} AC01_PCIE_CONTROLLER_INDEX; > + > +// > +// Root Complex type > +// > +typedef enum { > + RootComplexTypeA, > + RootComplexTypeB, > + MaxRootComplexType = RootComplexTypeB > +} AC01_ROOT_COMPLEX_TYPE; > + > +// > +// Root Complex index > +// > +typedef enum { > + RootComplexA0 = 0, > + RootComplexA1, > + RootComplexA2, > + RootComplexA3, > + MaxRootComplexA, > + RootComplexB0 = MaxRootComplexA, > + RootComplexB1, > + RootComplexB2, > + RootComplexB3, > + MaxRootComplex, > + MaxRootComplexB = MaxRootComplex > +} AC01_ROOT_COMPLEX_INDEX; > + > +#pragma pack(1) > + > +// > +// Data structure to store the PCIe controller information > +// > +typedef struct { > + PHYSICAL_ADDRESS CsrBase; // Base address of CSR block > + PHYSICAL_ADDRESS SnpsRamBase; // Base address of Synopsys SRAM > + UINT8 MaxGen; // Max speed Gen-1/-2/-3/-4 > + UINT8 CurrentGen; // Current speed Gen-1/-2/-3/-4 > + UINT8 MaxWidth; // Max lanes x2/x4/x8/x16 > + UINT8 CurWidth; // Current lanes x2/x4/x8/x16 > + UINT8 ID; // ID of the controller within Root Complex > + UINT8 DevNum; // Device number as part of Bus:Dev:Func > + BOOLEAN Active; // Active? Used in bi-furcation mode > + BOOLEAN LinkUp; // PHY and PCIE linkup > + BOOLEAN HotPlug; // Hotplug support > +} AC01_PCIE_CONTROLLER; > + > +// > +// Data structure to store the Root Complex information > +// > +typedef struct { > + PHYSICAL_ADDRESS CsrBase; > + PHYSICAL_ADDRESS TcuBase; > + PHYSICAL_ADDRESS HostBridgeBase; > + PHYSICAL_ADDRESS SerdesBase; > + PHYSICAL_ADDRESS MmcfgBase; > + PHYSICAL_ADDRESS MmioBase; > + PHYSICAL_ADDRESS MmioSize; > + PHYSICAL_ADDRESS Mmio32Base; > + PHYSICAL_ADDRESS Mmio32Size; > + AC01_PCIE_CONTROLLER Pcie[MaxPcieController]; > + UINT8 MaxPcieController; > + AC01_ROOT_COMPLEX_TYPE Type; > + UINT8 ID; > + DEV_MAP_MODE DevMapHigh:3; // Copy of High Devmap programmed to Host bridge > + DEV_MAP_MODE DevMapLow:3; // Copy of Low Devmap programmed to Host bridge > + DEV_MAP_MODE DefaultDevMapHigh:3; // Default of High devmap based on board settings > + DEV_MAP_MODE DefaultDevMapLow:3; // Default of Low devmap based on board settings > + UINT8 Socket; > + BOOLEAN Active; > + BOOLEAN DefaultActive; > + UINT16 Logical; > + UINT32 Flags; > + UINT8 PresetGen3[MaxPcieController]; > + UINT8 PresetGen4[MaxPcieController]; > +} AC01_ROOT_COMPLEX; > + > +#pragma pack() > + > +#endif /* ROOT_COMPLEX_INFO_HOB_H_ */ > -- > 2.17.1 >