From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) by mx.groups.io with SMTP id smtpd.web08.11609.1635252421516203727 for ; Tue, 26 Oct 2021 05:47:01 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20210112.gappssmtp.com header.s=20210112 header.b=YEvFquS4; spf=pass (domain: nuviainc.com, ip: 209.85.128.42, mailfrom: leif@nuviainc.com) Received: by mail-wm1-f42.google.com with SMTP id 131-20020a1c0489000000b0032cca9883b5so1713196wme.0 for ; Tue, 26 Oct 2021 05:47:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20210112.gappssmtp.com; s=20210112; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=MaKstNBdqbbG7B9Num+2tDuIZUYtFzMNZexwQld5hHA=; b=YEvFquS4Itmxg6r4Tn4J+iSk/rqqMsb8+tZEl4fLc3269QWUcOd0IWPtqiPU/Na3g0 rRaIaTRpE8vzvIiOOypeqEeqNdSD6pXG9JxR3p4rzctG1l1PT8daVsNLPTpgWGvlkmoi lBy1c94/0uFWsAyfSlW/whP22ANtg++CQ3gK7agN4E/1V1vlpHY6ZEmWq3SmsI6wVMtd 5hk8hNzooW05a26cwGN1CTlQyyl2kdEAn+PR9Iy8zcNFNzdoNwBSOK+zEwEHJWCsDEHh tJIpuT1B8NeOTUtSuL+D8hMiEFav4xveRr7YEWfnfHGx3b8XO2GES4jWYQI83jwfQ3M5 fgTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=MaKstNBdqbbG7B9Num+2tDuIZUYtFzMNZexwQld5hHA=; b=fy5AuSqATKpscuItncTciDGxF+1ykp1ArvgTJUFInqR44Ng6tZwLI2lHgYBS5PLATS zSq0qDVWvNmdTeLuWSFiKoBJd//o4Dj1ggTSsT6GBXvTgKIOon0a0bgfabH9TiGmBsMv aciTGKH+Am+i6Y1Ww8CGU8EkjfeaJxoYKQ9zNe3Ii7whZYx91Z4+nGq21/1yGOeMTN8m EADhrao8NowukHgXXv/wmgMSw7XsxyPywX2q9XV09jQUhC5zAUEd297d+8eOQ6dZVnVU MpuUFTHbW2lmrkxw7af+91CgteXmm5sF/l1owtjjpmFDYYiE516JLlt/WF3er2gyRW/d 1RXg== X-Gm-Message-State: AOAM533LjvS2Yc8l5+s+UjrnJogQxZ8xVm5hsWVO42AEwOe6IqF0uGS6 feySKY64ESWxhMwucb5zGaxpaQ== X-Google-Smtp-Source: ABdhPJzkPXTWy+7vD1QU+JoC+coWHf3hQ51sUhmhHApfz5mfQG1QxH2GaUlRu+c8ub9S6lU4/Aum6w== X-Received: by 2002:a7b:cb82:: with SMTP id m2mr21461678wmi.11.1635252420130; Tue, 26 Oct 2021 05:47:00 -0700 (PDT) Return-Path: Received: from leviathan (cpc92314-cmbg19-2-0-cust559.5-4.cable.virginm.net. [82.11.186.48]) by smtp.gmail.com with ESMTPSA id l5sm19146476wru.24.2021.10.26.05.46.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Oct 2021 05:46:59 -0700 (PDT) Date: Tue, 26 Oct 2021 13:46:58 +0100 From: "Leif Lindholm" To: Nhi Pham Cc: devel@edk2.groups.io, patches@amperecomputing.com, vunguyen@os.amperecomputing.com, Thang Nguyen , Chuong Tran , Phong Vo , Michael D Kinney , Ard Biesheuvel , Nate DeSimone Subject: Re: [edk2-platforms][PATCH v4 13/31] JadePkg: Add BoardPcieLib library instance Message-ID: <20211026124658.ma5uimpxmaadzx6t@leviathan> References: <20211022061809.31087-1-nhi@os.amperecomputing.com> <20211022061809.31087-14-nhi@os.amperecomputing.com> MIME-Version: 1.0 In-Reply-To: <20211022061809.31087-14-nhi@os.amperecomputing.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Oct 22, 2021 at 13:17:51 +0700, Nhi Pham wrote: > From: Vu Nguyen > > Provide Mt. Jade specific segment number for each Root Complex and > function to handle the PCIe PERST. > > Cc: Thang Nguyen > Cc: Chuong Tran > Cc: Phong Vo > Cc: Leif Lindholm > Cc: Michael D Kinney > Cc: Ard Biesheuvel > Cc: Nate DeSimone > > Signed-off-by: Nhi Pham > --- > Platform/Ampere/JadePkg/Jade.dsc | 2 +- > Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcieLib.inf | 27 +++++ > Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcieLib.c | 115 ++++++++++++++++++++ > 3 files changed, 143 insertions(+), 1 deletion(-) > > diff --git a/Platform/Ampere/JadePkg/Jade.dsc b/Platform/Ampere/JadePkg/Jade.dsc > index 23a297d0dbeb..9315c1c71cc7 100644 > --- a/Platform/Ampere/JadePkg/Jade.dsc > +++ b/Platform/Ampere/JadePkg/Jade.dsc > @@ -85,7 +85,7 @@ [LibraryClasses] > # > # Pcie Board > # > - BoardPcieLib|Silicon/Ampere/AmpereAltraPkg/Library/BoardPcieLibNull/BoardPcieLibNull.inf > + BoardPcieLib|Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcieLib.inf > > ################################################################################ > # > diff --git a/Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcieLib.inf b/Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcieLib.inf > new file mode 100644 > index 000000000000..1d722bceff2c > --- /dev/null > +++ b/Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcieLib.inf > @@ -0,0 +1,27 @@ > +## @file > +# > +# Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION = 0x0001001B > + BASE_NAME = BoardPcieLib > + FILE_GUID = 062191A6-E113-4FD6-84C7-E400B4B34759 > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = BoardPcieLib > + > +[Sources] > + BoardPcieLib.c > + > +[Packages] > + MdePkg/MdePkg.dec > + Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec > + > +[LibraryClasses] > + DebugLib > + GpioLib > + TimerLib > diff --git a/Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcieLib.c b/Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcieLib.c > new file mode 100644 > index 000000000000..4a9da7eeb4fe > --- /dev/null > +++ b/Platform/Ampere/JadePkg/Library/BoardPcieLib/BoardPcieLib.c > @@ -0,0 +1,115 @@ > +/** @file > + Pcie board specific driver to handle asserting PERST signal to Endpoint > + card. PERST asserting is via group of GPIO pins to CPLD as Platform Specification. > + > + Copyright (c) 2020 - 2021, Ampere Computing LLC. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > + > +#include > +#include > +#include > +#include > +#include > + > +#define RCA_MAX_PERST_GROUPVAL 62 > +#define RCB_MAX_PERST_GROUPVAL 46 > + > +VOID > +BoardPcieReleaseAllPerst ( > + IN UINT8 SocketId > + ) > +{ > + UINT32 GpioIndex, GpioPin; > + > + // Write 1 to all GPIO[16..21] to release all PERST > + GpioPin = AC01_GPIO_PINS_PER_SOCKET * SocketId + 16; > + for (GpioIndex = 0; GpioIndex < 6; GpioIndex++) { > + GpioModeConfig (GpioPin + GpioIndex, GpioConfigOutHigh); > + } > +} > + > +/** > + Assert PERST of PCIe controller > + > + @param[in] RootComplex Root Complex instance. > + @param[in] PcieIndex PCIe controller index of input Root Complex. > + @param[in] IsPullToHigh Target status for the PERST. > + > + @retval RETURN_SUCCESS The operation is successful. > + @retval Others An error occurred. > +**/ > +RETURN_STATUS > +EFIAPI > +BoardPcieAssertPerst ( > + IN AC01_ROOT_COMPLEX *RootComplex, > + IN UINT8 PcieIndex, > + IN BOOLEAN IsPullToHigh > + ) > +{ > + UINT32 GpioGroupVal, Val, GpioIndex, GpioPin; > + > + if (!IsPullToHigh) { > + if (RootComplex->Type == RootComplexTypeA) { > + // > + // RootComplexTypeA: RootComplex->ID: 0->3 ; PcieIndex: 0->3 > + // > + GpioGroupVal = RCA_MAX_PERST_GROUPVAL - RootComplex->ID * MaxPcieControllerA - PcieIndex; > + } else { > + // > + // RootComplexTypeB: RootComplex->ID: 4->7 ; PcieIndex: 0->7 > + // > + GpioGroupVal = RCB_MAX_PERST_GROUPVAL - (RootComplex->ID - MaxRootComplexA) * MaxPcieControllerB - PcieIndex; > + } > + > + // Update the value of GPIO[16..21]. Corresponding PERST line will be decoded by CPLD. > + GpioPin = AC01_GPIO_PINS_PER_SOCKET * RootComplex->Socket + 16; > + for (GpioIndex = 0; GpioIndex < 6; GpioIndex++) { > + Val = (GpioGroupVal & 0x3F) & (1 << GpioIndex); > + if (Val == 0) { > + GpioModeConfig (GpioPin + GpioIndex, GpioConfigOutLow); > + } else { > + GpioModeConfig (GpioPin + GpioIndex, GpioConfigOutHigh); > + } > + } > + > + // Keep reset as low as 100 ms as specification > + MicroSecondDelay (100 * 1000); > + } else { > + BoardPcieReleaseAllPerst (RootComplex->Socket); > + } > + > + return RETURN_SUCCESS; > +} > + > +/** > + Override the segment number for a root complex with a board specific number. > + > + @param[in] RootComplex Root Complex instance with properties. > + > + @retval Segment number corresponding to the input root complex. > + Default segment number is 0x0F. > +**/ > +UINT16 > +BoardPcieGetSegmentNumber ( > + IN AC01_ROOT_COMPLEX *RootComplex > + ) > +{ > + UINT8 Ac01BoardSegment[PLATFORM_CPU_MAX_SOCKET][AC01_PCIE_MAX_ROOT_COMPLEX] = > + { > + { 0x0C, 0x0D, 0x01, 0x00, 0x02, 0x03, 0x04, 0x05 }, > + { 0x10, 0x11, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B } > + }; > + > + if (RootComplex->Socket < PLATFORM_CPU_MAX_SOCKET > + && RootComplex->ID < AC01_PCIE_MAX_ROOT_COMPLEX) { > + return Ac01BoardSegment[RootComplex->Socket][RootComplex->ID]; > + } > + > + // Return default segment number > + return 0x0F; Macro. With that, Reviewed-by: Leif Lindholm > +} > -- > 2.17.1 >