From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) by mx.groups.io with SMTP id smtpd.web09.11585.1635253045475933307 for ; Tue, 26 Oct 2021 05:57:25 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20210112.gappssmtp.com header.s=20210112 header.b=6ymGw3Zg; spf=pass (domain: nuviainc.com, ip: 209.85.221.43, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f43.google.com with SMTP id s19so18981637wra.2 for ; Tue, 26 Oct 2021 05:57:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20210112.gappssmtp.com; s=20210112; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=SMCA836ZYQamEW3R7Z09KQzXksm5y6QQWsv1NYcfJMA=; b=6ymGw3ZgE2TZ70+zrgzAWu0PqJf9qyilpYbajTJZsmQN1Lm7FqMe2rFkv42CZTWqbV +G6KezNvBMMdm02x9/Du/A9K7lLGsunbtZXXH3SmcGtf+kAy9zvKIvErjA9TEpOXxeuy I0CUELG1kgnIrXysw4EG4k5qLfxwnb+q8WyRhXKiIE7fM5v0M+kIW9GswF/evA9MdlQc HhmdqS7akHDkelVXdGGVXGWhcz9NS7+mRuNb6aT5rbS8EN6vUPA8GRyFC36jntMblSYg jXqE5PKeR3ffcXxEDX7r+BY7WhTRcXDN+t9l/dj80t1Im6sPQQfwB4Xtd8ta2aly74qC JfRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=SMCA836ZYQamEW3R7Z09KQzXksm5y6QQWsv1NYcfJMA=; b=PirLZBdO5b92OmhUNil5c0hdKn1H12lQuotRbh2eSzVydR0TeJNLF99SJ87PYv3HGY oQctVEtkRfUuKZO4fPb6IoYUlFSt2SH6dvLSFH7pOwbmNK++SEHHdUDn3DYNA3j56fgi MFwWqbz9qRoMBN0Q/i8eoSpoHQeMVoKV3nxIRfswwMUUz9tbbnVNSPG4AVXI6bZFeuhy jWJrtcFJfuN2Wj6QoQPTHoM0rKyQgZdgjWfRlJO17tRYYCnGJ1sqtN36zJIAr3XBjKbJ G2wbGVjHJSXZufFMeAWmH1dtolGa6GZMesVy8JvZ+Ytba5KMsqzC0x7rFhDJWNVnwz1n H0Cw== X-Gm-Message-State: AOAM532Gqnac8wCyKPR+0U3my3ilhjlt+K8Psz8aKe/5M7bfGUvlDhqI v5YaPLIC+ryNmxJd8u0rdmbwLg== X-Google-Smtp-Source: ABdhPJzvCQWRS0QsWa0V0/ionffwz9yjUFkualYgmVRRpo1UlpCGcxWFmSbNhEoEj6hHvwaZ9NeXmQ== X-Received: by 2002:a5d:63ca:: with SMTP id c10mr33203942wrw.407.1635253044052; Tue, 26 Oct 2021 05:57:24 -0700 (PDT) Return-Path: Received: from leviathan (cpc92314-cmbg19-2-0-cust559.5-4.cable.virginm.net. [82.11.186.48]) by smtp.gmail.com with ESMTPSA id g77sm655475wmg.31.2021.10.26.05.57.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Oct 2021 05:57:23 -0700 (PDT) Date: Tue, 26 Oct 2021 13:57:21 +0100 From: "Leif Lindholm" To: Nhi Pham Cc: devel@edk2.groups.io, patches@amperecomputing.com, vunguyen@os.amperecomputing.com, Thang Nguyen , Chuong Tran , Phong Vo , Michael D Kinney , Ard Biesheuvel , Nate DeSimone Subject: Re: [edk2-platforms][PATCH v4 25/31] Ampere: Utilize the PCIe User setting Message-ID: <20211026125721.brcrawkqcqra5bki@leviathan> References: <20211022061809.31087-1-nhi@os.amperecomputing.com> <20211022061809.31087-26-nhi@os.amperecomputing.com> MIME-Version: 1.0 In-Reply-To: <20211022061809.31087-26-nhi@os.amperecomputing.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Oct 22, 2021 at 13:18:03 +0700, Nhi Pham wrote: > From: Vu Nguyen > > This change allows to configure the PCIe bifurcation mode and update > the ACPI IORT tables based on the PCIe User setting. > > Cc: Thang Nguyen > Cc: Chuong Tran > Cc: Phong Vo > Cc: Leif Lindholm > Cc: Michael D Kinney > Cc: Ard Biesheuvel > Cc: Nate DeSimone > > Signed-off-by: Nhi Pham Reviewed-by: Leif Lindholm > --- > Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 2 + > Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.inf | 5 +++ > Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiIort.c | 32 ++++++++++++---- > Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.c | 40 ++++++++++++++++++-- > 4 files changed, 69 insertions(+), 10 deletions(-) > > diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf > index 415f795d2a54..804e761a1524 100644 > --- a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf > +++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf > @@ -52,6 +52,7 @@ [LibraryClasses] > UefiBootServicesTableLib > UefiDriverEntryPoint > UefiLib > + UefiRuntimeServicesTableLib > > [Pcd] > gArmPlatformTokenSpaceGuid.PcdCoreCount > @@ -70,6 +71,7 @@ [Guids] > gEfiEventReadyToBootGuid > gPlatformInfoHobGuid > gRootComplexInfoHobGuid > + gRootComplexConfigFormSetGuid > > [Protocols] > gEfiAcpiTableProtocolGuid ## ALWAYS_CONSUMED > diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.inf b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.inf > index 17ac1672dac8..32d60bec1440 100644 > --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.inf > +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.inf > @@ -31,9 +31,14 @@ [LibraryClasses] > DebugLib > HobLib > PeimEntryPoint > + PeiServicesLib > + > +[Ppis] > + gEfiPeiReadOnlyVariable2PpiGuid > > [Guids] > gRootComplexInfoHobGuid > + gRootComplexConfigFormSetGuid > gPlatformInfoHobGuid > > [Depex] > diff --git a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiIort.c b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiIort.c > index b8f8cfa356af..97be85c51f25 100644 > --- a/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiIort.c > +++ b/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiIort.c > @@ -7,6 +7,7 @@ > **/ > > #include > +#include > #include > #include > #include > @@ -17,6 +18,7 @@ > #include > #include > #include > +#include > #include > #include > > @@ -282,8 +284,10 @@ AcpiInstallIort ( > EFI_ACPI_TABLE_PROTOCOL *AcpiTableProtocol; > EFI_STATUS Status; > INT32 EnabledRCs[AC01_PCIE_MAX_ROOT_COMPLEX]; > + ROOT_COMPLEX_CONFIG_VARSTORE_DATA VarStoreConfig; > UINT32 RcCount, SmmuPmuAgentCount, TotalCount; > UINT8 Idx; > + UINTN BufferSize; > UINTN TableKey; > VOID *Hob; > VOID *IortBuffer; > @@ -313,14 +317,28 @@ AcpiInstallIort ( > } > > SmmuPmuAgentCount = 0; > - for (Idx = 0; Idx < RcCount; Idx++) { > - if (mRootComplexList[EnabledRCs[Idx]].Type == RootComplexTypeA) { > - SmmuPmuAgentCount += AC01_RCA_MAX_TBU_PMU; > - } else { > - SmmuPmuAgentCount += AC01_RCB_MAX_TBU_PMU; > + > + // > + // Check SMMU setting > + // > + BufferSize = sizeof (VarStoreConfig); > + Status = gRT->GetVariable ( > + ROOT_COMPLEX_CONFIG_VARSTORE_NAME, > + &gRootComplexConfigFormSetGuid, > + NULL, > + &BufferSize, > + &VarStoreConfig > + ); > + if (!EFI_ERROR (Status) && VarStoreConfig.SmmuPmu) { > + for (Idx = 0; Idx < RcCount; Idx++) { > + if (mRootComplexList[EnabledRCs[Idx]].Type == RootComplexTypeA) { > + SmmuPmuAgentCount += AC01_RCA_MAX_TBU_PMU; > + } else { > + SmmuPmuAgentCount += AC01_RCB_MAX_TBU_PMU; > + } > + // Plus 1 TCU > + SmmuPmuAgentCount += 1; > } > - // Plus 1 TCU > - SmmuPmuAgentCount += 1; > } > > TotalCount = sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE) + > diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.c > index 76cbb76f38f0..3e873a669332 100644 > --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.c > +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.c > @@ -8,6 +8,7 @@ > > #include > > +#include > #include > #include > #include > @@ -15,7 +16,9 @@ > #include > #include > #include > +#include > #include > +#include > > #include "RootComplexNVParam.h" > > @@ -43,8 +46,39 @@ BuildRootComplexData ( > ) > { > AC01_ROOT_COMPLEX *RootComplex; > + BOOLEAN ConfigFound; > + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi; > + EFI_STATUS Status; > + ROOT_COMPLEX_CONFIG_VARSTORE_DATA RootComplexConfig; > UINT8 RCIndex; > UINT8 PcieIndex; > + UINTN DataSize; > + > + ConfigFound = FALSE; > + > + // > + // Get the Root Complex config from NVRAM > + // > + Status = PeiServicesLocatePpi ( > + &gEfiPeiReadOnlyVariable2PpiGuid, > + 0, > + NULL, > + (VOID **)&VariablePpi > + ); > + if (!EFI_ERROR (Status)) { > + DataSize = sizeof (RootComplexConfig); > + Status = VariablePpi->GetVariable ( > + VariablePpi, > + ROOT_COMPLEX_CONFIG_VARSTORE_NAME, > + &gRootComplexConfigFormSetGuid, > + NULL, > + &DataSize, > + &RootComplexConfig > + ); > + if (!EFI_ERROR (Status)) { > + ConfigFound = TRUE; > + } > + } > > ZeroMem (&mRootComplexList, sizeof (AC01_ROOT_COMPLEX) * AC01_PCIE_MAX_ROOT_COMPLEX); > > @@ -58,9 +92,9 @@ BuildRootComplexData ( > > for (RCIndex = 0; RCIndex < AC01_PCIE_MAX_ROOT_COMPLEX; RCIndex++) { > RootComplex = &mRootComplexList[RCIndex]; > - RootComplex->Active = TRUE; > - RootComplex->DevMapLow = 0; > - RootComplex->DevMapHigh = 0; > + RootComplex->Active = ConfigFound ? RootComplexConfig.RCStatus[RCIndex] : TRUE; > + RootComplex->DevMapLow = ConfigFound ? RootComplexConfig.RCBifurcationLow[RCIndex] : 0; > + RootComplex->DevMapHigh = ConfigFound ? RootComplexConfig.RCBifurcationLow[RCIndex] : 0; > RootComplex->Socket = RCIndex / AC01_PCIE_MAX_RCS_PER_SOCKET; > RootComplex->ID = RCIndex % AC01_PCIE_MAX_RCS_PER_SOCKET; > RootComplex->CsrBase = mCsrBase[RCIndex]; > -- > 2.17.1 >