From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by mx.groups.io with SMTP id smtpd.web12.639.1635453886031473821 for ; Thu, 28 Oct 2021 13:44:46 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="body hash did not verify" header.i=@linux.microsoft.com header.s=default header.b=kY/S/kHP; spf=pass (domain: linux.microsoft.com, ip: 13.77.154.182, mailfrom: mikuback@linux.microsoft.com) Received: from localhost.localdomain (c-73-27-179-174.hsd1.fl.comcast.net [73.27.179.174]) by linux.microsoft.com (Postfix) with ESMTPSA id 18240208F4E9; Thu, 28 Oct 2021 13:44:45 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 18240208F4E9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1635453885; bh=z6ug4vFszEd5hsuVyXfh56XXeXqJFCHrfZ3Qay68UwQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kY/S/kHPGSwAswVYCzOJ/wvIBiodnbBHMvu9mEOuQ+XO9C7b8BPznsEXaGtkXvj2c /cmnBWBJoYCpbl2E6rMj05fOp45fot2C2YyddvqBoMg4wGMNouopQ6mxuKClKntv0i bpPVh8xiTEEqmhFP7ZBby/nmM1CrCINAWywheSk4= From: "Michael Kubacki" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Jeremy Soller , Benjamin Doron Subject: [PATCH v6 12/52] KabylakeOpenBoardPkg: Use IntelSiliconPkg BIOS area and ucode PCDs Date: Thu, 28 Oct 2021 16:42:46 -0400 Message-Id: <20211028204326.645-13-mikuback@linux.microsoft.com> X-Mailer: git-send-email 2.28.0.windows.1 In-Reply-To: <20211028204326.645-1-mikuback@linux.microsoft.com> References: <20211028204326.645-1-mikuback@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Kubacki REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3307 Updates PCDs to use the IntelSiliconPkg PCD tokenspace now that the PCDs are declared in IntelSiliconPkg.dec. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Jeremy Soller Cc: Benjamin Doron Signed-off-by: Michael Kubacki Reviewed-by: Nate DeSimone Reviewed-by: Chasel Chiu --- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/FlashM= apInclude.fdf | 4 +-- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.fdf = | 38 ++++++++++-----= ----- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/Pei= SiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf | 4 +-- Platform/Intel/KabylakeOpenBoardPkg/BiosInfo/BiosInfo.inf = | 4 +-- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMapInclu= de.fdf | 4 +-- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf = | 38 ++++++++++-----= ----- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/FlashMapInc= lude.fdf | 4 +-- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf = | 38 ++++++++++-----= ----- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSilic= onPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf | 4 +-- 9 files changed, 69 insertions(+), 69 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Includ= e/Fdf/FlashMapInclude.fdf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7= Dash572G/Include/Fdf/FlashMapInclude.fdf index aac4d83f6480..8f6696b7d1fe 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/F= lashMapInclude.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/F= lashMapInclude.fdf @@ -36,8 +36,8 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D = 0x00180000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D = 0x003C0000 # Flash addr (0xFFDC0000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D = 0x00020000 # -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D = 0x003E0000 # Flash addr (0xFFDE0000) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D = 0x00080000 # +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D = 0x003E0000 # Flash addr (0xFFDE0000) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D = 0x00080000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D = 0x00460000 # Flash addr (0xFFE60000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D = 0x0004C000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D = 0x004AC000 # Flash addr (0xFFEAC000) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBo= ardPkg.fdf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBo= ardPkg.fdf index 7a926454eaad..36fd0bb733da 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.= fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.= fdf @@ -29,8 +29,8 @@ [FD.AspireVn7Dash572G] # assigned with PCD values. Instead, it uses the definitions for its var= iety, which # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS. # -BaseAddress =3D $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdFlashAreaBaseA= ddress #The base address of the FLASH Device. -Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdFlashAreaSize = #The size in bytes of the FLASH Device +BaseAddress =3D $(FLASH_BASE) | gIntelSiliconPkgTokenSpaceGuid.PcdBios= AreaBaseAddress #The base address of the FLASH Device. +Size =3D $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBios= Size #The size in bytes of the FLASH Device ErasePolarity =3D 1 BlockSize =3D $(FLASH_BLOCK_SIZE) NumBlocks =3D $(FLASH_NUM_BLOCKS) @@ -39,23 +39,23 @@ [FD.AspireVn7Dash572G] DEFINE SIPKG_PEI_BIN =3D INF =20 # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because ma= cro expression is not supported. -# So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase = to get the real CodeCache base address. +# So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase t= o get the real CodeCache base address. SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D $(gMinPlatformPkgTokenS= paceGuid.PcdFlashFvPreMemoryOffset) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gSiPkgTokenSpaceG= uid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFv= Offset) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceG= uid.PcdFlashMicrocodeFvSize) -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgTo= kenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPk= gTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gIntelSiliconPkgToken= SpaceGuid.PcdFlashMicrocodeFvOffset) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gIntelSi= liconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60 -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvBase -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvOffset -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gSiPkgT= okenSpaceGuid.PcdFlashAreaBaseAddress -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gSiPkgT= okenSpaceGuid.PcdFlashAreaSize -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGui= d.PcdFlashFvFspTOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGui= d.PcdFlashFvFspMOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGui= d.PcdFlashFvFspSOffset) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gSiPkgT= okenSpaceGuid.PcdFlashAreaBaseAddress -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gSiPkgT= okenSpaceGuid.PcdFlashAreaSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosSize +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspTOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspMOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspSOffset) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosSize ########################################################################= ######## # # Following are lists of FD Region layout which correspond to the locati= ons of different @@ -155,8 +155,8 @@ [FD.AspireVn7Dash572G] gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvPostMemorySize FV =3D FvPostMemory =20 -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdF= lashMicrocodeFvSize -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFla= shMicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconPk= gTokenSpaceGuid.PcdFlashMicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize #Microcode FV =3D FvMicrocode =20 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy= /Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platfo= rm/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSilicon= PolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf index 4dcc000186ac..1ce26fc3dcec 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar= y/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Librar= y/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf @@ -68,11 +68,11 @@ [Guids] =20 [Pcd] gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize gSiPkgTokenSpaceGuid.PcdMchBaseAddress gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress gSiPkgTokenSpaceGuid.PcdTsegSize + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd ## CONSU= MES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig ## CONSU= MES diff --git a/Platform/Intel/KabylakeOpenBoardPkg/BiosInfo/BiosInfo.inf b/= Platform/Intel/KabylakeOpenBoardPkg/BiosInfo/BiosInfo.inf index e5e40144a68a..6607ea6edfc3 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/BiosInfo/BiosInfo.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/BiosInfo/BiosInfo.inf @@ -36,8 +36,8 @@ [Packages] MinPlatformPkg/MinPlatformPkg.dec =20 [Pcd] - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CON= SUMES - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CON= SUMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = ## CONSUMES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = ## CONSUMES =20 [Sources] BiosInfo.c diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/F= lashMapInclude.fdf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Inclu= de/Fdf/FlashMapInclude.fdf index 6cb6d54f558f..ce809a277b6e 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMap= Include.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMap= Include.fdf @@ -36,8 +36,8 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D = 0x00140000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D = 0x002E0000 # Flash addr (0xFFD00000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D = 0x000B0000 # -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D = 0x00390000 # Flash addr (0xFFDB0000) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D = 0x000A0000 # +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D = 0x00390000 # Flash addr (0xFFDB0000) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D = 0x000A0000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D = 0x00430000 # Flash addr (0xFFE50000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D = 0x00060000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D = 0x00490000 # Flash addr (0xFFEB0000) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.= fdf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf index bcd1ade72ba5..39432d21b8b5 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf @@ -29,8 +29,8 @@ [FD.GalagoPro3] # assigned with PCD values. Instead, it uses the definitions for its var= iety, which # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS. # -BaseAddress =3D $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdFlashAreaBaseA= ddress #The base address of the FLASH Device. -Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdFlashAreaSize = #The size in bytes of the FLASH Device +BaseAddress =3D $(FLASH_BASE) | gIntelSiliconPkgTokenSpaceGuid.PcdBios= AreaBaseAddress #The base address of the FLASH Device. +Size =3D $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBios= Size #The size in bytes of the FLASH Device ErasePolarity =3D 1 BlockSize =3D $(FLASH_BLOCK_SIZE) NumBlocks =3D $(FLASH_NUM_BLOCKS) @@ -39,23 +39,23 @@ [FD.GalagoPro3] DEFINE SIPKG_PEI_BIN =3D INF =20 # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because ma= cro expression is not supported. -# So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase = to get the real CodeCache base address. +# So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase t= o get the real CodeCache base address. SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D $(gMinPlatformPkgTokenS= paceGuid.PcdFlashFvPreMemoryOffset) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gSiPkgTokenSpaceG= uid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFv= Offset) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceG= uid.PcdFlashMicrocodeFvSize) -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgTo= kenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPk= gTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gIntelSiliconPkgToken= SpaceGuid.PcdFlashMicrocodeFvOffset) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gIntelSi= liconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60 -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvBase -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvOffset -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gSiPkgT= okenSpaceGuid.PcdFlashAreaBaseAddress -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gSiPkgT= okenSpaceGuid.PcdFlashAreaSize -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGui= d.PcdFlashFvFspTOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGui= d.PcdFlashFvFspMOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGui= d.PcdFlashFvFspSOffset) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gSiPkgT= okenSpaceGuid.PcdFlashAreaBaseAddress -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gSiPkgT= okenSpaceGuid.PcdFlashAreaSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosSize +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspTOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspMOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspSOffset) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosSize ########################################################################= ######## # # Following are lists of FD Region layout which correspond to the locati= ons of different @@ -155,8 +155,8 @@ [FD.GalagoPro3] gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvPostMemorySize FV =3D FvPostMemory =20 -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdF= lashMicrocodeFvSize -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFla= shMicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconPk= gTokenSpaceGuid.PcdFlashMicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize #Microcode FV =3D FvMicrocode =20 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf= /FlashMapInclude.fdf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/I= nclude/Fdf/FlashMapInclude.fdf index b5e3f66ceafc..67649e867616 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/FlashM= apInclude.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/Fdf/FlashM= apInclude.fdf @@ -34,8 +34,8 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D = 0x001E0000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D = 0x00370000 # Flash addr (0xFFB70000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D = 0x00180000 # -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D = 0x004F0000 # Flash addr (0xFFCF0000) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D = 0x000A0000 # +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D = 0x004F0000 # Flash addr (0xFFCF0000) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D = 0x000A0000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D = 0x00590000 # Flash addr (0xFFD90000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D = 0x00060000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D = 0x005F0000 # Flash addr (0xFFDF0000) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPk= g.fdf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf index 6cdf4e2f9f1f..f003dda0ddfc 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf @@ -29,8 +29,8 @@ [FD.KabylakeRvp3] # assigned with PCD values. Instead, it uses the definitions for its var= iety, which # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS. # -BaseAddress =3D $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdFlashAreaBaseA= ddress #The base address of the FLASH Device. -Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdFlashAreaSize = #The size in bytes of the FLASH Device +BaseAddress =3D $(FLASH_BASE) | gIntelSiliconPkgTokenSpaceGuid.PcdBios= AreaBaseAddress #The base address of the FLASH Device. +Size =3D $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBios= Size #The size in bytes of the FLASH Device ErasePolarity =3D 1 BlockSize =3D $(FLASH_BLOCK_SIZE) NumBlocks =3D $(FLASH_NUM_BLOCKS) @@ -39,23 +39,23 @@ [FD.KabylakeRvp3] DEFINE SIPKG_PEI_BIN =3D INF =20 # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because ma= cro expression is not supported. -# So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase = to get the real CodeCache base address. +# So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase t= o get the real CodeCache base address. SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D $(gMinPlatformPkgTokenS= paceGuid.PcdFlashFvPreMemoryOffset) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gSiPkgTokenSpaceG= uid.PcdFlashAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFv= Offset) -SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceG= uid.PcdFlashMicrocodeFvSize) -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgTo= kenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 -SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPk= gTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gIntelSiliconPkgToken= SpaceGuid.PcdFlashMicrocodeFvOffset) +SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gIntelSi= liconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D 0x60 -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvBase -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvOffset -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gSiPkgT= okenSpaceGuid.PcdFlashAreaBaseAddress -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gSiPkgT= okenSpaceGuid.PcdFlashAreaSize -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGui= d.PcdFlashFvFspTOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGui= d.PcdFlashFvFspMOffset) -SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gSiPk= gTokenSpaceGuid.PcdFlashAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGui= d.PcdFlashFvFspSOffset) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gSiPkgT= okenSpaceGuid.PcdFlashAreaBaseAddress -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gSiPkgT= okenSpaceGuid.PcdFlashAreaSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gIntelS= iliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosSize +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspTOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspMOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gInte= lSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspSOffset) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gIntelS= iliconPkgTokenSpaceGuid.PcdBiosSize ########################################################################= ######## # # Following are lists of FD Region layout which correspond to the locati= ons of different @@ -151,8 +151,8 @@ [FD.KabylakeRvp3] gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvPostMemorySize FV =3D FvPostMemory =20 -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdF= lashMicrocodeFvSize -gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFla= shMicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconPk= gTokenSpaceGuid.PcdFlashMicrocodeFvSize +gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize #Microcode FV =3D FvMicrocode =20 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Libr= ary/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/In= tel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpda= teLib/PeiSiliconPolicyUpdateLib.inf index 4b30ba02ead6..25eae88f5989 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/Pei= SiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/Pei= SiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf @@ -54,11 +54,11 @@ [Guids] =20 [Pcd] gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase - gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize gSiPkgTokenSpaceGuid.PcdMchBaseAddress gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress gSiPkgTokenSpaceGuid.PcdTsegSize + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONSU= MES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONSU= MES --=20 2.28.0.windows.1