From: "Michael Kubacki" <mikuback@linux.microsoft.com>
To: devel@edk2.groups.io
Cc: Ray Ni <ray.ni@intel.com>,
Rangasai V Chaganty <rangasai.v.chaganty@intel.com>,
Nate DeSimone <nathaniel.l.desimone@intel.com>
Subject: [PATCH v6 07/52] IntelSiliconPkg: Add PCH SPI Protocol
Date: Thu, 28 Oct 2021 16:42:41 -0400 [thread overview]
Message-ID: <20211028204326.645-8-mikuback@linux.microsoft.com> (raw)
In-Reply-To: <20211028204326.645-1-mikuback@linux.microsoft.com>
From: Michael Kubacki <michael.kubacki@microsoft.com>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3307
These SPI Protocol definitions are intended to serve as the single
definitions for Intel platform and silicon packages.
1. gPchSpiProtocolGuid
2. gPchSmmSpiProtocolGuid
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
---
Silicon/Intel/IntelSiliconPkg/Include/Protocol/Spi.h | 301 ++++++++++++++++++++
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 5 +
2 files changed, 306 insertions(+)
diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Protocol/Spi.h b/Silicon/Intel/IntelSiliconPkg/Include/Protocol/Spi.h
new file mode 100644
index 000000000000..c13dc5a5f5f5
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/Protocol/Spi.h
@@ -0,0 +1,301 @@
+/** @file
+ This file defines the PCH SPI Protocol which implements the
+ Intel(R) PCH SPI Host Controller Compatibility Interface.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_SPI_PROTOCOL_H_
+#define _PCH_SPI_PROTOCOL_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gPchSpiProtocolGuid;
+extern EFI_GUID gPchSmmSpiProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL;
+
+//
+// SPI protocol data structures and definitions
+//
+
+/**
+ Flash Region Type
+**/
+typedef enum {
+ FlashRegionDescriptor,
+ FlashRegionBios,
+ FlashRegionMe,
+ FlashRegionGbE,
+ FlashRegionPlatformData,
+ FlashRegionDer,
+ FlashRegionSecondaryBios,
+ FlashRegionuCodePatch,
+ FlashRegionEC,
+ FlashRegionDeviceExpansion2,
+ FlashRegionIE,
+ FlashRegion10Gbe_A,
+ FlashRegion10Gbe_B,
+ FlashRegion13,
+ FlashRegion14,
+ FlashRegion15,
+ FlashRegionAll,
+ FlashRegionMax
+} FLASH_REGION_TYPE;
+//
+// Protocol member functions
+//
+
+/**
+ Read data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[out] Buffer The Pointer to caller-allocated buffer containing the dada received.
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Write data to the flash part. Remark: Erase may be needed before write to the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[in] Buffer Pointer to caller-allocated buffer containing the data sent during the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_WRITE) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN UINT8 *Buffer
+ );
+
+/**
+ Erase some area on the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_ERASE) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount
+ );
+
+/**
+ Read SFDP data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] Address The starting byte address for SFDP data read.
+ @param[in] ByteCount Number of bytes in SFDP data portion of the SPI cycle
+ @param[out] SfdpData The Pointer to caller-allocated buffer containing the SFDP data received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ_SFDP) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *SfdpData
+ );
+
+/**
+ Read Jedec Id from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] ByteCount Number of bytes in JedecId data portion of the SPI cycle, the data size is 3 typically
+ @param[out] JedecId The Pointer to caller-allocated buffer containing JEDEC ID received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ_JEDEC_ID) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 ByteCount,
+ OUT UINT8 *JedecId
+ );
+
+/**
+ Write the status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[in] StatusValue The Pointer to caller-allocated buffer containing the value of Status register writing
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_WRITE_STATUS) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ IN UINT8 *StatusValue
+ );
+
+/**
+ Read status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[out] StatusValue The Pointer to caller-allocated buffer containing the value of Status register received.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ_STATUS) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ OUT UINT8 *StatusValue
+ );
+
+/**
+ Get the SPI region base and size, based on the enum type
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for for the base address which is listed in the Descriptor.
+ @param[out] BaseAddress The Flash Linear Address for the Region 'n' Base
+ @param[out] RegionSize The size for the Region 'n'
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_INVALID_PARAMETER Invalid region type given
+ @retval EFI_DEVICE_ERROR The region is not used
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_GET_REGION_ADDRESS) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ OUT UINT32 *BaseAddress,
+ OUT UINT32 *RegionSize
+ );
+
+/**
+ Read PCH Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing PCH Soft Strap Value.
+ If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_READ_PCH_SOFTSTRAP) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ );
+
+/**
+ Read CPU Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle.
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing CPU Soft Strap Value.
+ If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_READ_CPU_SOFTSTRAP) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ );
+
+/**
+ These protocols/PPI allows a platform module to perform SPI operations through the
+ Intel PCH SPI Host Controller Interface.
+**/
+struct _PCH_SPI_PROTOCOL {
+ /**
+ This member specifies the revision of this structure. This field is used to
+ indicate backwards compatible changes to the protocol.
+ **/
+ UINT8 Revision;
+ PCH_SPI_FLASH_READ FlashRead; ///< Read data from the flash part.
+ PCH_SPI_FLASH_WRITE FlashWrite; ///< Write data to the flash part. Remark: Erase may be needed before write to the flash part.
+ PCH_SPI_FLASH_ERASE FlashErase; ///< Erase some area on the flash part.
+ PCH_SPI_FLASH_READ_SFDP FlashReadSfdp; ///< Read SFDP data from the flash part.
+ PCH_SPI_FLASH_READ_JEDEC_ID FlashReadJedecId; ///< Read Jedec Id from the flash part.
+ PCH_SPI_FLASH_WRITE_STATUS FlashWriteStatus; ///< Write the status register in the flash part.
+ PCH_SPI_FLASH_READ_STATUS FlashReadStatus; ///< Read status register in the flash part.
+ PCH_SPI_GET_REGION_ADDRESS GetRegionAddress; ///< Get the SPI region base and size
+ PCH_SPI_READ_PCH_SOFTSTRAP ReadPchSoftStrap; ///< Read PCH Soft Strap Values
+ PCH_SPI_READ_CPU_SOFTSTRAP ReadCpuSoftStrap; ///< Read CPU Soft Strap Values
+};
+
+/**
+ PCH SPI PPI/PROTOCOL revision number
+
+ Revision 1: Initial version
+**/
+#define PCH_SPI_SERVICES_REVISION 1
+
+#endif
diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index 1fa447f37722..4e87d5e852d3 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -78,6 +78,11 @@ [Ppis]
gEdkiiVTdNullRootEntryTableGuid = { 0x3de0593f, 0x6e3e, 0x4542, { 0xa1, 0xcb, 0xcb, 0xb2, 0xdb, 0xeb, 0xd8, 0xff } }
[Protocols]
+ ## Protocols that provide services for the Intel(R) PCH SPI Host Controller Compatibility Interface
+ # Include/Protocol/Spi.h
+ gPchSpiProtocolGuid = { 0xe007dec0, 0xccc3, 0x4c90, { 0x9c, 0xd0, 0xef, 0x99, 0x38, 0x83, 0x28, 0xcf } }
+ gPchSmmSpiProtocolGuid = { 0x4840e48e, 0xc264, 0x4fef, { 0xb9, 0x34, 0x14, 0x84, 0x0c, 0x95, 0xd8, 0x3f } }
+
gEdkiiPlatformVTdPolicyProtocolGuid = { 0x3d17e448, 0x466, 0x4e20, { 0x99, 0x9f, 0xb2, 0xe1, 0x34, 0x88, 0xee, 0x22 }}
## Protocol for device security policy.
--
2.28.0.windows.1
next prev parent reply other threads:[~2021-10-28 20:44 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-28 20:42 [PATCH v6 00/52] Consolidate SpiFlashCommonLib instances Michael Kubacki
2021-10-28 20:42 ` [PATCH v6 01/52] CometlakeOpenBoardPkg: Remove redundant IntelSiliconPkg.dec entry Michael Kubacki
2021-10-28 20:42 ` [PATCH v6 02/52] WhiskeylakeOpenBoardPkg: " Michael Kubacki
2021-10-28 20:42 ` [PATCH v6 03/52] CometlakeOpenBoardPkg/PeiPolicyUpdateLib: Add missing GUID to INF Michael Kubacki
2021-10-28 20:42 ` [PATCH v6 04/52] IntelSiliconPkg: Add BIOS area base address and size PCDs Michael Kubacki
2021-10-28 20:42 ` [PATCH v6 05/52] IntelSiliconPkg: Add microcode FV PCDs Michael Kubacki
2021-10-28 20:42 ` [PATCH v6 06/52] IntelSiliconPkg: Add PCH SPI PPI Michael Kubacki
2021-10-29 22:22 ` Nate DeSimone
2021-10-29 22:54 ` [edk2-devel] " Michael Kubacki
2021-10-28 20:42 ` Michael Kubacki [this message]
2021-10-29 22:22 ` [edk2-devel] [PATCH v6 07/52] IntelSiliconPkg: Add PCH SPI Protocol Nate DeSimone
2021-10-28 20:42 ` [PATCH v6 08/52] IntelSiliconPkg: Add SpiFlashCommonLib Michael Kubacki
2021-10-28 20:42 ` [PATCH v6 09/52] IntelSiliconPkg: Add SmmSpiFlashCommonLib Michael Kubacki
2021-10-28 20:42 ` [PATCH v6 10/52] IntelSiliconPkg: Add MM SPI FVB services Michael Kubacki
2021-10-28 20:42 ` [PATCH v6 11/52] CometlakeOpenBoardPkg: Use IntelSiliconPkg BIOS area and ucode PCDs Michael Kubacki
2021-10-28 20:42 ` [PATCH v6 12/52] KabylakeOpenBoardPkg: " Michael Kubacki
2021-10-28 20:42 ` [PATCH v6 13/52] SimicsOpenBoardPkg: " Michael Kubacki
2021-10-28 20:42 ` [PATCH v6 14/52] TigerlakeOpenBoardPkg: " Michael Kubacki
2021-10-28 20:42 ` [PATCH v6 15/52] WhiskeylakeOpenBoardPkg: " Michael Kubacki
2021-10-28 20:42 ` [PATCH v6 16/52] CoffeelakeSiliconPkg: " Michael Kubacki
2021-10-28 20:42 ` [PATCH v6 17/52] KabylakeSiliconPkg: " Michael Kubacki
2021-10-28 20:42 ` [PATCH v6 18/52] SimicsIch10Pkg: " Michael Kubacki
2021-10-28 20:42 ` [PATCH v6 19/52] TigerlakeSiliconPkg: " Michael Kubacki
2021-10-29 3:02 ` [edk2-devel] " Heng Luo
2021-10-28 20:42 ` [PATCH v6 20/52] CometlakeOpenBoardPkg: Update SpiFvbService & SpiFlashCommonLib Michael Kubacki
2021-10-28 20:42 ` [PATCH v6 21/52] KabylakeOpenBoardPkg: " Michael Kubacki
2021-10-28 20:42 ` [PATCH v6 22/52] SimicsOpenBoardPkg: " Michael Kubacki
2021-10-28 20:42 ` [PATCH v6 23/52] TigerlakeOpenBoardPkg: " Michael Kubacki
2021-10-29 3:03 ` Heng Luo
2021-10-28 20:42 ` [PATCH v6 24/52] WhiskeylakeOpenBoardPkg: " Michael Kubacki
2021-10-28 20:42 ` [PATCH v6 25/52] PurleyOpenBoardPkg: Use IntelSiliconPkg SpiFvbServiceSmm Michael Kubacki
2021-11-02 23:11 ` Nate DeSimone
2021-10-28 20:43 ` [PATCH v6 26/52] WhitleyOpenBoardPkg: UseIntelSiliconPkg SpiFvbServiceSmm Michael Kubacki
2021-11-01 20:40 ` Oram, Isaac W
2021-11-02 23:12 ` Nate DeSimone
2021-10-28 20:43 ` [PATCH v6 27/52] MinPlatformPkg: Remove SpiFvbService modules Michael Kubacki
2021-10-28 20:43 ` [PATCH v6 28/52] CoffeelakeSiliconPkg: Remove SmmSpiFlashCommonLib Michael Kubacki
2021-10-28 20:43 ` [PATCH v6 29/52] KabylakeSiliconPkg: " Michael Kubacki
2021-10-28 20:43 ` [PATCH v6 30/52] SimicsIch10Pkg: " Michael Kubacki
2021-10-28 20:43 ` [PATCH v6 31/52] TigerlakeOpenBoardPkg: " Michael Kubacki
2021-10-29 3:03 ` Heng Luo
2021-10-28 20:43 ` [PATCH v6 32/52] MinPlatformPkg: Remove SpiFlashCommonLibNull Michael Kubacki
2021-10-28 20:43 ` [PATCH v6 33/52] PurleyOpenBoardPkg: Add SpiFlashCommonLib.h Michael Kubacki
2021-11-01 20:38 ` Oram, Isaac W
2021-11-01 21:01 ` Michael Kubacki
2021-11-02 23:18 ` Nate DeSimone
2021-10-28 20:43 ` [PATCH v6 34/52] KabylakeOpenBoardPkg/PeiSerialPortLibSpiFlash: Add IntelSiliconPkg.dec Michael Kubacki
2021-10-28 20:43 ` [PATCH v6 35/52] CoffeelakeSiliconPkg: Remove PCH SPI PPI and Protocol from package Michael Kubacki
2021-11-01 20:43 ` [edk2-devel] [PATCH v6 00/52] Consolidate SpiFlashCommonLib instances Oram, Isaac W
2021-11-01 21:13 ` Michael Kubacki
2021-11-02 23:39 ` Nate DeSimone
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