From: "Sheng Wei" <w.sheng@intel.com>
To: devel@edk2.groups.io
Cc: Robert Kowalewski <robert.kowalewski@intel.com>,
Jenny Huang <jenny.huang@intel.com>, Ray Ni <ray.ni@intel.com>,
Rangasai V Chaganty <rangasai.v.chaganty@intel.com>,
Albecki Mateusz <mateusz.albecki@intel.com>,
Kolakowski Jacek <Jacek.Kolakowski@intel.com>
Subject: [PATCH v6] IntelSiliconPkg/IntelVTdDxe: Support Multi PCI Root Bus
Date: Wed, 3 Nov 2021 14:38:21 +0800 [thread overview]
Message-ID: <20211103063821.9808-1-w.sheng@intel.com> (raw)
Some system may has multi PCI root bridges. It needs to use PciRootBridgeIo
protocol to get the root bridge count. Scan each root bridge to get all
PCI devices.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3695
Signed-off-by: Robert Kowalewski <robert.kowalewski@intel.com>
Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Jenny Huang <jenny.huang@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Robert Kowalewski <robert.kowalewski@intel.com>
Cc: Albecki Mateusz <mateusz.albecki@intel.com>
Cc: Kolakowski Jacek <Jacek.Kolakowski@intel.com>
Reviewed-by: Jenny Huang <jenny.huang@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
---
.../Feature/VTd/IntelVTdDxe/DmaProtection.h | 17 ++++++
.../Feature/VTd/IntelVTdDxe/DmarAcpiTable.c | 2 +-
.../Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf | 1 +
.../Feature/VTd/IntelVTdDxe/PciInfo.c | 70 ++++++++++++++++++++++
4 files changed, 89 insertions(+), 1 deletion(-)
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.h b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.h
index a24fbc37..7dd29a24 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.h
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.h
@@ -33,6 +33,7 @@
#include <Protocol/PciEnumerationComplete.h>
#include <Protocol/PlatformVtdPolicy.h>
#include <Protocol/IoMmu.h>
+#include <Protocol/PciRootBridgeIo.h>
#include <IndustryStandard/Pci.h>
#include <IndustryStandard/DmaRemappingReportingTable.h>
@@ -341,6 +342,22 @@ ScanPciBus (
IN SCAN_BUS_FUNC_CALLBACK_FUNC Callback
);
+/**
+ Scan PCI bus and invoke callback function for each PCI devices under all root bus.
+
+ @param[in] Context The context of the callback function.
+ @param[in] Segment The segment of the source.
+ @param[in] Callback The callback function in PCI scan.
+
+ @retval EFI_SUCCESS The PCI devices under the bus are scaned.
+**/
+EFI_STATUS
+ScanAllPciBus (
+ IN VOID *Context,
+ IN UINT16 Segment,
+ IN SCAN_BUS_FUNC_CALLBACK_FUNC Callback
+ );
+
/**
Dump the PCI device information managed by this VTd engine.
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTable.c
index 2d9b4374..1ee290b7 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTable.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTable.c
@@ -692,7 +692,7 @@ ProcessDhrd (
mVtdUnitInformation[VtdIndex].PciDeviceInfo.IncludeAllFlag = TRUE;
DEBUG ((DEBUG_INFO," ProcessDhrd: with INCLUDE ALL\n"));
- Status = ScanPciBus((VOID *)VtdIndex, DmarDrhd->SegmentNumber, 0, ScanBusCallbackRegisterPciDevice);
+ Status = ScanAllPciBus((VOID *)VtdIndex, DmarDrhd->SegmentNumber, ScanBusCallbackRegisterPciDevice);
if (EFI_ERROR (Status)) {
return Status;
}
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
index 220636ad..387f90e3 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
@@ -70,6 +70,7 @@
gEfiPciIoProtocolGuid ## CONSUMES
gEfiPciEnumerationCompleteProtocolGuid ## CONSUMES
gEdkiiPlatformVTdPolicyProtocolGuid ## SOMETIMES_CONSUMES
+ gEfiPciRootBridgeIoProtocolGuid ## CONSUMES
[Pcd]
gIntelSiliconPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask ## CONSUMES
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/PciInfo.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/PciInfo.c
index 4af376b3..98726002 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/PciInfo.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/PciInfo.c
@@ -279,6 +279,76 @@ ScanPciBus (
return EFI_SUCCESS;
}
+/**
+ Scan PCI bus and invoke callback function for each PCI devices under all root bus.
+
+ @param[in] Context The context of the callback function.
+ @param[in] Segment The segment of the source.
+ @param[in] Callback The callback function in PCI scan.
+
+ @retval EFI_SUCCESS The PCI devices under the bus are scaned.
+**/
+EFI_STATUS
+ScanAllPciBus (
+ IN VOID *Context,
+ IN UINT16 Segment,
+ IN SCAN_BUS_FUNC_CALLBACK_FUNC Callback
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ UINTN HandleCount;
+ EFI_HANDLE *HandleBuffer;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
+
+ DEBUG ((DEBUG_INFO, "ScanAllPciBus ()\n"));
+
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiPciRootBridgeIoProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO,"Find %d root bridges\n", HandleCount));
+
+ for (Index = 0; Index < HandleCount; Index++) {
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gEfiPciRootBridgeIoProtocolGuid,
+ (VOID **) &PciRootBridgeIo
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PciRootBridgeIo->Configuration (PciRootBridgeIo, (VOID **) &Descriptors);
+ ASSERT_EFI_ERROR (Status);
+
+ while (Descriptors->Desc != ACPI_END_TAG_DESCRIPTOR) {
+ if (Descriptors->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {
+ break;
+ }
+ Descriptors++;
+ }
+
+ if (Descriptors->Desc == ACPI_END_TAG_DESCRIPTOR) {
+ continue;
+ }
+
+ DEBUG ((DEBUG_INFO,"Scan root bridges : %d, Segment : %d, Bus : 0x%02X\n", Index, PciRootBridgeIo->SegmentNumber, Descriptors->AddrRangeMin));
+ Status = ScanPciBus(Context, (UINT16) PciRootBridgeIo->SegmentNumber, (UINT8) Descriptors->AddrRangeMin, Callback);
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+ }
+
+ FreePool(HandleBuffer);
+
+ return Status;
+}
+
/**
Dump the PCI device information managed by this VTd engine.
--
2.16.2.windows.1
reply other threads:[~2021-11-03 6:38 UTC|newest]
Thread overview: [no followups] expand[flat|nested] mbox.gz Atom feed
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211103063821.9808-1-w.sheng@intel.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox