From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web09.3291.1636105577524348002 for ; Fri, 05 Nov 2021 02:46:18 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: ian.chiu@intel.com) X-IronPort-AV: E=McAfee;i="6200,9189,10158"; a="219068142" X-IronPort-AV: E=Sophos;i="5.87,211,1631602800"; d="scan'208";a="219068142" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Nov 2021 02:46:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,211,1631602800"; d="scan'208";a="450749963" Received: from ikuox-desk1.gar.corp.intel.com ([10.227.107.18]) by orsmga003.jf.intel.com with ESMTP; 05 Nov 2021 02:46:14 -0700 From: ian.chiu@intel.com To: devel@edk2.groups.io Cc: Ian Chiu , Ian Chiu , Maggie Chu , Ray Ni , Hao A Wu Subject: [PATCH v2] MdeModulePkg\UfsBlockIoPei: UFS MMIO address size support both 32/64 bits Date: Fri, 5 Nov 2021 17:46:09 +0800 Message-Id: <20211105094609.717-1-ian.chiu@intel.com> X-Mailer: git-send-email 2.30.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Ian Chiu REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3703 MMIO base address size will overflow while finding two or more Host controller in the system. Correct it and support 32 and 64 bits address space. Signed-off-by: Ian Chiu Cc: Maggie Chu Cc: Ray Ni Cc: Hao A Wu --- MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c | 47 +++++++++++++++++++- 1 file changed, 45 insertions(+), 2 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c b/MdeModulePkg/= Bus/Pci/UfsPciHcPei/UfsPciHcPei.c index 447a05b5b2..86f1529eec 100644 --- a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c +++ b/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c @@ -76,6 +76,8 @@ InitializeUfsHcPeim ( UINT16 Device;=0D UINT16 Function;=0D UINT32 Size;=0D + UINT64 MmioSize;=0D + UINT32 BarAddr;=0D UINT8 SubClass;=0D UINT8 BaseClass;=0D UFS_HC_PEI_PRIVATE_DATA *Private;=0D @@ -106,6 +108,7 @@ InitializeUfsHcPeim ( Private->PpiList =3D mPpiList;=0D Private->PpiList.Ppi =3D &Private->UfsHostControllerPpi;=0D =0D + BarAddr =3D PcdGet32 (PcdUfsPciHostControllerMmioBase);=0D for (Bus =3D 0; Bus < 256; Bus++) {=0D for (Device =3D 0; Device < 32; Device++) {=0D for (Function =3D 0; Function < 8; Function++) {=0D @@ -119,17 +122,57 @@ InitializeUfsHcPeim ( PciAnd16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OF= FSET), (UINT16)~(EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE)= );=0D PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADD= RESSREG_OFFSET), 0xFFFFFFFF);=0D Size =3D PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_= BASE_ADDRESSREG_OFFSET));=0D +=0D + switch (Size & 0x07) {=0D + case 0x0:=0D + //=0D + // Memory space: anywhere in 32 bit address space=0D + //=0D + MmioSize =3D (~(Size & 0xFFFFFFF0)) + 1;=0D + break;=0D + case 0x4:=0D + //=0D + // Memory space: anywhere in 64 bit address space=0D + //=0D + MmioSize =3D Size & 0xFFFFFFF0;=0D + PciWrite32 (PCI_LIB_ADDRESS(Bus, Device, Function, PCI_BASE_= ADDRESSREG_OFFSET + 4), 0xFFFFFFFF);=0D + Size =3D PciRead32 (PCI_LIB_ADDRESS(Bus, Device, Function, P= CI_BASE_ADDRESSREG_OFFSET + 4));=0D +=0D + //=0D + // Fix the length to support some specific 64 bit BAR=0D + //=0D + Size |=3D ((UINT32)(-1) << HighBitSet32 (Size));=0D +=0D + //=0D + // Calculate the size of 64bit bar=0D + //=0D + MmioSize |=3D LShiftU64 ((UINT64) Size, 32);=0D + MmioSize =3D (~(MmioSize)) + 1;=0D +=0D + //=0D + // Clean the high 32bits of this 64bit BAR to 0 as we only a= llow a 32bit BAR.=0D + //=0D + PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE= _ADDRESSREG_OFFSET + 4), 0);=0D + break;=0D + default:=0D + //=0D + // Unknown BAR type=0D + //=0D + ASSERT (FALSE);=0D + continue;=0D + };=0D //=0D // Assign resource to the Ufs Pci host controller's MMIO BAR.=0D // Enable the Ufs Pci host controller by setting BME and MSE bit= s of PCI_CMD register.=0D //=0D - PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADD= RESSREG_OFFSET), (UINT32)(PcdGet32 (PcdUfsPciHostControllerMmioBase) + Size= * Private->TotalUfsHcs));=0D + PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADD= RESSREG_OFFSET), BarAddr);=0D PciOr16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFF= SET), (EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));=0D //=0D // Record the allocated Mmio base address.=0D //=0D - Private->UfsHcPciAddr[Private->TotalUfsHcs] =3D PcdGet32 (PcdUfs= PciHostControllerMmioBase) + Size * Private->TotalUfsHcs;=0D + Private->UfsHcPciAddr[Private->TotalUfsHcs] =3D BarAddr;=0D Private->TotalUfsHcs++;=0D + BarAddr +=3D (UINT32)MmioSize;=0D ASSERT (Private->TotalUfsHcs < MAX_UFS_HCS);=0D }=0D }=0D --=20 2.16.2.windows.1