From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by mx.groups.io with SMTP id smtpd.web10.10061.1636452399190712704 for ; Tue, 09 Nov 2021 02:06:39 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=UZmaVEwh; spf=pass (domain: ventanamicro.com, ip: 209.85.128.49, mailfrom: sunilvl@ventanamicro.com) Received: by mail-wm1-f49.google.com with SMTP id 133so15353356wme.0 for ; Tue, 09 Nov 2021 02:06:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=7aPlccAojcftVeJgLDaFPpS6+W0EGGZGHAErwjDsdrI=; b=UZmaVEwhR+fLcqa85os+roDGzcbG6VCm/dfei/dARtBhYI0+i3QbB3SEaBnxW50R9A hKDQhxbIZ0UkXvfJaD5R2eNnW6vpMVYelWoTji6KY10aHYcyGj3xYy1x6vcIiX3ioM2Q JuCVnr9OmKlWFV5sT1lKcE+yJbnnu8bB3M+g6XhWSaPVHxyPbzsTTouaQSxTpnTknYW3 IXJJJxXU5x8dpPmJ+e6DSDEc3NMuFWdiZfRkVolxt6mYtjMpjfy9G6DRxiDQ5E7C0h7o LucDr8j/4DQ4l3HjLI3oznLnKEWwVuRsRcX42s+pF9xOraE1G9KiZpd6EnZoaEOyr++x +K9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=7aPlccAojcftVeJgLDaFPpS6+W0EGGZGHAErwjDsdrI=; b=cuMzn02OGeUDKhwly8DYTvJzmRPPsb9RC6aP43LKElJYWwa26ll1hFRhfKO2En0Lz5 hF0PBoIxmpxeJbXIRPpWItI+zzoxFkorY3XWc3lSW44+oiJBIXZnwpXMgw0tSYsNyrWM ChYQaCZXtBkV+bYMUTXuOjHCm5JF6R5ujaC0sBJM427myBu01P0UomefXK9Fv3c3JIKF Qf7VY88EvkbfGuBswIX2KYqQ2Qt8qzWxMQnHN8ICQvdNsB79GgZk3IJf/hkXCpARwQun qt4UaHHU+OpkF5IvuQyR/fcBejHbolPzxwf73NXzPK+sNUo/wV+Qrd/n1s6L9FwxRrwQ VAmA== X-Gm-Message-State: AOAM531+dNQLaUdT8rMbXrch872TL6plxOtb76lhR2kUAt3yvOFReLfH /WWuNHsQ5lgcp1tCG/1DnSD3kA== X-Google-Smtp-Source: ABdhPJzcQYjoymyrqRNiiqRlh5fD9evj8kvUEHfgwym6ycLhugHL4OILwNBQFRA0hFTt1ARnPflJzA== X-Received: by 2002:a05:600c:4f8f:: with SMTP id n15mr5809716wmq.70.1636452397669; Tue, 09 Nov 2021 02:06:37 -0800 (PST) Return-Path: Received: from sunil-ThinkPad-T490 ([49.206.3.187]) by smtp.gmail.com with ESMTPSA id h18sm20941614wre.46.2021.11.09.02.06.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Nov 2021 02:06:37 -0800 (PST) Date: Tue, 9 Nov 2021 15:36:31 +0530 From: "Sunil V L" To: Abner Chang Cc: devel@edk2.groups.io, Daniel Schaefer Subject: Re: [edk2-platforms][PATCH 00/30] EDK2 RISC-V port with opensbi v0.9 Message-ID: <20211109100631.GA59028@sunil-ThinkPad-T490> References: <20211019081007.31165-1-abner.chang@hpe.com> MIME-Version: 1.0 In-Reply-To: <20211019081007.31165-1-abner.chang@hpe.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline The patch set looks good to me. Reviewed-by: Sunil V L On Tue, Oct 19, 2021 at 04:09:37PM +0800, Abner Chang wrote: > This is the patch set to incorporate opensbi v0.9 with edk2 > RISC-V port. There are many architecture changes to compliant > with the RISC-V SBI implementation (opensbi) and also provide the > flexibility to OEM platform. > > Below is the summary of major changes. You can also refer to patch (1/31) > to understand the architecture design. > > - Flexibly support privilege modes for edk2 execution phases using PCD. > - M-mode SEC then S-mode all the way to boot OS. > - M-mode SEC and PEI, then S-mode for DXE to boot OS. > - M-mode firmware all the way to S-mode OS. > Default is M-mode SEC then S-mode all the way to boot OS. > Still have to implemente priviledge mode switching for PEI to DXE and > BDSto Boot OS. > > - Apply opensbi firmware domain solution to protect firmware regions using > FDF/PCD. > > - Provide Platform SEC PPI library that can be executed in either M-mode or > S-mode PEI phases according to OEM platform definition. > > - Determine boot hart using Device Tree or PCD. This allows OEM to > flexibly select the desired HARTs for booting system. Non-boot HARTs > can be used for other applications/purposes. > > - Provide an edk2 library wrapper of opensbi platform functions. This > allows OEM to have procedures that hooks before or after the certain > opensbi platform functions. > > - Other patches to adopt opensbi v0.9. > > Cc: Sunil V L > Cc: Daniel Schaefer > Signed-off-by: Abner Chang > > Abner Chang (30): > RISC-V/PlatformPkg: Update document > RISC-V: Add RISC-V PeiCoreEntryPoint library > RISC-V: Create opensbi firmware domains > RISC-V: Use RISC-V PeiCoreEntryPoint library > Platform/RISC-V: Add library to get PPI descriptor > Platform/U540: Provide PlatormSecPpiLib > Platform/RISC-V: Use PlatformSecPpiLib > Platform/SiFive: CoreInfoHob uses RiscVFirmwareContextLib > SiFive/U5SeriesPkg: Add CLINT to Device Tree > Platform/RISC-V: Add NULL library instance of RiscVSpecialPlatformLib > SiFive/U540: RiscVSpecialPlatformLib instance of U540 > Platform/RISC-V: Remove platform dependency from this library > Platform/RISC-V: Remove Null instance of OpensbilatformLibNull > RiscVPlatformPkg/Sec: Initial hart_index2Id array > RiscVPlatformPkg/OpensbiPlatformLib: Remove platform code > RiscVPlatformPkg/U540: Only use four harts on U540 > U5SeriesPkg/PeiCoreInfoHob: Remove hart count check > RiscVPlatformPkg/RiscVSpecialPlatformLib: Rename module name > RiscVPlatformPkg/U540: Add SortLib > ProcessorPkg/opensbi: Update opensbi library > RiscVPlatformPkg/Sec: Check Cold/Warm hart > RiscVPlatformPkg/Sec: Add more comments to Secmain.c > RiscV/ProcessorPkg: Create read mtime CSR library instances > RiscV/ProcessorPkg: Use mtime CSR library > Silicon/SiFive: Use mtime CSR library > SiFive/SerialPortLib: Remove global variable > RISC-V/PlatformPkg: Updates for the latest OpenSBI > RiscVPlatformPkg/Sec: Separate EDK2 Opensbi platform hook. > RISC-V/PlatformPkg: Determine hart number from DTB > Silicon/RISC-V: Add PciCpuIoDxe driver > > .../RISC-V/PlatformPkg/RiscVPlatformPkg.dec | 52 +- > .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 1 + > .../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 20 +- > .../FreedomU500VC707Board/U500.dsc | 1 + > .../FreedomU540HiFiveUnleashedBoard/U540.dsc | 11 +- > .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dsc | 3 + > .../U540.fdf.inc | 94 +- > .../VarStore.fdf.inc | 8 +- > .../Edk2OpensbiPlatformWrapperLib.inf | 44 + > .../OpensbiPlatformLib/OpensbiPlatformLib.inf | 11 +- > .../OpensbiPlatformLibNull.inf | 38 - > .../PeiCoreEntryPoint/PeiCoreEntryPoint.inf | 37 + > .../PlatformSecPpiLibNull.inf | 36 + > .../RiscVSpecialPlatformLibNull.inf | 36 + > .../PlatformPkg/Universal/Sec/SecMain.inf | 15 +- > .../RiscVSpecialPlatformLib.inf | 36 + > .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 3 +- > .../PlatformSecPpiLib/PlatformSecPpiLib.inf | 43 + > .../Universal/Dxe/TimerDxe/TimerDxe.inf | 1 + > .../EmulatedMachineModeTimerLib.inf | 34 + > .../MachineModeTimerLib.inf | 38 + > .../RiscVTimerLib/BaseRiscVTimerLib.inf | 3 +- > .../ProcessorPkg/Universal/CpuDxe/CpuDxe.inf | 1 + > .../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 47 + > .../Library/Edk2OpensbiPlatformWrapperLib.h | 16 + > .../Include/Library/PlatformSecPpiLib.h | 24 + > .../Include/Library/RiscVSpecialPlatformLib.h | 20 + > .../OpensbiPlatformLib/PlatformOverride.h | 30 - > .../PlatformPkg/Universal/Sec/SecMain.h | 28 +- > .../SiFive/U5SeriesPkg/Include/SifiveU5Uart.h | 1 + > .../Include/IndustryStandard/RiscV.h | 5 + > .../Include/IndustryStandard/RiscVOpensbi.h | 8 +- > .../Include/Library/RiscVCpuLib.h | 3 + > .../Edk2OpensbiPlatformWrapperLib.c | 530 +++++ > .../Library/OpensbiPlatformLib/Platform.c | 77 +- > .../Library/OpensbiPlatformLibNull/Platform.c | 51 - > .../PeiCoreEntryPoint/PeiCoreEntryPoint.c | 108 + > .../PlatformSecPpiLibNull/PlatformSecPpiLib.c | 28 + > .../RiscVSpecialPlatformLib.c | 20 + > .../PlatformPkg/Universal/Sec/SecMain.c | 268 +-- > .../RiscVSpecialPlatformLib}/SifiveFu540.c | 11 +- > .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 9 +- > .../PlatformSecPpiLib/PlatformSecPpiLib.c | 148 ++ > .../Library/SerialIoLib/SerialPortLib.c | 58 +- > .../Universal/Dxe/TimerDxe/Timer.c | 14 +- > .../Library/RiscVTimerLib/RiscVTimerLib.c | 6 +- > .../ProcessorPkg/Universal/CpuDxe/CpuDxe.c | 2 +- > .../Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 554 +++++ > .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 6 +- > Platform/RISC-V/PlatformPkg/Readme.md | 132 +- > .../Documents/Media/RiscVEdk2BootProcess.svg | 1928 +++++++++++++++++ > .../Documents/Media/RiscVEdk2FwDomain.svg | 1290 +++++++++++ > .../PeiCoreEntryPoint/PeiCoreEntryPoint.uni | 14 + > .../Universal/Sec/Riscv64/SecEntry.S | 372 ++-- > .../DeviceTree/fu540-c000.dtsi | 591 ++--- > .../Library/RiscVOpensbiLib/opensbi | 2 +- > .../EmulatedMachineModeTimerLib.S | 24 + > .../MachineModeTimerLib/MachineModeTimerLib.S | 25 + > 58 files changed, 6105 insertions(+), 911 deletions(-) > create mode 100644 Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf > delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf > create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf > create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLibNull.inf > create mode 100644 Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf > create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf > create mode 100644 Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.inf > create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf > create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.inf > create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.inf > create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/Edk2OpensbiPlatformWrapperLib.h > create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/PlatformSecPpiLib.h > create mode 100644 Platform/RISC-V/PlatformPkg/Include/Library/RiscVSpecialPlatformLib.h > delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/PlatformOverride.h > create mode 100644 Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.c > delete mode 100644 Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLibNull/Platform.c > create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.c > create mode 100644 Platform/RISC-V/PlatformPkg/Library/PlatformSecPpiLibNull/PlatformSecPpiLib.c > create mode 100644 Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c > rename Platform/{RISC-V/PlatformPkg/Library/OpensbiPlatformLib => SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/RiscVSpecialPlatformLib}/SifiveFu540.c (76%) > create mode 100644 Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.c > create mode 100644 Silicon/RISC-V/ProcessorPkg/Universal/PciCpuIo2Dxe/PciCpuIo2Dxe.c > create mode 100644 Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2BootProcess.svg > create mode 100644 Platform/RISC-V/PlatformPkg/Documents/Media/RiscVEdk2FwDomain.svg > create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.uni > create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.S > create mode 100644 Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/MachineModeTimerLib/MachineModeTimerLib.S > > -- > 2.31.1 >