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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT066.mail.protection.outlook.com (10.13.177.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4690.15 via Frontend Transport; Wed, 10 Nov 2021 22:15:19 +0000 Received: from sbrijesh-desktop.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Wed, 10 Nov 2021 16:15:18 -0600 From: "Brijesh Singh" To: CC: James Bottomley , Min Xu , "Jiewen Yao" , Tom Lendacky , "Jordan Justen" , Ard Biesheuvel , Erdem Aktas , "Michael Roth" , Gerd Hoffmann , "Michael D Kinney" , Liming Gao , Zhiguang Liu , Ray Ni , Rahul Kumar , Eric Dong , Michael Roth , Jiewen Yao , Brijesh Singh Subject: [PATCH v12 11/32] OvmfPkg/VmgExitLib: use SEV-SNP-validated CPUID values Date: Wed, 10 Nov 2021 16:14:36 -0600 Message-ID: <20211110221457.2397234-12-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211110221457.2397234-1-brijesh.singh@amd.com> References: <20211110221457.2397234-1-brijesh.singh@amd.com> MIME-Version: 1.0 Return-Path: brijesh.singh@amd.com X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: df5b9981-cceb-4c52-ff76-08d9a4979536 X-MS-TrafficTypeDiagnostic: BY5PR12MB3652: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Nov 2021 22:15:19.9632 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: df5b9981-cceb-4c52-ff76-08d9a4979536 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT066.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3652 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Michael Roth SEV-SNP firmware allows a special guest page to be populated with guest CPUID values so that they can be validated against supported host features before being loaded into encrypted guest memory to be used instead of hypervisor-provided values [1]. Add handling for this in the CPUID #VC handler and use it whenever SEV-SNP is enabled. To do so, existing CPUID handling via VmgExit is moved to a helper, GetCpuidHyp(), and a new helper that uses the CPUID page to do the lookup, GetCpuidFw(), is used instead when SNP is enabled. For cases where SNP CPUID lookups still rely on fetching specific CPUID fields from hypervisor, GetCpuidHyp() is used there as well. [1]: SEV SNP Firmware ABI Specification, Rev. 0.8, 8.13.2.6 Cc: James Bottomley Cc: Min Xu Cc: Jiewen Yao Cc: Tom Lendacky Cc: Jordan Justen Cc: Ard Biesheuvel Cc: Erdem Aktas Cc: Gerd Hoffmann Acked-by: Jiewen Yao Acked-by: Gerd Hoffmann Signed-off-by: Michael Roth Signed-off-by: Brijesh Singh --- OvmfPkg/Library/VmgExitLib/SecVmgExitLib.inf | 2 + OvmfPkg/Library/VmgExitLib/VmgExitLib.inf | 3 + OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 444 ++++++++++++++++-- 3 files changed, 419 insertions(+), 30 deletions(-) diff --git a/OvmfPkg/Library/VmgExitLib/SecVmgExitLib.inf b/OvmfPkg/Library= /VmgExitLib/SecVmgExitLib.inf index e6f6ea7972fd..78207fa0f9c9 100644 --- a/OvmfPkg/Library/VmgExitLib/SecVmgExitLib.inf +++ b/OvmfPkg/Library/VmgExitLib/SecVmgExitLib.inf @@ -42,4 +42,6 @@ [LibraryClasses] [FixedPcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidSize =20 diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitLib.inf b/OvmfPkg/Library/Vm= gExitLib/VmgExitLib.inf index c66c68726cdb..7963670e7d30 100644 --- a/OvmfPkg/Library/VmgExitLib/VmgExitLib.inf +++ b/OvmfPkg/Library/VmgExitLib/VmgExitLib.inf @@ -38,3 +38,6 @@ [LibraryClasses] LocalApicLib MemEncryptSevLib =20 +[Pcd] + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidSize diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c b/OvmfPkg/Librar= y/VmgExitLib/VmgExitVcHandler.c index 41b0c8cc5312..7fbd986fb012 100644 --- a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c +++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c @@ -17,6 +17,7 @@ #include =20 #include "VmgExitVcHandler.h" +//#include =20 // // Instruction execution mode definition @@ -130,6 +131,32 @@ UINT64 SEV_ES_INSTRUCTION_DATA *InstructionData ); =20 +// +// SEV-SNP Cpuid table entry/function +// +typedef PACKED struct { + UINT32 EaxIn; + UINT32 EcxIn; + UINT64 Unused; + UINT64 Unused2; + UINT32 Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; + UINT64 Reserved; +} SEV_SNP_CPUID_FUNCTION; + +// +// SEV-SNP Cpuid page format +// +typedef PACKED struct { + UINT32 Count; + UINT32 Reserved1; + UINT64 Reserved2; + SEV_SNP_CPUID_FUNCTION function[0]; +} SEV_SNP_CPUID_INFO; + + /** Return a pointer to the contents of the specified register. =20 @@ -1496,58 +1523,415 @@ InvdExit ( } =20 /** - Handle a CPUID event. + Fetch CPUID leaf/function via hypervisor/VMGEXIT. =20 - Use the VMGEXIT instruction to handle a CPUID event. + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communicati= on + Block + @param[in] EaxIn EAX input for cpuid instruction + @param[in] EcxIn ECX input for cpuid instruction + @param[in] Xcr0In XCR0 at time of cpuid instruction + @param[in, out] Eax Pointer to store leaf's EAX value + @param[in, out] Ebx Pointer to store leaf's EBX value + @param[in, out] Ecx Pointer to store leaf's ECX value + @param[in, out] Edx Pointer to store leaf's EDX value + @param[in, out] Status Pointer to store status from VMGEXIT (alway= s 0 + unless return value indicates failure) + @param[in, out] Unsupported Pointer to store indication of unsupported + VMGEXIT (always false unless return value + indicates failure) =20 - @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communi= cation - Block - @param[in, out] Regs x64 processor context - @param[in] InstructionData Instruction parsing context - - @retval 0 Event handled successfully - @return New exception value to propagate + @retval TRUE CPUID leaf fetch successfully. + @retval FALSE Error occurred while fetching CPUID leaf. C= allers + should Status and Unsupported and handle + accordingly if they indicate a more precise + error condition. =20 **/ STATIC -UINT64 -CpuidExit ( +BOOLEAN +GetCpuidHyp ( IN OUT GHCB *Ghcb, - IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, - IN SEV_ES_INSTRUCTION_DATA *InstructionData + IN UINT32 EaxIn, + IN UINT32 EcxIn, + IN UINT64 XCr0, + IN OUT UINT32 *Eax, + IN OUT UINT32 *Ebx, + IN OUT UINT32 *Ecx, + IN OUT UINT32 *Edx, + IN OUT UINT64 *Status, + IN OUT BOOLEAN *UnsupportedExit ) { - UINT64 Status; - - Ghcb->SaveArea.Rax =3D Regs->Rax; + *UnsupportedExit =3D FALSE; + Ghcb->SaveArea.Rax =3D EaxIn; VmgSetOffsetValid (Ghcb, GhcbRax); - Ghcb->SaveArea.Rcx =3D Regs->Rcx; + Ghcb->SaveArea.Rcx =3D EcxIn; VmgSetOffsetValid (Ghcb, GhcbRcx); - if (Regs->Rax =3D=3D CPUID_EXTENDED_STATE) { - IA32_CR4 Cr4; - - Cr4.UintN =3D AsmReadCr4 (); - Ghcb->SaveArea.XCr0 =3D (Cr4.Bits.OSXSAVE =3D=3D 1) ? AsmXGetBv (0) : = 1; + if (EaxIn =3D=3D CPUID_EXTENDED_STATE) { + Ghcb->SaveArea.XCr0 =3D XCr0; VmgSetOffsetValid (Ghcb, GhcbXCr0); } =20 - Status =3D VmgExit (Ghcb, SVM_EXIT_CPUID, 0, 0); - if (Status !=3D 0) { - return Status; + *Status =3D VmgExit (Ghcb, SVM_EXIT_CPUID, 0, 0); + if (*Status !=3D 0) { + return FALSE; } =20 if (!VmgIsOffsetValid (Ghcb, GhcbRax) || !VmgIsOffsetValid (Ghcb, GhcbRbx) || !VmgIsOffsetValid (Ghcb, GhcbRcx) || !VmgIsOffsetValid (Ghcb, GhcbRdx)) { - return UnsupportedExit (Ghcb, Regs, InstructionData); + *UnsupportedExit =3D TRUE; + return FALSE; } - Regs->Rax =3D Ghcb->SaveArea.Rax; - Regs->Rbx =3D Ghcb->SaveArea.Rbx; - Regs->Rcx =3D Ghcb->SaveArea.Rcx; - Regs->Rdx =3D Ghcb->SaveArea.Rdx; + + if (Eax) { + *Eax =3D (UINT32) (UINTN) Ghcb->SaveArea.Rax; + } + if (Ebx) { + *Ebx =3D (UINT32) (UINTN) Ghcb->SaveArea.Rbx; + } + if (Ecx) { + *Ecx =3D (UINT32) (UINTN) Ghcb->SaveArea.Rcx; + } + if (Edx) { + *Edx =3D (UINT32) (UINTN) Ghcb->SaveArea.Rdx; + } + + return TRUE; +} + +/** + Check if SEV-SNP enabled. + + @retval TRUE SEV-SNP is enabled. + @retval FALSE SEV-SNP is disabled. + +**/ +STATIC +BOOLEAN +SnpEnabled (VOID) +{ + MSR_SEV_STATUS_REGISTER Msr; + + Msr.Uint32 =3D AsmReadMsr32(MSR_SEV_STATUS); + + return !!Msr.Bits.SevSnpBit; +} + +/** + Calculate the total XSAVE area size for enabled XSAVE areas + + @param[in] XFeaturesEnabled Bit-mask of enabled XSAVE features/are= as as + indicated by XCR0/MSR_IA32_XSS bits + @param[in] XSaveBaseSize Base/legacy XSAVE area size (e.g. when + XCR0 is 1) + @param[in, out] XSaveSize Pointer to storage for calculated XSAV= E area + size + @param[in] Compacted Whether or not the calculation is for = the + normal XSAVE area size (leaf 0xD,0x0,E= BX) or + compacted XSAVE area size (leaf 0xD,0x= 1,EBX) + + + @retval TRUE XSAVE size calculation was successful. + @retval FALSE XSAVE size calculation was unsuccessfu= l. +**/ +STATIC +BOOLEAN +GetCpuidXSaveSize ( + IN UINT64 XFeaturesEnabled, + IN UINT32 XSaveBaseSize, + IN OUT UINT32 *XSaveSize, + IN BOOLEAN Compacted + ) +{ + SEV_SNP_CPUID_INFO *CpuidInfo; + UINT64 XFeaturesFound =3D 0; + UINT32 Idx; + + *XSaveSize =3D XSaveBaseSize; + CpuidInfo =3D (SEV_SNP_CPUID_INFO *)(UINT64)PcdGet32(PcdOvmfCpuidBase); + + for (Idx =3D 0; Idx < CpuidInfo->Count; Idx++) { + SEV_SNP_CPUID_FUNCTION *CpuidFn =3D &CpuidInfo->function[Idx]; + + if (!(CpuidFn->EaxIn =3D=3D 0xD && + (CpuidFn->EcxIn =3D=3D 0 || CpuidFn->EcxIn =3D=3D 1))) { + continue; + } + + if (XFeaturesFound & (1ULL << CpuidFn->EcxIn) || + !(XFeaturesEnabled & (1ULL << CpuidFn->EcxIn))) { + continue; + } + + XFeaturesFound |=3D (1ULL << CpuidFn->EcxIn); + if (Compacted) { + *XSaveSize +=3D CpuidFn->Eax; + } else { + *XSaveSize =3D MAX(*XSaveSize, CpuidFn->Eax + CpuidFn->Ebx); + } + } + + /* + * Either the guest set unsupported XCR0/XSS bits, or the corresponding + * entries in the CPUID table were not present. This is an invalid state= . + */ + if (XFeaturesFound !=3D (XFeaturesEnabled & ~3UL)) { + return FALSE; + } + + return TRUE; +} + +/** + Check if a CPUID leaf/function is indexed via ECX sub-leaf/sub-function + + @param[in] EaxIn EAX input for cpuid instruction + + @retval FALSE cpuid leaf/function is not indexed by ECX i= nput + @retval TRUE cpuid leaf/function is indexed by ECX input + +**/ +STATIC +BOOLEAN +IsFunctionIndexed ( + IN UINT32 EaxIn + ) +{ + switch (EaxIn) { + case CPUID_CACHE_PARAMS: + case CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS: + case CPUID_EXTENDED_TOPOLOGY: + case CPUID_EXTENDED_STATE: + case CPUID_INTEL_RDT_MONITORING: + case CPUID_INTEL_RDT_ALLOCATION: + case CPUID_INTEL_SGX: + case CPUID_INTEL_PROCESSOR_TRACE: + case CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS: + case CPUID_V2_EXTENDED_TOPOLOGY: + case 0x8000001D: /* Cache Topology Information */ + return TRUE; + } + return FALSE; +} + +/** + Fetch CPUID leaf/function via SEV-SNP CPUID table. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communicati= on + Block + @param[in] EaxIn EAX input for cpuid instruction + @param[in] EcxIn ECX input for cpuid instruction + @param[in] Xcr0In XCR0 at time of cpuid instruction + @param[in, out] Eax Pointer to store leaf's EAX value + @param[in, out] Ebx Pointer to store leaf's EBX value + @param[in, out] Ecx Pointer to store leaf's ECX value + @param[in, out] Edx Pointer to store leaf's EDX value + @param[in, out] Status Pointer to store status from VMGEXIT (alway= s 0 + unless return value indicates failure) + @param[in, out] Unsupported Pointer to store indication of unsupported + VMGEXIT (always false unless return value + indicates failure) + + @retval TRUE CPUID leaf fetch successfully. + @retval FALSE Error occurred while fetching CPUID leaf. C= allers + should Status and Unsupported and handle + accordingly if they indicate a more precise + error condition. + +**/ +STATIC +BOOLEAN +GetCpuidFw ( + IN OUT GHCB *Ghcb, + IN UINT32 EaxIn, + IN UINT32 EcxIn, + IN UINT64 XCr0, + IN OUT UINT32 *Eax, + IN OUT UINT32 *Ebx, + IN OUT UINT32 *Ecx, + IN OUT UINT32 *Edx, + IN OUT UINT64 *Status, + IN OUT BOOLEAN *Unsupported + ) +{ + SEV_SNP_CPUID_INFO *CpuidInfo; + BOOLEAN Found; + UINT32 Idx; + + CpuidInfo =3D (SEV_SNP_CPUID_INFO *)(UINT64)PcdGet32(PcdOvmfCpuidBase); + Found =3D FALSE; + + for (Idx =3D 0; Idx < CpuidInfo->Count; Idx++) { + SEV_SNP_CPUID_FUNCTION *CpuidFn =3D &CpuidInfo->function[Idx]; + + if (CpuidFn->EaxIn !=3D EaxIn) { + continue; + } + + if (IsFunctionIndexed(CpuidFn->EaxIn) && CpuidFn->EcxIn !=3D EcxIn) { + continue; + } + + *Eax =3D CpuidFn->Eax; + *Ebx =3D CpuidFn->Ebx; + *Ecx =3D CpuidFn->Ecx; + *Edx =3D CpuidFn->Edx; + + Found =3D TRUE; + break; + } + + if (!Found) { + *Eax =3D *Ebx =3D *Ecx =3D *Edx =3D 0; + goto Out; + } + + if (EaxIn =3D=3D CPUID_VERSION_INFO) { + IA32_CR4 Cr4; + UINT32 Ebx2; + UINT32 Edx2; + + if (!GetCpuidHyp (Ghcb, EaxIn, EcxIn, XCr0, NULL, &Ebx2, NULL, &Edx2, + Status, Unsupported)) { + return FALSE; + } + + /* initial APIC ID */ + *Ebx =3D (*Ebx & 0x00FFFFFF) | (Ebx2 & 0xFF000000); + /* APIC enabled bit */ + *Edx =3D (*Edx & ~BIT9) | (Edx2 & BIT9); + /* OSXSAVE enabled bit */ + Cr4.UintN =3D AsmReadCr4 (); + *Ecx =3D (Cr4.Bits.OSXSAVE) ? (*Ecx & ~BIT27) | (*Ecx & BIT27) + : (*Ecx & ~BIT27); + } else if (EaxIn =3D=3D CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS) { + IA32_CR4 Cr4; + + Cr4.UintN =3D AsmReadCr4 (); + /* OSPKE enabled bit */ + *Ecx =3D (Cr4.Bits.PKE) ? (*Ecx | BIT4) : (*Ecx & ~BIT4); + } else if (EaxIn =3D=3D CPUID_EXTENDED_TOPOLOGY) { + if (!GetCpuidHyp (Ghcb, EaxIn, EcxIn, XCr0, NULL, NULL, NULL, Edx, + Status, Unsupported)) { + return FALSE; + } + } else if (EaxIn =3D=3D CPUID_EXTENDED_STATE && (EcxIn =3D=3D 0 || EcxIn= =3D=3D 1)) { + MSR_IA32_XSS_REGISTER XssMsr; + BOOLEAN Compacted; + UINT32 XSaveSize; + + XssMsr.Uint64 =3D 0; + if (EcxIn =3D=3D 1) { + /* + * The PPR and APM aren't clear on what size should be encoded in + * 0xD:0x1:EBX when compaction is not enabled by either XSAVEC or + * XSAVES, as these are generally fixed to 1 on real CPUs. Report + * this undefined case as an error. + */ + if (!(*Eax & (BIT3 | BIT1))) { /* (XSAVES | XSAVEC) */ + return FALSE; + } + + Compacted =3D TRUE; + XssMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_XSS); + } + + if (!GetCpuidXSaveSize (XCr0 | XssMsr.Uint64, *Ebx, &XSaveSize, + Compacted)) { + return FALSE; + } + + *Ebx =3D XSaveSize; + } else if (EaxIn =3D=3D 0x8000001E) { + UINT32 Ebx2; + UINT32 Ecx2; + + /* extended APIC ID */ + if (!GetCpuidHyp (Ghcb, EaxIn, EcxIn, XCr0, Eax, &Ebx2, &Ecx2, NULL, + Status, Unsupported)) { + return FALSE; + } + /* compute ID */ + *Ebx =3D (*Ebx & 0xFFFFFF00) | (Ebx2 & 0x000000FF); + /* node ID */ + *Ecx =3D (*Ecx & 0xFFFFFF00) | (Ecx2 & 0x000000FF); + } + +Out: + *Status =3D 0; + *Unsupported =3D FALSE; + return TRUE; +} + +/** + Handle a CPUID event. + + Use VMGEXIT instruction or CPUID table to handle a CPUID event. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communi= cation + Block + @param[in, out] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @retval 0 Event handled successfully + @return New exception value to propagate + +**/ +STATIC +UINT64 +CpuidExit ( + IN OUT GHCB *Ghcb, + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + BOOLEAN Unsupported; + UINT64 Status; + UINT32 EaxIn; + UINT32 EcxIn; + UINT64 XCr0; + UINT32 Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; + + EaxIn =3D (UINT32) (UINTN) Regs->Rax; + EcxIn =3D (UINT32) (UINTN) Regs->Rcx; + + if (EaxIn =3D=3D CPUID_EXTENDED_STATE) { + IA32_CR4 Cr4; + + Cr4.UintN =3D AsmReadCr4 (); + XCr0 =3D (Cr4.Bits.OSXSAVE =3D=3D 1) ? AsmXGetBv (0) : 1; + } + + if (SnpEnabled ()) { + if (!GetCpuidFw (Ghcb, EaxIn, EcxIn, XCr0, &Eax, &Ebx, &Ecx, &Edx, + &Status, &Unsupported)) { + goto CpuidFail; + } + } else { + if (!GetCpuidHyp (Ghcb, EaxIn, EcxIn, XCr0, &Eax, &Ebx, &Ecx, &Edx, + &Status, &Unsupported)) { + goto CpuidFail; + } + } + + Regs->Rax =3D Eax; + Regs->Rbx =3D Ebx; + Regs->Rcx =3D Ecx; + Regs->Rdx =3D Edx; =20 return 0; + +CpuidFail: + if (Unsupported) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + + return Status; } =20 /** --=20 2.25.1