From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-002e3701.pphosted.com (mx0b-002e3701.pphosted.com [148.163.143.35]) by mx.groups.io with SMTP id smtpd.web11.18030.1636948560211227513 for ; Sun, 14 Nov 2021 19:56:05 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=lmqx2N1I; spf=temperror, err=temporary DNS error (domain: hpe.com, ip: 148.163.143.35, mailfrom: prvs=0953f1bc5c=abner.chang@hpe.com) Received: from pps.filterd (m0134424.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 1AEKooSD029985; Mon, 15 Nov 2021 03:55:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pps0720; bh=CVk1uJ6jLEwjkyf9d3awrwB4cP1hYJRshSCBsZOE4Kk=; b=lmqx2N1IJtpDdX6WGUOZVQjSTZ5BKvkYpQEBzHQAKD34DYzGqHpX2OglvU5z15r1CvK+ W4QZRopibWARqElFbLDsWGcGW+DBWZdqpLZr6/25qVwKa/rs0xf6sW3CIJujhMb5z/VO /UHgZ/F2XLNBaHPwN4+i5b3SNddR5PkfeW8Q1Qd8eNXXHDmCQ10cud0IQEY4sDV8Vhqh 4YSqXScjk1jalkn8s1XyX/otG9Eb+kAj7nWTy8OfO3oSjaT1eL9jdEiixOu763gmHDki AEnCCgWiIbEiAa/WakUrnUNDf77qpTvyyeiv+cuMgbFsjQpFHuhZccESWrhIV8niuWL3 wA== Received: from g2t2353.austin.hpe.com (g2t2353.austin.hpe.com [15.233.44.26]) by mx0b-002e3701.pphosted.com with ESMTP id 3ca4bsushc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 15 Nov 2021 03:55:59 +0000 Received: from g2t2360.austin.hpecorp.net (g2t2360.austin.hpecorp.net [16.196.225.135]) by g2t2353.austin.hpe.com (Postfix) with ESMTP id 9A9446D; Mon, 15 Nov 2021 03:55:58 +0000 (UTC) Received: from UB16Abner.asiapacific.hpqcorp.net (ub16abner.asiapacific.hpqcorp.net [15.119.209.229]) by g2t2360.austin.hpecorp.net (Postfix) with ESMTP id 8C31636; Mon, 15 Nov 2021 03:55:57 +0000 (UTC) From: "Abner Chang" To: devel@edk2.groups.io Cc: abner.chang@hpe.com, Daniel Schaefer , Sunil V L Subject: [edk2-platforms][PATCH 11/14] RiscVPlatformPkg/U500: Add device tree for U500 platform Date: Mon, 15 Nov 2021 10:56:37 +0800 Message-Id: <20211115025640.12897-12-abner.chang@hpe.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211115025640.12897-1-abner.chang@hpe.com> References: <20211115025640.12897-1-abner.chang@hpe.com> MIME-Version: 1.0 X-Proofpoint-GUID: EGN1Hu0sfH2QFtgt-iFE87c_AAqv_KLM X-Proofpoint-ORIG-GUID: EGN1Hu0sfH2QFtgt-iFE87c_AAqv_KLM X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-15_02,2021-11-12_01,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 mlxlogscore=999 phishscore=0 malwarescore=0 lowpriorityscore=0 mlxscore=0 adultscore=0 spamscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2111150021 Content-Transfer-Encoding: quoted-printable Signed-off-by: Abner Chang Cc: Daniel Schaefer Cc: Sunil V L --- .../DeviceTree/U500DeviceTree.inf | 25 ++ .../FreedomU500VC707Board/DeviceTree/gpio.h | 45 +++ .../DeviceTree/sifive-fu500-prci.h | 19 ++ .../DeviceTree/fu500-c000.dtsi | 276 ++++++++++++++++++ .../DeviceTree/hifive-unleashed-a00.dts | 108 +++++++ 5 files changed, 473 insertions(+) create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Devic= eTree/U500DeviceTree.inf create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Devic= eTree/gpio.h create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Devic= eTree/sifive-fu500-prci.h create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Devic= eTree/fu500-c000.dtsi create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Devic= eTree/hifive-unleashed-a00.dts diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/U= 500DeviceTree.inf b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Devic= eTree/U500DeviceTree.inf new file mode 100644 index 0000000000..3eeb8c51f4 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/U500Devi= ceTree.inf @@ -0,0 +1,25 @@ +## @file=0D +#=0D +# Device tree description of SiFive U500 VC707 platform=0D +#=0D +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001A=0D + BASE_NAME =3D U500DeviceTree=0D + FILE_GUID =3D 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDef= aultDtbFileGuid=0D + MODULE_TYPE =3D USER_DEFINED=0D + VERSION_STRING =3D 1.0=0D +=0D +[Sources]=0D + gpio.h=0D + hifive-unleashed-a00.dts=0D + fu500-c000.dtsi=0D + sifive-fu500-prci.h=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/g= pio.h b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/gpio.h new file mode 100644 index 0000000000..bc7e2fe7a1 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/gpio.h @@ -0,0 +1,45 @@ +/** @file=0D + This header provides constants for most GPIO bindings.=0D +=0D + Most GPIO bindings include a flags cell as part of the GPIO specifier.=0D + In most cases, the format of the flags cell uses the standard values=0D + defined in this header.=0D +=0D + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef DT_BINDINGS_GPIO_GPIO_H_=0D +#define DT_BINDINGS_GPIO_GPIO_H_=0D +=0D +/* Bit 0 express polarity */=0D +#define GPIO_ACTIVE_HIGH 0=0D +#define GPIO_ACTIVE_LOW 1=0D +=0D +/* Bit 1 express single-endedness */=0D +#define GPIO_PUSH_PULL 0=0D +#define GPIO_SINGLE_ENDED 2=0D +=0D +/* Bit 2 express Open drain or open source */=0D +#define GPIO_LINE_OPEN_SOURCE 0=0D +#define GPIO_LINE_OPEN_DRAIN 4=0D +=0D +//=0D +// Open Drain/Collector is the combination of single-ended open drain inte= rface.=0D +// Open Source/Emitter is the combination of single-ended open source inte= rface.=0D +//=0D +#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)=0D +#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)=0D +=0D +/* Bit 3 express GPIO suspend/resume and reset persistence */=0D +#define GPIO_PERSISTENT 0=0D +#define GPIO_TRANSITORY 8=0D +=0D +/* Bit 4 express pull up */=0D +#define GPIO_PULL_UP 16=0D +=0D +/* Bit 5 express pull down */=0D +#define GPIO_PULL_DOWN 32=0D +=0D +#endif=0D diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/s= ifive-fu500-prci.h b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Devi= ceTree/sifive-fu500-prci.h new file mode 100644 index 0000000000..7efa0006a0 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/sifive-f= u500-prci.h @@ -0,0 +1,19 @@ +/**@file + + SPDX-License-Identifier: (GPL-2.0 OR MIT) + Copyright (c) 2018-2019 SiFive, Inc + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU500_PRCI_H +#define __DT_BINDINGS_CLOCK_SIFIVE_FU500_PRCI_H + +/* Clock indexes for use by Device Tree data and the PRCI driver */ + +#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_TLCLK 3 + +#endif diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/f= u500-c000.dtsi b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTr= ee/fu500-c000.dtsi new file mode 100644 index 0000000000..82f10e71e0 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/fu500-c0= 00.dtsi @@ -0,0 +1,276 @@ +/**@file=0D + U500 VC707 Device Tree, compatible with fu540-c000 platform.=0D +=0D + SPDX-License-Identifier: (GPL-2.0 OR MIT)=0D + Copyright (c) 2018-2019 SiFive, Inc=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +/dts-v1/;=0D +=0D +#include "sifive-fu500-prci.h"=0D +=0D +/ {=0D + #address-cells =3D <2>;=0D + #size-cells =3D <2>;=0D + compatible =3D "sifive,fu540-c000", "sifive,fu540";=0D +=0D + aliases {=0D + serial0 =3D &uart0;=0D + ethernet0 =3D ð0;=0D + };=0D +=0D + chosen {=0D + };=0D +=0D + cpus {=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + cpu0: cpu@0 {=0D + compatible =3D "sifive,u54-mc", "sifive,rocket0", = "riscv";=0D + d-cache-block-size =3D <64>;=0D + d-cache-sets =3D <64>;=0D + d-cache-size =3D <32768>;=0D + d-tlb-sets =3D <1>;=0D + d-tlb-size =3D <32>;=0D + device_type =3D "cpu";=0D + i-cache-block-size =3D <64>;=0D + i-cache-sets =3D <64>;=0D + i-cache-size =3D <32768>;=0D + i-tlb-sets =3D <1>;=0D + i-tlb-size =3D <32>;=0D + mmu-type =3D "riscv,sv39";=0D + reg =3D <0>;=0D + riscv,isa =3D "rv64imafdc";=0D + tlb-split;=0D + next-level-cache =3D <&l2cache>;=0D + cpu0_intc: interrupt-controller {=0D + #interrupt-cells =3D <1>;=0D + compatible =3D "riscv,cpu-intc";=0D + interrupt-controller;=0D + };=0D + };=0D + cpu1: cpu@1 {=0D + compatible =3D "sifive,u54-mc", "sifive,rocket0", = "riscv";=0D + d-cache-block-size =3D <64>;=0D + d-cache-sets =3D <64>;=0D + d-cache-size =3D <32768>;=0D + d-tlb-sets =3D <1>;=0D + d-tlb-size =3D <32>;=0D + device_type =3D "cpu";=0D + i-cache-block-size =3D <64>;=0D + i-cache-sets =3D <64>;=0D + i-cache-size =3D <32768>;=0D + i-tlb-sets =3D <1>;=0D + i-tlb-size =3D <32>;=0D + mmu-type =3D "riscv,sv39";=0D + reg =3D <1>;=0D + riscv,isa =3D "rv64imafdc";=0D + tlb-split;=0D + next-level-cache =3D <&l2cache>;=0D + cpu1_intc: interrupt-controller {=0D + #interrupt-cells =3D <1>;=0D + compatible =3D "riscv,cpu-intc";=0D + interrupt-controller;=0D + };=0D + };=0D + cpu2: cpu@2 {=0D + compatible =3D "sifive,u54-mc", "sifive,rocket0", = "riscv";=0D + d-cache-block-size =3D <64>;=0D + d-cache-sets =3D <64>;=0D + d-cache-size =3D <32768>;=0D + d-tlb-sets =3D <1>;=0D + d-tlb-size =3D <32>;=0D + device_type =3D "cpu";=0D + i-cache-block-size =3D <64>;=0D + i-cache-sets =3D <64>;=0D + i-cache-size =3D <32768>;=0D + i-tlb-sets =3D <1>;=0D + i-tlb-size =3D <32>;=0D + mmu-type =3D "riscv,sv39";=0D + reg =3D <2>;=0D + riscv,isa =3D "rv64imafdc";=0D + tlb-split;=0D + next-level-cache =3D <&l2cache>;=0D + cpu2_intc: interrupt-controller {=0D + #interrupt-cells =3D <1>;=0D + compatible =3D "riscv,cpu-intc";=0D + interrupt-controller;=0D + };=0D + };=0D + cpu3: cpu@3 {=0D + compatible =3D "sifive,u54-mc", "sifive,rocket0", = "riscv";=0D + d-cache-block-size =3D <64>;=0D + d-cache-sets =3D <64>;=0D + d-cache-size =3D <32768>;=0D + d-tlb-sets =3D <1>;=0D + d-tlb-size =3D <32>;=0D + device_type =3D "cpu";=0D + i-cache-block-size =3D <64>;=0D + i-cache-sets =3D <64>;=0D + i-cache-size =3D <32768>;=0D + i-tlb-sets =3D <1>;=0D + i-tlb-size =3D <32>;=0D + mmu-type =3D "riscv,sv39";=0D + reg =3D <3>;=0D + riscv,isa =3D "rv64imafdc";=0D + tlb-split;=0D + next-level-cache =3D <&l2cache>;=0D + cpu3_intc: interrupt-controller {=0D + #interrupt-cells =3D <1>;=0D + compatible =3D "riscv,cpu-intc";=0D + interrupt-controller;=0D + };=0D + };=0D + };=0D + soc {=0D + #address-cells =3D <2>;=0D + #size-cells =3D <2>;=0D + compatible =3D "sifive,fu540-c000", "sifive,fu540", "simpl= e-bus";=0D + ranges;=0D + plic0: interrupt-controller@c000000 {=0D + #interrupt-cells =3D <1>;=0D + compatible =3D "sifive,plic-1.0.0";=0D + reg =3D <0x0 0xc000000 0x0 0x4000000>;=0D + riscv,ndev =3D <53>;=0D + interrupt-controller;=0D + interrupts-extended =3D <=0D + &cpu0_intc 0xffffffff &cpu0_intc 9=0D + &cpu1_intc 0xffffffff &cpu1_intc 9=0D + &cpu2_intc 0xffffffff &cpu2_intc 9=0D + &cpu3_intc 0xffffffff &cpu3_intc 9>;=0D + };=0D + prci: clock-controller@10000000 {=0D + compatible =3D "sifive,fu540-c000-prci";=0D + reg =3D <0x0 0x10000000 0x0 0x1000>;=0D + clocks =3D <&hfclk>, <&rtcclk>;=0D + #clock-cells =3D <1>;=0D + };=0D + uart0: serial@54000000 {=0D + compatible =3D "sifive,fu540-c000-uart", "sifive,u= art0";=0D + reg =3D <0x0 0x54000000 0x0 0x1000>;=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <4>;=0D + clocks =3D <&prci PRCI_CLK_TLCLK>;=0D + status =3D "disabled";=0D + };=0D + dma: dma@3000000 {=0D + compatible =3D "sifive,fu540-c000-pdma";=0D + reg =3D <0x0 0x3000000 0x0 0x8000>;=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <23 24 25 26 27 28 29 30>;=0D + #dma-cells =3D <1>;=0D + };=0D + i2c0: i2c@10030000 {=0D + compatible =3D "sifive,fu540-c000-i2c", "sifive,i2= c0";=0D + reg =3D <0x0 0x10030000 0x0 0x1000>;=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <50>;=0D + clocks =3D <&prci PRCI_CLK_TLCLK>;=0D + reg-shift =3D <2>;=0D + reg-io-width =3D <1>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + status =3D "disabled";=0D + };=0D + qspi0: spi@10040000 {=0D + compatible =3D "sifive,fu540-c000-spi", "sifive,sp= i0";=0D + reg =3D <0x0 0x10040000 0x0 0x1000=0D + 0x0 0x20000000 0x0 0x10000000>;=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <51>;=0D + clocks =3D <&prci PRCI_CLK_TLCLK>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + status =3D "disabled";=0D + };=0D + qspi1: spi@10041000 {=0D + compatible =3D "sifive,fu540-c000-spi", "sifive,sp= i0";=0D + reg =3D <0x0 0x10041000 0x0 0x1000=0D + 0x0 0x30000000 0x0 0x10000000>;=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <52>;=0D + clocks =3D <&prci PRCI_CLK_TLCLK>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + status =3D "disabled";=0D + };=0D + qspi2: spi@10050000 {=0D + compatible =3D "sifive,fu540-c000-spi", "sifive,sp= i0";=0D + reg =3D <0x0 0x10050000 0x0 0x1000>;=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <6>;=0D + clocks =3D <&prci PRCI_CLK_TLCLK>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + status =3D "disabled";=0D + };=0D + eth0: ethernet@10090000 {=0D + compatible =3D "sifive,fu540-c000-gem";=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <53>;=0D + reg =3D <0x0 0x10090000 0x0 0x2000=0D + 0x0 0x100a0000 0x0 0x1000>;=0D + local-mac-address =3D [00 00 00 00 00 00];=0D + clock-names =3D "pclk", "hclk";=0D + clocks =3D <&prci PRCI_CLK_GEMGXLPLL>,=0D + <&prci PRCI_CLK_GEMGXLPLL>;=0D + #address-cells =3D <1>;=0D + #size-cells =3D <0>;=0D + status =3D "disabled";=0D + };=0D + pwm0: pwm@10020000 {=0D + compatible =3D "sifive,fu540-c000-pwm", "sifive,pw= m0";=0D + reg =3D <0x0 0x10020000 0x0 0x1000>;=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <42 43 44 45>;=0D + clocks =3D <&prci PRCI_CLK_TLCLK>;=0D + #pwm-cells =3D <3>;=0D + status =3D "disabled";=0D + };=0D + pwm1: pwm@10021000 {=0D + compatible =3D "sifive,fu540-c000-pwm", "sifive,pw= m0";=0D + reg =3D <0x0 0x10021000 0x0 0x1000>;=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <46 47 48 49>;=0D + clocks =3D <&prci PRCI_CLK_TLCLK>;=0D + #pwm-cells =3D <3>;=0D + status =3D "disabled";=0D + };=0D + l2cache: cache-controller@2010000 {=0D + compatible =3D "sifive,fu540-c000-ccache", "cache"= ;=0D + cache-block-size =3D <64>;=0D + cache-level =3D <2>;=0D + cache-sets =3D <1024>;=0D + cache-size =3D <2097152>;=0D + cache-unified;=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <1 2 3>;=0D + reg =3D <0x0 0x2010000 0x0 0x1000>;=0D + };=0D + gpio: gpio@10060000 {=0D + compatible =3D "sifive,fu540-c000-gpio", "sifive,g= pio0";=0D + interrupt-parent =3D <&plic0>;=0D + interrupts =3D <7>, <8>, <9>, <10>, <11>, <12>, <1= 3>,=0D + <14>, <15>, <16>, <17>, <18>, <19>, <= 20>,=0D + <21>, <22>;=0D + reg =3D <0x0 0x10060000 0x0 0x1000>;=0D + gpio-controller;=0D + #gpio-cells =3D <2>;=0D + interrupt-controller;=0D + #interrupt-cells =3D <2>;=0D + clocks =3D <&prci PRCI_CLK_TLCLK>;=0D + status =3D "disabled";=0D + };=0D + clint: clint@2000000 {=0D + compatible =3D "riscv,clint0";=0D + interrupts-extended =3D <&cpu0_intc 3 &cpu0_intc 7=0D + &cpu1_intc 3 &cpu1_intc 7=0D + &cpu2_intc 3 &cpu2_intc 7=0D + &cpu3_intc 3 &cpu3_intc 7>;=0D + reg =3D <0x0 0x2000000 0x0 0xc0000>;=0D + };=0D + };=0D +};=0D diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/h= ifive-unleashed-a00.dts b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board= /DeviceTree/hifive-unleashed-a00.dts new file mode 100644 index 0000000000..2074b18fa8 --- /dev/null +++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/hifive-u= nleashed-a00.dts @@ -0,0 +1,108 @@ +/**@file + U500 VC707 Device Tree + + SPDX-License-Identifier: (GPL-2.0 OR MIT) + Copyright (c) 2018-2019 SiFive, Inc + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "fu500-c000.dtsi" +#include "gpio.h" + +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + model =3D "SiFive HiFive Unleashed A00"; + compatible =3D "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; + + chosen { + stdout-path =3D "serial0"; + }; + + cpus { + timebase-frequency =3D ; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x2 0x00000000>; + }; + + soc { + }; + + hfclk: hfclk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <33333333>; + clock-output-names =3D "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D ; + clock-output-names =3D "rtcclk"; + }; + gpio-restart { + compatible =3D "gpio-restart"; + gpios =3D <&gpio 10 GPIO_ACTIVE_LOW>; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; +}; + +&qspi0 { + status =3D "okay"; + flash@0 { + compatible =3D "issi,is25wp256", "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <50000000>; + m25p,fast-read; + spi-tx-bus-width =3D <4>; + spi-rx-bus-width =3D <4>; + }; +}; + +&qspi2 { + status =3D "okay"; + mmc@0 { + compatible =3D "mmc-spi-slot"; + reg =3D <0>; + spi-max-frequency =3D <20000000>; + voltage-ranges =3D <3300 3300>; + disable-wp; + }; +}; + +ð0 { + status =3D "okay"; + phy-mode =3D "gmii"; + phy-handle =3D <&phy0>; + phy0: ethernet-phy@0 { + reg =3D <0>; + }; +}; + +&pwm0 { + status =3D "okay"; +}; + +&pwm1 { + status =3D "okay"; +}; + +&gpio { + status =3D "okay"; +}; --=20 2.31.1