* [edk2-platforms][PATCH 01/14] RiscVPlatformPkg/U500: Pass DTB from PEI to DXE
2021-11-15 2:56 [edk2-platforms][PATCH 00/14] Revise U500 for the latest RISC-V packages Abner Chang
@ 2021-11-15 2:56 ` Abner Chang
2021-11-15 2:56 ` [edk2-platforms][PATCH 02/14] RiscVPlatformPkg/U500: Fix up FDT and install into config table Abner Chang
` (13 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2021-11-15 2:56 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Add FdtPeim to build for passing DTB from PEI to DXE via
HOB.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc | 5 +++++
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf | 1 +
2 files changed, 6 insertions(+)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
index e680e330ed..e858b0bdea 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
@@ -149,6 +149,9 @@
RiscVPlatformTimerLib|Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf
CpuExceptionHandlerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
+ # Flattened Device Tree (FDT) access library
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+
[LibraryClasses.common.SEC]
!ifdef $(DEBUG_ON_SERIAL_PORT)
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
@@ -402,6 +405,8 @@
PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
}
+ Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf
+
#
# DXE Phase modules
#
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf
index 7db3a02bcb..b9d238994b 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf
@@ -100,6 +100,7 @@ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
# RISC-V Platform PEI Driver
INF Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
+INF Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf
################################################################################
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH 02/14] RiscVPlatformPkg/U500: Fix up FDT and install into config table
2021-11-15 2:56 [edk2-platforms][PATCH 00/14] Revise U500 for the latest RISC-V packages Abner Chang
2021-11-15 2:56 ` [edk2-platforms][PATCH 01/14] RiscVPlatformPkg/U500: Pass DTB from PEI to DXE Abner Chang
@ 2021-11-15 2:56 ` Abner Chang
2021-11-15 2:56 ` [edk2-platforms][PATCH 03/14] RiscVPlatformPkg/U500: Use FirmwareContext library Abner Chang
` (12 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2021-11-15 2:56 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
The Linux EFISTUB reads the FDT from the EFI system
configuration table. Before installing the FDT needs
to be patched with the booting hartid, because the kernel
in S-Mode cannot determine it.
Add RISC-V ProcessPkg/FdtDxe driver to build.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc | 2 +-
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
index e858b0bdea..8b7c851dbc 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
@@ -515,7 +515,7 @@
MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
-
+ Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf
#
# FAT filesystem + GPT/MBR partitioning + UDF filesystem
#
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf
index b9d238994b..cf9b673e97 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf
@@ -181,6 +181,7 @@ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
INF FatPkg/EnhancedFatDxe/Fat.inf
INF MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf
+INF Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf
!ifndef $(SOURCE_DEBUG_ENABLE)
INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH 03/14] RiscVPlatformPkg/U500: Use FirmwareContext library
2021-11-15 2:56 [edk2-platforms][PATCH 00/14] Revise U500 for the latest RISC-V packages Abner Chang
2021-11-15 2:56 ` [edk2-platforms][PATCH 01/14] RiscVPlatformPkg/U500: Pass DTB from PEI to DXE Abner Chang
2021-11-15 2:56 ` [edk2-platforms][PATCH 02/14] RiscVPlatformPkg/U500: Fix up FDT and install into config table Abner Chang
@ 2021-11-15 2:56 ` Abner Chang
2021-11-15 2:56 ` [edk2-platforms][PATCH 04/14] RiscVPlatformPkg/U500: Use generic platform library Abner Chang
` (11 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2021-11-15 2:56 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Use RISC-V FirmwareContext library to set and get the
pointer of PeiService on SiFive U5 series platforms.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
index 8b7c851dbc..e59fdda59f 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
@@ -177,6 +177,7 @@
[LibraryClasses.common.PEI_CORE]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+ RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
@@ -193,6 +194,7 @@
[LibraryClasses.common.PEIM]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+ RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH 04/14] RiscVPlatformPkg/U500: Use generic platform library
2021-11-15 2:56 [edk2-platforms][PATCH 00/14] Revise U500 for the latest RISC-V packages Abner Chang
` (2 preceding siblings ...)
2021-11-15 2:56 ` [edk2-platforms][PATCH 03/14] RiscVPlatformPkg/U500: Use FirmwareContext library Abner Chang
@ 2021-11-15 2:56 ` Abner Chang
2021-11-15 2:56 ` [edk2-platforms][PATCH 05/14] RiscVPlatformPkg/U500: Creates opensbi firmware domains Abner Chang
` (10 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2021-11-15 2:56 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Also removed the one under U500 package.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
.../FreedomU500VC707Board/U500.dsc | 2 +-
.../OpensbiPlatformLib/OpensbiPlatformLib.inf | 54 -----
.../Library/OpensbiPlatformLib/Platform.c | 206 ------------------
3 files changed, 1 insertion(+), 261 deletions(-)
delete mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
delete mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/Platform.c
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
index e59fdda59f..fb1b5b5d22 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
@@ -172,7 +172,7 @@
#
# OpenSBi Platform Library
#
- RiscVOpensbiPlatformLib|Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
+ RiscVOpensbiPlatformLib|Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
[LibraryClasses.common.PEI_CORE]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
deleted file mode 100644
index f38b339770..0000000000
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
+++ /dev/null
@@ -1,54 +0,0 @@
-## @file
-# RISC-V OpenSBI Platform Library
-# This is the the library which provides platform
-# level opensbi functions follow RISC-V OpenSBI implementation.
-#
-# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-[Defines]
- INF_VERSION = 0x0001001b
- BASE_NAME = RiscVOpensbiPlatformLib
- FILE_GUID = 9424ED54-EBDA-4FB5-8FF6-8291B07BB151
- MODULE_TYPE = SEC
- VERSION_STRING = 1.0
- LIBRARY_CLASS = RiscVOpensbiPlatformLib
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = RISCV64
-#
-
-[Sources]
- Platform.c
-
-[Packages]
- EmbeddedPkg/EmbeddedPkg.dec
- MdeModulePkg/MdeModulePkg.dec
- MdePkg/MdePkg.dec
- Platform/SiFive/U5SeriesPkg/U5SeriesPkg.dec
- Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
- Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
-
-[LibraryClasses]
- BaseLib
- BaseMemoryLib
- DebugLib
- DebugAgentLib
- FdtLib
- PcdLib
- PrintLib
- RiscVCpuLib
-
-[FixedPcd]
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber
- gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
-
- gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5UartBase
- gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/Platform.c b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/Platform.c
deleted file mode 100644
index b346eccaf0..0000000000
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/Platform.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- *
- * Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
- *
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2019 Western Digital Corporation or its affiliates.
- *
- * Authors:
- * Atish Patra <atish.patra@wdc.com>
- */
-
-#include <libfdt.h>
-#include <sbi/riscv_asm.h>
-#include <sbi/riscv_io.h>
-#include <sbi/riscv_encoding.h>
-#include <sbi/sbi_console.h>
-#include <sbi/sbi_const.h>
-#include <sbi/sbi_platform.h>
-#include <sbi_utils/fdt/fdt_fixup.h>
-#include <sbi_utils/irqchip/plic.h>
-#include <sbi_utils/serial/sifive-uart.h>
-#include <sbi_utils/sys/clint.h>
-#include <U5Clint.h>
-
-#define U500_HART_COUNT FixedPcdGet32(PcdHartCount)
-#define U500_BOOTABLE_HART_COUNT FixedPcdGet32(PcdBootableHartNumber)
-#define U500_HART_STACK_SIZE FixedPcdGet32(PcdOpenSbiStackSize)
-#define U500_BOOT_HART_ID FixedPcdGet32(PcdBootHartId)
-
-#define U500_SYS_CLK FixedPcdGet32(PcdU5PlatformSystemClock)
-
-#define U500_PLIC_ADDR 0xc000000
-#define U500_PLIC_NUM_SOURCES 0x35
-#define U500_PLIC_NUM_PRIORITIES 7
-
-#define U500_UART_ADDR FixedPcdGet32(PcdU5UartBase)
-
-#define U500_UART_BAUDRATE 115200
-
-/* PRCI clock related macros */
-//TODO: Do we need a separate driver for this ?
-#define U500_PRCI_BASE_ADDR 0x10000000
-#define U500_PRCI_CLKMUXSTATUSREG 0x002C
-#define U500_PRCI_CLKMUX_STATUS_TLCLKSEL (0x1 << 1)
-
-/* Full tlb flush always */
-#define U500_TLB_RANGE_FLUSH_LIMIT 0
-
-unsigned long log2roundup(unsigned long x);
-
-static struct plic_data plic = {
- .addr = U500_PLIC_ADDR,
- .num_src = U500_PLIC_NUM_SOURCES,
-};
-
-static struct clint_data clint = {
- .addr = CLINT_REG_BASE_ADDR,
- .first_hartid = 0,
- .hart_count = U500_HART_COUNT,
- .has_64bit_mmio = TRUE,
-};
-
-static void U500_modify_dt(void *fdt)
-{
- u32 i, size;
- int chosen_offset, err;
- int cpu_offset;
- char cpu_node[32] = "";
- const char *mmu_type;
-
- for (i = 0; i < U500_HART_COUNT; i++) {
- sbi_sprintf(cpu_node, "/cpus/cpu@%d", i);
- cpu_offset = fdt_path_offset(fdt, cpu_node);
- mmu_type = fdt_getprop(fdt, cpu_offset, "mmu-type", NULL);
- if (mmu_type && (!AsciiStrCmp(mmu_type, "riscv,sv39") ||
- !AsciiStrCmp(mmu_type,"riscv,sv48")))
- continue;
- else
- fdt_setprop_string(fdt, cpu_offset, "status", "masked");
- memset(cpu_node, 0, sizeof(cpu_node));
- }
- size = fdt_totalsize(fdt);
- err = fdt_open_into(fdt, fdt, size + 256);
- if (err < 0)
- sbi_printf("Device Tree can't be expanded to accmodate new node");
-
- chosen_offset = fdt_path_offset(fdt, "/chosen");
- fdt_setprop_string(fdt, chosen_offset, "stdout-path",
- "/soc/serial@10010000:115200");
-
- fdt_plic_fixup(fdt, "riscv,plic0");
-}
-
-static int U500_final_init(bool cold_boot)
-{
- void *fdt;
- struct sbi_scratch *ThisScratch;
-
- if (!cold_boot)
- return 0;
-
- fdt = sbi_scratch_thishart_arg1_ptr();
- U500_modify_dt(fdt);
- //
- // Set PMP of firmware regions to R and X. We will lock this in the end of PEI.
- // This region only protects SEC, PEI and Scratch buffer.
- //
- ThisScratch = sbi_scratch_thishart_ptr ();
- pmp_set(0, PMP_R | PMP_X | PMP_W, ThisScratch->fw_start, log2roundup (ThisScratch->fw_size));
- return 0;
-}
-
-static int U500_console_init(void)
-{
- unsigned long peri_in_freq;
-
- peri_in_freq = U500_SYS_CLK/2;
- return sifive_uart_init(U500_UART_ADDR, peri_in_freq, U500_UART_BAUDRATE);
-}
-
-static int U500_irqchip_init(bool cold_boot)
-{
- int rc;
- u32 hartid = current_hartid();
-
- if (cold_boot) {
- rc = plic_cold_irqchip_init(&plic);
- if (rc)
- return rc;
- }
-
- return plic_warm_irqchip_init(&plic,
- (hartid) ? (2 * hartid - 1) : 0,
- (hartid) ? (2 * hartid) : -1);
-}
-
-static int U500_ipi_init(bool cold_boot)
-{
- int rc;
-
- if (cold_boot) {
- rc = clint_cold_ipi_init(&clint);
- if (rc)
- return rc;
-
- }
-
- return clint_warm_ipi_init();
-}
-
-static u64 U500_get_tlbr_flush_limit(void)
-{
- return U500_TLB_RANGE_FLUSH_LIMIT;
-}
-
-static int U500_timer_init(bool cold_boot)
-{
- int rc;
-
- if (cold_boot) {
- rc = clint_cold_timer_init(&clint, NULL);
- if (rc)
- return rc;
- }
-
- return clint_warm_timer_init();
-}
-/**
- * The U500 SoC has 4 HARTs, Boot HART ID is determined by
- * PcdBootHartId.
- */
-static u32 u500_hart_index2id[U500_BOOTABLE_HART_COUNT] = {0, 1, 2, 3};
-
-static void U500_system_reset(u32 type, u32 second_param)
-{
- /* For now nothing to do. */
-}
-
-const struct sbi_platform_operations platform_ops = {
- .final_init = U500_final_init,
- .console_putc = sifive_uart_putc,
- .console_getc = sifive_uart_getc,
- .console_init = U500_console_init,
- .irqchip_init = U500_irqchip_init,
- .ipi_send = clint_ipi_send,
- .ipi_clear = clint_ipi_clear,
- .ipi_init = U500_ipi_init,
- .get_tlbr_flush_limit = U500_get_tlbr_flush_limit,
- .timer_value = clint_timer_value,
- .timer_event_stop = clint_timer_event_stop,
- .timer_event_start = clint_timer_event_start,
- .timer_init = U500_timer_init,
- .system_reset = U500_system_reset
-};
-
-const struct sbi_platform platform = {
- .opensbi_version = OPENSBI_VERSION, // The OpenSBI version this platform table is built bassed on.
- .platform_version = SBI_PLATFORM_VERSION(0x0001, 0x0000), // SBI Platform version 1.0
- .name = "SiFive Freedom U500",
- .features = SBI_PLATFORM_DEFAULT_FEATURES,
- .hart_count = U500_BOOTABLE_HART_COUNT,
- .hart_index2id = u500_hart_index2id,
- .hart_stack_size = U500_HART_STACK_SIZE,
- .platform_ops_addr = (unsigned long)&platform_ops
-};
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH 05/14] RiscVPlatformPkg/U500: Creates opensbi firmware domains
2021-11-15 2:56 [edk2-platforms][PATCH 00/14] Revise U500 for the latest RISC-V packages Abner Chang
` (3 preceding siblings ...)
2021-11-15 2:56 ` [edk2-platforms][PATCH 04/14] RiscVPlatformPkg/U500: Use generic platform library Abner Chang
@ 2021-11-15 2:56 ` Abner Chang
2021-11-15 2:56 ` [edk2-platforms][PATCH 06/14] RiscVPlatformPkg/U500: Uses RISC-V PeiCoreEntryPoint library Abner Chang
` (9 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2021-11-15 2:56 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Incorporate with opensbi to create three firmware domains,
- Addjust the ROM layout.
- Boot firmware domain, which built with opensbi library as M-mode access only region.
- Firmware domain which includes PEI and DXE regions, the
PMP attribute is readable, wriable and executable.
- EFI Variable region which is readable and writable.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
.../FreedomU500VC707Board/U500.fdf.inc | 73 ++++++++++++++-----
.../FreedomU500VC707Board/VarStore.fdf.inc | 6 +-
2 files changed, 57 insertions(+), 22 deletions(-)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc
index e88aee8c02..abfb013a92 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc
@@ -10,35 +10,70 @@
DEFINE BLOCK_SIZE = 0x1000
DEFINE FW_BASE_ADDRESS = 0x80000000
-DEFINE FW_SIZE = 0x00800000
-DEFINE FW_BLOCKS = 0x800
+DEFINE FW_SIZE = 0x00900000
+DEFINE FW_BLOCKS = 0x900
#
-# 0x000000-0x7DFFFF code
-# 0x7E0000-0x800000 variables
+# 0x000000-0x800000 code
+# 0x800000-0x818000 variables
#
DEFINE CODE_BASE_ADDRESS = 0x80000000
-DEFINE CODE_SIZE = 0x007E0000
-DEFINE CODE_BLOCKS = 0x7E0
+DEFINE CODE_SIZE = 0x00800000
+DEFINE CODE_BLOCKS = 0x800
DEFINE VARS_BLOCKS = 0x20
-DEFINE SECFV_OFFSET = 0x00000000
-DEFINE SECFV_SIZE = 0x00030000
-DEFINE PEIFV_OFFSET = 0x00030000
-DEFINE PEIFV_SIZE = 0x00080000
-DEFINE SCRATCH_OFFSET = 0x000b0000
-DEFINE SCRATCH_SIZE = 0x00010000
-DEFINE FVMAIN_OFFSET = 0x00100000 # Must be power of 2 for PMP setting
-DEFINE FVMAIN_SIZE = 0x0018C000
-DEFINE VARS_OFFSET = 0x007E0000
-DEFINE VARS_SIZE = 0x00020000
+#
+# SEC + opensbi library is the root FW domain.
+# The base address must be round up to log2.
+#
+DEFINE SECFV_OFFSET = 0x00000000
+DEFINE SECFV_SIZE = 0x00040000
+DEFINE ROOT_FW_DOMAIN_SIZE = $(SECFV_SIZE)
+
+#
+# Other FV regions are in the second FW domain.
+# The size of memory region must be power of 2.
+# The base address must be aligned with the size.
+#
+# FW memory region
+#
+DEFINE PEIFV_OFFSET = 0x00400000
+DEFINE PEIFV_SIZE = 0x00180000
+DEFINE FVMAIN_OFFSET = 0x00580000
+DEFINE FVMAIN_SIZE = 0x00280000
+
+#
+# EFI Variable memory region.
+# The total size of EFI Variable FD must include
+# all of sub regions of EFI Variable
+#
+DEFINE VARS_OFFSET = 0x00800000
+DEFINE VARS_SIZE = 0x00007000
+DEFINE VARS_FTW_WORKING_OFFSET = 0x00807000
+DEFINE VARS_FTW_WORKING_SIZE = 0x00001000
+DEFINE VARS_FTW_SPARE_OFFSET = 0x00808000
+DEFINE VARS_FTW_SPARE_SIZE = 0x00018000
+
+#
+# Scratch area memory region
+#
+DEFINE SCRATCH_OFFSET = 0x00840000
+DEFINE SCRATCH_SIZE = 0x00010000
+
+DEFINE FW_DOMAIN_SIZE = $(FVMAIN_OFFSET) + $(FVMAIN_SIZE) - $(PEIFV_OFFSET)
+DEFINE VARIABLE_FW_SIZE = $(VARS_FTW_SPARE_OFFSET) + $(VARS_FTW_SPARE_SIZE) - $(VARS_OFFSET)
+
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress = $(CODE_BASE_ADDRESS) + $(SECFV_OFFSET)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize = $(ROOT_FW_DOMAIN_SIZE)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress = $(CODE_BASE_ADDRESS) + $(PEIFV_OFFSET)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize = $(FW_DOMAIN_SIZE)
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress = $(FW_BASE_ADDRESS) + $(VARS_OFFSET)
-SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize = $(VARS_SIZE)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize = $(VARS_SIZE) + $(VARS_FTW_WORKING_SIZE) + $(VARS_FTW_SPARE_SIZE)
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize = $(BLOCK_SIZE)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress = $(CODE_BASE_ADDRESS) + $(VARS_OFFSET)
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize = $(VARIABLE_FW_SIZE)
-SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress = $(CODE_BASE_ADDRESS)
-SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress = $(CODE_BASE_ADDRESS) + $(SECFV_SIZE) + $(PEIFV_SIZE) + $(SCRATCH_SIZE)
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize = 8192
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase = $(CODE_BASE_ADDRESS) + $(SCRATCH_OFFSET)
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize = $(SCRATCH_SIZE)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/VarStore.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/VarStore.fdf.inc
index c287bb4336..d7d75fa494 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/VarStore.fdf.inc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/VarStore.fdf.inc
@@ -9,7 +9,7 @@
#
##
-$(VARS_OFFSET)|0x00007000
+$(VARS_OFFSET)|$(VARS_SIZE)
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
#
# NV_VARIABLE_STORE
@@ -56,7 +56,7 @@ DATA = {
0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}
-0x007e7000|0x00001000
+$(VARS_FTW_WORKING_OFFSET)|$(VARS_FTW_WORKING_SIZE)
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
#
#NV_FTW_WROK
@@ -72,7 +72,7 @@ DATA = {
0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}
-0x007e8000|0x00018000
+$(VARS_FTW_SPARE_OFFSET)|$(VARS_FTW_SPARE_SIZE)
gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
#
#NV_FTW_SPARE
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH 06/14] RiscVPlatformPkg/U500: Uses RISC-V PeiCoreEntryPoint library
2021-11-15 2:56 [edk2-platforms][PATCH 00/14] Revise U500 for the latest RISC-V packages Abner Chang
` (4 preceding siblings ...)
2021-11-15 2:56 ` [edk2-platforms][PATCH 05/14] RiscVPlatformPkg/U500: Creates opensbi firmware domains Abner Chang
@ 2021-11-15 2:56 ` Abner Chang
2021-11-15 2:56 ` [edk2-platforms][PATCH 07/14] RiscVPlatformPkg/U500: Use PlatormSecPpiLib Abner Chang
` (8 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2021-11-15 2:56 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
1. Use RISC-V PeiCoreEntryPoint library instance for opensbi
to switch to the next phase with arg0 as HART Id and arg1
as the SEC to PEI handoff data.
2. Introduce EDK2 opensbi platform operation functions.
With this, OEM can has its won platform initialization code
before and/or after opensbi vendor platform functions.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
index fb1b5b5d22..398da5238c 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
@@ -190,6 +190,8 @@
DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
!endif
PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ # RISC-V platform PEI core entry point.
+ PeiCoreEntryPoint|Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
[LibraryClasses.common.PEIM]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH 07/14] RiscVPlatformPkg/U500: Use PlatormSecPpiLib
2021-11-15 2:56 [edk2-platforms][PATCH 00/14] Revise U500 for the latest RISC-V packages Abner Chang
` (5 preceding siblings ...)
2021-11-15 2:56 ` [edk2-platforms][PATCH 06/14] RiscVPlatformPkg/U500: Uses RISC-V PeiCoreEntryPoint library Abner Chang
@ 2021-11-15 2:56 ` Abner Chang
2021-11-15 2:56 ` [edk2-platforms][PATCH 08/14] RiscVPlatformPkg/U500: U500 uses mtime CSR library Abner Chang
` (7 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2021-11-15 2:56 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Use PlatormSecPpiLib on U500 platform.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc | 1 +
1 file changed, 1 insertion(+)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
index 398da5238c..9c9a676de5 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
@@ -192,6 +192,7 @@
PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
# RISC-V platform PEI core entry point.
PeiCoreEntryPoint|Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ PlatformSecPpiLib|Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.inf
[LibraryClasses.common.PEIM]
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH 08/14] RiscVPlatformPkg/U500: U500 uses mtime CSR library
2021-11-15 2:56 [edk2-platforms][PATCH 00/14] Revise U500 for the latest RISC-V packages Abner Chang
` (6 preceding siblings ...)
2021-11-15 2:56 ` [edk2-platforms][PATCH 07/14] RiscVPlatformPkg/U500: Use PlatormSecPpiLib Abner Chang
@ 2021-11-15 2:56 ` Abner Chang
2021-11-15 2:56 ` [edk2-platforms][PATCH 09/14] RiscVPlatformPkg/U500: Determines hart number from DTB Abner Chang
` (6 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2021-11-15 2:56 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Use mtime CSR library interface to access mtime
CSR in Timer DXE driver.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc | 1 +
1 file changed, 1 insertion(+)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
index 9c9a676de5..587f1dfa62 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
@@ -147,6 +147,7 @@
RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
RiscVEdk2SbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.inf
RiscVPlatformTimerLib|Platform/SiFive/U5SeriesPkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf
+ MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
CpuExceptionHandlerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
# Flattened Device Tree (FDT) access library
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH 09/14] RiscVPlatformPkg/U500: Determines hart number from DTB
2021-11-15 2:56 [edk2-platforms][PATCH 00/14] Revise U500 for the latest RISC-V packages Abner Chang
` (7 preceding siblings ...)
2021-11-15 2:56 ` [edk2-platforms][PATCH 08/14] RiscVPlatformPkg/U500: U500 uses mtime CSR library Abner Chang
@ 2021-11-15 2:56 ` Abner Chang
2021-11-15 2:56 ` [edk2-platforms][PATCH 10/14] RiscVPlatformPkg/U500: Use NULL instance of RiscVSpecialPlatformLib Abner Chang
` (5 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2021-11-15 2:56 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Determine total number of HARTs from DTB instead of
using PCD. Also specify the desired boot HART ID.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
.../SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc
index abfb013a92..3b40f5486c 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc
@@ -83,10 +83,13 @@ SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize = 0x10000
SET gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz = 1000000
SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdU5PlatformSystemClock = 100000000 # 100Mhz system clock
-SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount = 4 # Total cores on U500 platform
SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber = 4 # The bootable hart core number.
# Which is incorporate with OpenSBI
# platform hart_index2id value.
+#
+# Use hart ID 0, 1, 2, 3
+#
+SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId = {0x0,0x1,0x2,0x3}
SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdNumberofU5Cores = 4 # Total U5 cores enabled on U500 platform
SET gSiFiveU5SeriesPlatformsPkgTokenSpaceGuid.PcdE5MCSupported = False # Enable optional E51 MC core?
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH 10/14] RiscVPlatformPkg/U500: Use NULL instance of RiscVSpecialPlatformLib
2021-11-15 2:56 [edk2-platforms][PATCH 00/14] Revise U500 for the latest RISC-V packages Abner Chang
` (8 preceding siblings ...)
2021-11-15 2:56 ` [edk2-platforms][PATCH 09/14] RiscVPlatformPkg/U500: Determines hart number from DTB Abner Chang
@ 2021-11-15 2:56 ` Abner Chang
2021-11-15 2:56 ` [edk2-platforms][PATCH 11/14] RiscVPlatformPkg/U500: Add device tree for U500 platform Abner Chang
` (4 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2021-11-15 2:56 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc | 1 +
1 file changed, 1 insertion(+)
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
index 587f1dfa62..9faa68fd6d 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
@@ -163,6 +163,7 @@
ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
Edk2OpensbiPlatformWrapperLib|Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf
+ RiscVSpecialPlatformLib|Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLibNull.inf
!ifdef $(SOURCE_DEBUG_ENABLE)
DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH 11/14] RiscVPlatformPkg/U500: Add device tree for U500 platform
2021-11-15 2:56 [edk2-platforms][PATCH 00/14] Revise U500 for the latest RISC-V packages Abner Chang
` (9 preceding siblings ...)
2021-11-15 2:56 ` [edk2-platforms][PATCH 10/14] RiscVPlatformPkg/U500: Use NULL instance of RiscVSpecialPlatformLib Abner Chang
@ 2021-11-15 2:56 ` Abner Chang
2021-11-15 2:56 ` [edk2-platforms][PATCH 12/14] RiscVPlatformPkg/U500: Add device tree to build Abner Chang
` (3 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2021-11-15 2:56 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
.../DeviceTree/U500DeviceTree.inf | 25 ++
.../FreedomU500VC707Board/DeviceTree/gpio.h | 45 +++
.../DeviceTree/sifive-fu500-prci.h | 19 ++
.../DeviceTree/fu500-c000.dtsi | 276 ++++++++++++++++++
.../DeviceTree/hifive-unleashed-a00.dts | 108 +++++++
5 files changed, 473 insertions(+)
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/U500DeviceTree.inf
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/gpio.h
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/sifive-fu500-prci.h
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/fu500-c000.dtsi
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/hifive-unleashed-a00.dts
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/U500DeviceTree.inf b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/U500DeviceTree.inf
new file mode 100644
index 0000000000..3eeb8c51f4
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/U500DeviceTree.inf
@@ -0,0 +1,25 @@
+## @file
+#
+# Device tree description of SiFive U500 VC707 platform
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = U500DeviceTree
+ FILE_GUID = 25462CDA-221F-47DF-AC1D-259CFAA4E326 # gDtPlatformDefaultDtbFileGuid
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ gpio.h
+ hifive-unleashed-a00.dts
+ fu500-c000.dtsi
+ sifive-fu500-prci.h
+
+[Packages]
+ MdePkg/MdePkg.dec
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/gpio.h b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/gpio.h
new file mode 100644
index 0000000000..bc7e2fe7a1
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/gpio.h
@@ -0,0 +1,45 @@
+/** @file
+ This header provides constants for most GPIO bindings.
+
+ Most GPIO bindings include a flags cell as part of the GPIO specifier.
+ In most cases, the format of the flags cell uses the standard values
+ defined in this header.
+
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef DT_BINDINGS_GPIO_GPIO_H_
+#define DT_BINDINGS_GPIO_GPIO_H_
+
+/* Bit 0 express polarity */
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
+/* Bit 1 express single-endedness */
+#define GPIO_PUSH_PULL 0
+#define GPIO_SINGLE_ENDED 2
+
+/* Bit 2 express Open drain or open source */
+#define GPIO_LINE_OPEN_SOURCE 0
+#define GPIO_LINE_OPEN_DRAIN 4
+
+//
+// Open Drain/Collector is the combination of single-ended open drain interface.
+// Open Source/Emitter is the combination of single-ended open source interface.
+//
+#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)
+#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)
+
+/* Bit 3 express GPIO suspend/resume and reset persistence */
+#define GPIO_PERSISTENT 0
+#define GPIO_TRANSITORY 8
+
+/* Bit 4 express pull up */
+#define GPIO_PULL_UP 16
+
+/* Bit 5 express pull down */
+#define GPIO_PULL_DOWN 32
+
+#endif
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/sifive-fu500-prci.h b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/sifive-fu500-prci.h
new file mode 100644
index 0000000000..7efa0006a0
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/sifive-fu500-prci.h
@@ -0,0 +1,19 @@
+/**@file
+
+ SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ Copyright (c) 2018-2019 SiFive, Inc
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU500_PRCI_H
+#define __DT_BINDINGS_CLOCK_SIFIVE_FU500_PRCI_H
+
+/* Clock indexes for use by Device Tree data and the PRCI driver */
+
+#define PRCI_CLK_COREPLL 0
+#define PRCI_CLK_DDRPLL 1
+#define PRCI_CLK_GEMGXLPLL 2
+#define PRCI_CLK_TLCLK 3
+
+#endif
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/fu500-c000.dtsi b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/fu500-c000.dtsi
new file mode 100644
index 0000000000..82f10e71e0
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/fu500-c000.dtsi
@@ -0,0 +1,276 @@
+/**@file
+ U500 VC707 Device Tree, compatible with fu540-c000 platform.
+
+ SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ Copyright (c) 2018-2019 SiFive, Inc
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/dts-v1/;
+
+#include "sifive-fu500-prci.h"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,fu540-c000", "sifive,fu540";
+
+ aliases {
+ serial0 = &uart0;
+ ethernet0 = ð0;
+ };
+
+ chosen {
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu0: cpu@0 {
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <0>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ next-level-cache = <&l2cache>;
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu1: cpu@1 {
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ next-level-cache = <&l2cache>;
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu2: cpu@2 {
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <2>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ next-level-cache = <&l2cache>;
+ cpu2_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu3: cpu@3 {
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <3>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ next-level-cache = <&l2cache>;
+ cpu3_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
+ ranges;
+ plic0: interrupt-controller@c000000 {
+ #interrupt-cells = <1>;
+ compatible = "sifive,plic-1.0.0";
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ riscv,ndev = <53>;
+ interrupt-controller;
+ interrupts-extended = <
+ &cpu0_intc 0xffffffff &cpu0_intc 9
+ &cpu1_intc 0xffffffff &cpu1_intc 9
+ &cpu2_intc 0xffffffff &cpu2_intc 9
+ &cpu3_intc 0xffffffff &cpu3_intc 9>;
+ };
+ prci: clock-controller@10000000 {
+ compatible = "sifive,fu540-c000-prci";
+ reg = <0x0 0x10000000 0x0 0x1000>;
+ clocks = <&hfclk>, <&rtcclk>;
+ #clock-cells = <1>;
+ };
+ uart0: serial@54000000 {
+ compatible = "sifive,fu540-c000-uart", "sifive,uart0";
+ reg = <0x0 0x54000000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <4>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ status = "disabled";
+ };
+ dma: dma@3000000 {
+ compatible = "sifive,fu540-c000-pdma";
+ reg = <0x0 0x3000000 0x0 0x8000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <23 24 25 26 27 28 29 30>;
+ #dma-cells = <1>;
+ };
+ i2c0: i2c@10030000 {
+ compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
+ reg = <0x0 0x10030000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <50>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ reg-shift = <2>;
+ reg-io-width = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ qspi0: spi@10040000 {
+ compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10040000 0x0 0x1000
+ 0x0 0x20000000 0x0 0x10000000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <51>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ qspi1: spi@10041000 {
+ compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10041000 0x0 0x1000
+ 0x0 0x30000000 0x0 0x10000000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <52>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ qspi2: spi@10050000 {
+ compatible = "sifive,fu540-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10050000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <6>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ eth0: ethernet@10090000 {
+ compatible = "sifive,fu540-c000-gem";
+ interrupt-parent = <&plic0>;
+ interrupts = <53>;
+ reg = <0x0 0x10090000 0x0 0x2000
+ 0x0 0x100a0000 0x0 0x1000>;
+ local-mac-address = [00 00 00 00 00 00];
+ clock-names = "pclk", "hclk";
+ clocks = <&prci PRCI_CLK_GEMGXLPLL>,
+ <&prci PRCI_CLK_GEMGXLPLL>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ pwm0: pwm@10020000 {
+ compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
+ reg = <0x0 0x10020000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <42 43 44 45>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+ pwm1: pwm@10021000 {
+ compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
+ reg = <0x0 0x10021000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <46 47 48 49>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+ l2cache: cache-controller@2010000 {
+ compatible = "sifive,fu540-c000-ccache", "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <1024>;
+ cache-size = <2097152>;
+ cache-unified;
+ interrupt-parent = <&plic0>;
+ interrupts = <1 2 3>;
+ reg = <0x0 0x2010000 0x0 0x1000>;
+ };
+ gpio: gpio@10060000 {
+ compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
+ interrupt-parent = <&plic0>;
+ interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>,
+ <14>, <15>, <16>, <17>, <18>, <19>, <20>,
+ <21>, <22>;
+ reg = <0x0 0x10060000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&prci PRCI_CLK_TLCLK>;
+ status = "disabled";
+ };
+ clint: clint@2000000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
+ &cpu1_intc 3 &cpu1_intc 7
+ &cpu2_intc 3 &cpu2_intc 7
+ &cpu3_intc 3 &cpu3_intc 7>;
+ reg = <0x0 0x2000000 0x0 0xc0000>;
+ };
+ };
+};
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/hifive-unleashed-a00.dts b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/hifive-unleashed-a00.dts
new file mode 100644
index 0000000000..2074b18fa8
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/hifive-unleashed-a00.dts
@@ -0,0 +1,108 @@
+/**@file
+ U500 VC707 Device Tree
+
+ SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ Copyright (c) 2018-2019 SiFive, Inc
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "fu500-c000.dtsi"
+#include "gpio.h"
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+#define RTCCLK_FREQ 1000000
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "SiFive HiFive Unleashed A00";
+ compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ cpus {
+ timebase-frequency = <RTCCLK_FREQ>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x2 0x00000000>;
+ };
+
+ soc {
+ };
+
+ hfclk: hfclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <33333333>;
+ clock-output-names = "hfclk";
+ };
+
+ rtcclk: rtcclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <RTCCLK_FREQ>;
+ clock-output-names = "rtcclk";
+ };
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&qspi0 {
+ status = "okay";
+ flash@0 {
+ compatible = "issi,is25wp256", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
+&qspi2 {
+ status = "okay";
+ mmc@0 {
+ compatible = "mmc-spi-slot";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ voltage-ranges = <3300 3300>;
+ disable-wp;
+ };
+};
+
+ð0 {
+ status = "okay";
+ phy-mode = "gmii";
+ phy-handle = <&phy0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&gpio {
+ status = "okay";
+};
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH 12/14] RiscVPlatformPkg/U500: Add device tree to build
2021-11-15 2:56 [edk2-platforms][PATCH 00/14] Revise U500 for the latest RISC-V packages Abner Chang
` (10 preceding siblings ...)
2021-11-15 2:56 ` [edk2-platforms][PATCH 11/14] RiscVPlatformPkg/U500: Add device tree for U500 platform Abner Chang
@ 2021-11-15 2:56 ` Abner Chang
2021-11-15 2:56 ` [edk2-platforms][PATCH 13/14] Platform/RISC-V: Add debug message to SecMain.c Abner Chang
` (2 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2021-11-15 2:56 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
.../FreedomU500VC707Board/U500.dsc | 2 ++
.../FreedomU500VC707Board/U500.fdf | 6 ++++
.../FreedomU500VC707Board/DeviceTree.fdf.inc | 33 +++++++++++++++++++
.../FreedomU500VC707Board/U500.fdf.inc | 8 ++++-
4 files changed, 48 insertions(+), 1 deletion(-)
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree.fdf.inc
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
index 9faa68fd6d..318851332a 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
@@ -503,6 +503,8 @@
MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+ Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/U500DeviceTree.inf
+
#
# SMBIOS Support
#
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf
index cf9b673e97..4ce192799f 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf
@@ -33,6 +33,7 @@ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|gUefiRiscVPlatformPkgToken
FV = FVMAIN_COMPACT
!include VarStore.fdf.inc
+!include DeviceTree.fdf.inc
################################################################################
@@ -327,3 +328,8 @@ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
RAW ACPI |.acpi
RAW ASL |.aml
}
+
+[Rule.Common.USER_DEFINED.DTB]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW BIN |.dtb
+ }
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree.fdf.inc
new file mode 100644
index 0000000000..5ddaa6b8f2
--- /dev/null
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree.fdf.inc
@@ -0,0 +1,33 @@
+## @file
+# FDF include file with Layout Regions that define an empty variable store.
+#
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+$(DTB_OFFSET)|$(DTB_SIZE)
+gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase|gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvSize
+FV = DTBFV
+
+[FV.DTBFV]
+BlockSize = 0x1000
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+INF RuleOverride = DTB Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/U500DeviceTree.inf
diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc
index 3b40f5486c..d7da76f4d3 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.fdf.inc
@@ -54,10 +54,16 @@ DEFINE VARS_FTW_WORKING_SIZE = 0x00001000
DEFINE VARS_FTW_SPARE_OFFSET = 0x00808000
DEFINE VARS_FTW_SPARE_SIZE = 0x00018000
+#
+# Device Tree memory region
+#
+DEFINE DTB_OFFSET = 0x00840000
+DEFINE DTB_SIZE = 0x00002000
+
#
# Scratch area memory region
#
-DEFINE SCRATCH_OFFSET = 0x00840000
+DEFINE SCRATCH_OFFSET = 0x00880000
DEFINE SCRATCH_SIZE = 0x00010000
DEFINE FW_DOMAIN_SIZE = $(FVMAIN_OFFSET) + $(FVMAIN_SIZE) - $(PEIFV_OFFSET)
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH 13/14] Platform/RISC-V: Add debug message to SecMain.c
2021-11-15 2:56 [edk2-platforms][PATCH 00/14] Revise U500 for the latest RISC-V packages Abner Chang
` (11 preceding siblings ...)
2021-11-15 2:56 ` [edk2-platforms][PATCH 12/14] RiscVPlatformPkg/U500: Add device tree to build Abner Chang
@ 2021-11-15 2:56 ` Abner Chang
2021-11-15 2:56 ` [edk2-platforms][PATCH 14/14] Platform/RISC-V: Initialize variable to zero Abner Chang
2021-11-22 11:40 ` [edk2-platforms][PATCH 00/14] Revise U500 for the latest RISC-V packages Daniel Schaefer
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2021-11-15 2:56 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Add more debug messages when search FFS in SEC phase.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
.../RISC-V/PlatformPkg/Universal/Sec/SecMain.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
index 17f33a02cc..05f228c44d 100644
--- a/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
+++ b/Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
@@ -166,6 +166,8 @@ FindFfsFileAndSection (
UINT32 Size;
EFI_PHYSICAL_ADDRESS EndOfFile;
+ DEBUG ((DEBUG_INFO, "%a: DBT FV at 0x%x\n", __FUNCTION__, Fv));
+
if (Fv->Signature != EFI_FVH_SIGNATURE) {
DEBUG ((DEBUG_ERROR, "%a: FV at %p does not have FV header signature\n", __FUNCTION__, Fv));
return EFI_VOLUME_CORRUPTED;
@@ -181,17 +183,20 @@ FindFfsFileAndSection (
CurrentAddress = (EndOfFile + 7) & ~(7ULL);
if (CurrentAddress > EndOfFirmwareVolume) {
+ DEBUG ((DEBUG_ERROR, "%a: FV corrupted\n", __FUNCTION__));
return EFI_VOLUME_CORRUPTED;
}
File = (EFI_FFS_FILE_HEADER*)(UINTN) CurrentAddress;
Size = *(UINT32*) File->Size & 0xffffff;
if (Size < (sizeof (*File) + sizeof (EFI_COMMON_SECTION_HEADER))) {
+ DEBUG ((DEBUG_ERROR, "%a: FV corrupted\n", __FUNCTION__));
return EFI_VOLUME_CORRUPTED;
}
EndOfFile = CurrentAddress + Size;
if (EndOfFile > EndOfFirmwareVolume) {
+ DEBUG ((DEBUG_ERROR, "%a: FV corrupted\n", __FUNCTION__));
return EFI_VOLUME_CORRUPTED;
}
@@ -199,6 +204,7 @@ FindFfsFileAndSection (
// Look for the request file type
//
if (File->Type != FileType) {
+ DEBUG ((DEBUG_INFO, "%a: (File->Type != FileType), find next FFS\n", __FUNCTION__));
continue;
}
@@ -208,9 +214,15 @@ FindFfsFileAndSection (
SectionType,
FoundSection
);
- if (!EFI_ERROR (Status) || (Status == EFI_VOLUME_CORRUPTED)) {
+ if (!EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_INFO, "%a: Get firmware file section\n", __FUNCTION__));
+ return Status;
+ }
+ if (Status == EFI_VOLUME_CORRUPTED) {
+ DEBUG ((DEBUG_ERROR, "%a: FV corrupted\n", __FUNCTION__));
return Status;
}
+ DEBUG ((DEBUG_INFO, "%a: Find next FFS\n", __FUNCTION__));
}
}
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [edk2-platforms][PATCH 14/14] Platform/RISC-V: Initialize variable to zero
2021-11-15 2:56 [edk2-platforms][PATCH 00/14] Revise U500 for the latest RISC-V packages Abner Chang
` (12 preceding siblings ...)
2021-11-15 2:56 ` [edk2-platforms][PATCH 13/14] Platform/RISC-V: Add debug message to SecMain.c Abner Chang
@ 2021-11-15 2:56 ` Abner Chang
2021-11-22 11:40 ` [edk2-platforms][PATCH 00/14] Revise U500 for the latest RISC-V packages Daniel Schaefer
14 siblings, 0 replies; 16+ messages in thread
From: Abner Chang @ 2021-11-15 2:56 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Daniel Schaefer, Sunil V L
Initialize variable NumberOfPlatformInArray to 0.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
.../RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
index 18c152001c..f64bde4535 100644
--- a/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
+++ b/Platform/RISC-V/PlatformPkg/Library/RiscVSpecialPlatformLibNull/RiscVSpecialPlatformLib.c
@@ -16,5 +16,5 @@
const struct platform_override *special_platforms = NULL;
const struct platform_override *SpecialPlatformArray = NULL;
-INTN NumberOfPlaformsInArray;
+INTN NumberOfPlaformsInArray = 0;
--
2.31.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [edk2-platforms][PATCH 00/14] Revise U500 for the latest RISC-V packages.
2021-11-15 2:56 [edk2-platforms][PATCH 00/14] Revise U500 for the latest RISC-V packages Abner Chang
` (13 preceding siblings ...)
2021-11-15 2:56 ` [edk2-platforms][PATCH 14/14] Platform/RISC-V: Initialize variable to zero Abner Chang
@ 2021-11-22 11:40 ` Daniel Schaefer
14 siblings, 0 replies; 16+ messages in thread
From: Daniel Schaefer @ 2021-11-22 11:40 UTC (permalink / raw)
To: Chang, Abner (HPS SW/FW Technologist), devel@edk2.groups.io; +Cc: Sunil V L
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Great! U500 confirmed working again and cleanup through generic code.
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
________________________________
From: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
Sent: Monday, November 15, 2021 10:56
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>; Schaefer, Daniel (ROM Janitor) <daniel.schaefer@hpe.com>; Sunil V L <sunilvl@ventanamicro.com>
Subject: [edk2-platforms][PATCH 00/14] Revise U500 for the latest RISC-V packages.
Incorporate U500 platform with the latest RISC-V ProcessPkg and PlatformPkg.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Abner Chang (14):
RiscVPlatformPkg/U500: Pass DTB from PEI to DXE
RiscVPlatformPkg/U500: Fix up FDT and install into config table
RiscVPlatformPkg/U500: Use FirmwareContext library
RiscVPlatformPkg/U500: Use generic platform library
RiscVPlatformPkg/U500: Creates opensbi firmware domains
RiscVPlatformPkg/U500: Uses RISC-V PeiCoreEntryPoint library
RiscVPlatformPkg/U500: Use PlatormSecPpiLib
RiscVPlatformPkg/U500: U500 uses mtime CSR library
RiscVPlatformPkg/U500: Determines hart number from DTB
RiscVPlatformPkg/U500: Use NULL instance of RiscVSpecialPlatformLib
RiscVPlatformPkg/U500: Add device tree for U500 platform
RiscVPlatformPkg/U500: Add device tree to build
Platform/RISC-V: Add debug message to SecMain.c
Platform/RISC-V: Initialize variable to zero
.../FreedomU500VC707Board/U500.dsc | 18 +-
.../FreedomU500VC707Board/U500.fdf | 8 +
.../FreedomU500VC707Board/DeviceTree.fdf.inc | 33 +++
.../FreedomU500VC707Board/U500.fdf.inc | 84 ++++--
.../FreedomU500VC707Board/VarStore.fdf.inc | 6 +-
.../DeviceTree/U500DeviceTree.inf | 25 ++
.../OpensbiPlatformLib/OpensbiPlatformLib.inf | 54 ----
.../FreedomU500VC707Board/DeviceTree/gpio.h | 45 +++
.../DeviceTree/sifive-fu500-prci.h | 19 ++
.../RiscVSpecialPlatformLib.c | 2 +-
.../PlatformPkg/Universal/Sec/SecMain.c | 14 +-
.../Library/OpensbiPlatformLib/Platform.c | 206 -------------
.../DeviceTree/fu500-c000.dtsi | 276 ++++++++++++++++++
.../DeviceTree/hifive-unleashed-a00.dts | 108 +++++++
14 files changed, 611 insertions(+), 287 deletions(-)
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree.fdf.inc
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/U500DeviceTree.inf
delete mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/gpio.h
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/sifive-fu500-prci.h
delete mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/Library/OpensbiPlatformLib/Platform.c
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/fu500-c000.dtsi
create mode 100644 Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/DeviceTree/hifive-unleashed-a00.dts
--
2.31.1
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