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From: "Nhi Pham" <nhi@os.amperecomputing.com>
To: devel@edk2.groups.io
CC: patches@amperecomputing.com,
nhi@os.amperecomputing.com,
vunguyen@os.amperecomputing.com,
Thang Nguyen <thang@os.amperecomputing.com>,
Chuong Tran <chuong@os.amperecomputing.com>,
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Subject: [edk2-platforms][PATCH v5 10/30] AmpereAltraPkg: Add Root Complex HOB data structures
Date: Wed, 17 Nov 2021 23:47:07 +0700
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From: Vu Nguyen <vunguyen@os.amperecomputing.com>
Provide common data structures and macros which will be consumed by
various PCIe modules.
Cc: Thang Nguyen <thang@os.amperecomputing.com>
Cc: Chuong Tran <chuong@os.amperecomputing.com>
Cc: Phong Vo <phong@os.amperecomputing.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
---
Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec | 3 +
Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h | 140 ++++=
++++++++++++++++
2 files changed, 143 insertions(+)
diff --git a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec b/Silicon/Amp=
ere/AmpereAltraPkg/AmpereAltraPkg.dec
index c1226c296dad..e19925c68a0e 100644
--- a/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
+++ b/Silicon/Ampere/AmpereAltraPkg/AmpereAltraPkg.dec
@@ -52,3 +52,6 @@ [Guids]
=20
## Include/Guid/PlatformInfoHob.h
gPlatformInfoHobGuid =3D { 0x7f73e372, 0x7183, 0x4022, { 0xb3, 0=
x76, 0x78, 0x30, 0x32, 0x6d, 0x79, 0xb4 } }
+
+ ## Include/Guid/RootComplexInfoHob.h
+ gRootComplexInfoHobGuid =3D { 0x568a258a, 0xcaa1, 0x47e9, { 0xbb, 0=
x89, 0x65, 0xa3, 0x73, 0x9b, 0x58, 0x75 } }
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.=
h b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h
new file mode 100644
index 000000000000..24599b781646
--- /dev/null
+++ b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h
@@ -0,0 +1,140 @@
+/** @file
+
+ Copyright (c) 2021, Ampere Computing LLC. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef ROOT_COMPLEX_INFO_HOB_H_
+#define ROOT_COMPLEX_INFO_HOB_H_
+
+#define ROOT_COMPLEX_INFO_HOB_GUID \
+ { 0x568a258a, 0xcaa1, 0x47e9, { 0xbb, 0x89, 0x65, 0xa3, 0x73, 0x9b, 0x58=
, 0x75 } }
+
+extern GUID gRootComplexInfoHobGuid;
+
+#define PRESET_INVALID 0xFF
+
+//
+// PCIe link width
+//
+#define LINK_WIDTH_NONE 0x00
+#define LINK_WIDTH_X1 0x01
+#define LINK_WIDTH_X2 0x02
+#define LINK_WIDTH_X4 0x04
+#define LINK_WIDTH_X8 0x08
+#define LINK_WIDTH_X16 0x10
+
+//
+// PCIe link speed
+//
+#define LINK_SPEED_NONE 0x00
+#define LINK_SPEED_GEN1 0x01
+#define LINK_SPEED_GEN2 0x02
+#define LINK_SPEED_GEN3 0x04
+#define LINK_SPEED_GEN4 0x08
+
+typedef enum {
+ DevMapMode1 =3D 0,
+ DevMapMode2,
+ DevMapMode3,
+ DevMapMode4,
+ MaxDevMapMode =3D DevMapMode4
+} DEV_MAP_MODE;
+
+//
+// PCIe controller index
+//
+typedef enum {
+ PcieController0 =3D 0,
+ PcieController1,
+ PcieController2,
+ PcieController3,
+ PcieController4,
+ MaxPcieControllerOfRootComplexA =3D PcieController4,
+ PcieController5,
+ PcieController6,
+ PcieController7,
+ MaxPcieController,
+ MaxPcieControllerOfRootComplexB =3D MaxPcieController
+} AC01_PCIE_CONTROLLER_INDEX;
+
+//
+// Root Complex type
+//
+typedef enum {
+ RootComplexTypeA,
+ RootComplexTypeB,
+ MaxRootComplexType =3D RootComplexTypeB
+} AC01_ROOT_COMPLEX_TYPE;
+
+//
+// Root Complex index
+//
+typedef enum {
+ RootComplexA0 =3D 0,
+ RootComplexA1,
+ RootComplexA2,
+ RootComplexA3,
+ MaxRootComplexA,
+ RootComplexB0 =3D MaxRootComplexA,
+ RootComplexB1,
+ RootComplexB2,
+ RootComplexB3,
+ MaxRootComplex,
+ MaxRootComplexB =3D MaxRootComplex
+} AC01_ROOT_COMPLEX_INDEX;
+
+#pragma pack(1)
+
+//
+// Data structure to store the PCIe controller information
+//
+typedef struct {
+ PHYSICAL_ADDRESS CsrBase; // Base address of CSR block
+ PHYSICAL_ADDRESS SnpsRamBase; // Base address of Synopsys SRA=
M
+ UINT8 MaxGen; // Max speed Gen-1/-2/-3/-4
+ UINT8 CurrentGen; // Current speed Gen-1/-2/-3/-4
+ UINT8 MaxWidth; // Max lanes x2/x4/x8/x16
+ UINT8 CurWidth; // Current lanes x2/x4/x8/x16
+ UINT8 ID; // ID of the controller within =
Root Complex
+ UINT8 DevNum; // Device number as part of Bus=
:Dev:Func
+ BOOLEAN Active; // Active? Used in bi-furcation=
mode
+ BOOLEAN LinkUp; // PHY and PCIE linkup
+ BOOLEAN HotPlug; // Hotplug support
+} AC01_PCIE_CONTROLLER;
+
+//
+// Data structure to store the Root Complex information
+//
+typedef struct {
+ PHYSICAL_ADDRESS CsrBase;
+ PHYSICAL_ADDRESS TcuBase;
+ PHYSICAL_ADDRESS HostBridgeBase;
+ PHYSICAL_ADDRESS SerdesBase;
+ PHYSICAL_ADDRESS MmcfgBase;
+ PHYSICAL_ADDRESS MmioBase;
+ PHYSICAL_ADDRESS MmioSize;
+ PHYSICAL_ADDRESS Mmio32Base;
+ PHYSICAL_ADDRESS Mmio32Size;
+ AC01_PCIE_CONTROLLER Pcie[MaxPcieController];
+ UINT8 MaxPcieController;
+ AC01_ROOT_COMPLEX_TYPE Type;
+ UINT8 ID;
+ DEV_MAP_MODE DevMapHigh:3; // Copy of High Devmap pr=
ogrammed to Host bridge
+ DEV_MAP_MODE DevMapLow:3; // Copy of Low Devmap pro=
grammed to Host bridge
+ DEV_MAP_MODE DefaultDevMapHigh:3; // Default of High devmap=
based on board settings
+ DEV_MAP_MODE DefaultDevMapLow:3; // Default of Low devmap =
based on board settings
+ UINT8 Socket;
+ BOOLEAN Active;
+ BOOLEAN DefaultActive;
+ UINT16 Logical;
+ UINT32 Flags;
+ UINT8 PresetGen3[MaxPcieController];
+ UINT8 PresetGen4[MaxPcieController];
+} AC01_ROOT_COMPLEX;
+
+#pragma pack()
+
+#endif /* ROOT_COMPLEX_INFO_HOB_H_ */
--=20
2.17.1